JP2001111050A - Vertical semiconductor device - Google Patents

Vertical semiconductor device

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Publication number
JP2001111050A
JP2001111050A JP29076599A JP29076599A JP2001111050A JP 2001111050 A JP2001111050 A JP 2001111050A JP 29076599 A JP29076599 A JP 29076599A JP 29076599 A JP29076599 A JP 29076599A JP 2001111050 A JP2001111050 A JP 2001111050A
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JP
Japan
Prior art keywords
type
region
semiconductor region
effect transistor
mos field
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP29076599A
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Japanese (ja)
Other versions
JP4924781B2 (en
Inventor
Yoshikuni Hatsutori
佳晋 服部
Takashi Suzuki
隆司 鈴木
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Toyota Central R&D Labs Inc
Original Assignee
Toyota Central R&D Labs Inc
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Priority to JP29076599A priority Critical patent/JP4924781B2/en
Publication of JP2001111050A publication Critical patent/JP2001111050A/en
Application granted granted Critical
Publication of JP4924781B2 publication Critical patent/JP4924781B2/en
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Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0878—Impurity concentration or distribution
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a vertical MOS field effect transistor which can lower its ON resistance and have a high withstand voltage. SOLUTION: By increasing an (n) type impurity concentration in an n+ type drift region 21, an ON resistance is lowered. In an OFF state, a depletion layer extended from a junction part 23 and a depletion layer extended from a side face of a trench 19 are spread in the drift region 21. The depletion layer extended from the junction part 23 is also spread in a p- type silicon single crystalline region 17. As a result, since the drift region 21 and single crystalline region 17 can be completely depleted, there can be obtained a vertical n+ type MOS field effect transistor 1 which has a high withstand voltage.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、例えば、パワーエ
レクトロニクスに用いることができる縦型半導体装置に
関する。The present invention relates to a vertical semiconductor device that can be used, for example, in power electronics.

【０００２】[0002]

【背景技術および発明が解決しようとする課題】縦型Ｍ
ＯＳ（Metal Oxide Semiconductor）電界効果トランジ
スタは、例えば、家庭用電気機器や自動車のモータの電
力変換や電力制御に使われる半導体素子の一種である。
縦型ＭＯＳ電界効果トランジスタは、電力用に使用され
るので、高耐圧である必要がある。また、縦型ＭＯＳ電
界効果トランジスタの低消費電力化のためには、縦型Ｍ
ＯＳ電界効果トランジスタのＯＮ動作時の抵抗を下げる
必要がある。このように、縦型ＭＯＳ電界効果トランジ
スタの特性としては、高耐圧で、かつＯＮ抵抗が低い、
ことが求められる。2. Description of the Related Art Vertical M
An OS (Metal Oxide Semiconductor) field-effect transistor is a type of semiconductor element used for power conversion and power control of, for example, home electric appliances and motors of automobiles.
Since the vertical MOS field effect transistor is used for electric power, it needs to have a high breakdown voltage. In order to reduce the power consumption of the vertical MOS field effect transistor, the vertical M
It is necessary to reduce the resistance of the OS field-effect transistor during the ON operation. As described above, the characteristics of the vertical MOS field-effect transistor include a high withstand voltage and a low ON resistance.
Is required.

【０００３】ところで、縦型ＭＯＳ電界効果トランジス
タにおいて、ドリフト領域に形成された空乏層により、
その絶縁破壊を防いでいる。縦型ＭＯＳ電界効果トラン
ジスタを高耐圧にするには、空乏層の延びを大きくする
必要がある。このためには、ドリフト領域の不純物濃度
を低くしなければならない。In a vertical MOS field effect transistor, a depletion layer formed in a drift region causes
The dielectric breakdown is prevented. In order to increase the breakdown voltage of the vertical MOS field effect transistor, it is necessary to increase the extension of the depletion layer. For this purpose, the impurity concentration in the drift region must be reduced.

【０００４】しかし、ドリフト領域の不純物濃度を低く
すると、ドリフト領域の抵抗が上昇し、それにより、縦
型ＭＯＳ電界効果トランジスタのＯＮ抵抗が上昇する。However, when the impurity concentration of the drift region is reduced, the resistance of the drift region increases, and as a result, the ON resistance of the vertical MOS field effect transistor increases.

【０００５】このように、縦型ＭＯＳ電界効果トランジ
スタにおいては、高耐圧にするとＯＮ抵抗が上昇し、Ｏ
Ｎ抵抗を下げようとすると耐圧が低下するという、耐圧
とＯＮ抵抗との間にはトレードオフの関係がある。As described above, in a vertical MOS field-effect transistor, when the breakdown voltage is increased, the ON resistance increases, and
There is a trade-off relationship between the withstand voltage and the ON resistance in that the withstand voltage decreases when the N resistance is reduced.

【０００６】本発明の目的は、ＯＮ抵抗を下げつつ、高
耐圧にすることができる縦型半導体装置を提供すること
である。An object of the present invention is to provide a vertical semiconductor device capable of achieving a high withstand voltage while reducing the ON resistance.

【０００７】[0007]

【課題を解決するための手段】本発明は、縦型半導体装
置であって、第１導電型の第１半導体領域、第１導電型
の第２半導体領域、トレンチおよび第２導電型の第３半
導体領域を備え、前記第１半導体領域には、チャネルが
形成され、前記第２半導体領域は、第１導電型の不純物
が低濃度であり、前記第３半導体領域は、前記トレンチ
と前記第２半導体領域との間に位置し、前記第３半導体
領域は、前記第２半導体領域と接合し、前記第３半導体
領域は、キャリアが流れる経路となり、前記第３半導体
領域は、第２導電型の不純物が高濃度である、縦型半導
体装置である。The present invention is directed to a vertical semiconductor device, comprising a first semiconductor region of a first conductivity type, a second semiconductor region of a first conductivity type, a trench and a third semiconductor region of a second conductivity type. A semiconductor region, a channel is formed in the first semiconductor region, the second semiconductor region has a low concentration of impurities of a first conductivity type, and the third semiconductor region has a trench and the second semiconductor region. A third semiconductor region that is located between the third semiconductor region and the second semiconductor region; and the third semiconductor region is a path through which carriers flow, and the third semiconductor region is a second conductive type. This is a vertical semiconductor device having a high impurity concentration.

【０００８】上記構成の本発明にかかる縦型半導体装置
によれば、ＯＮ抵抗を下げつつ、高耐圧にすることがで
きる。According to the vertical semiconductor device of the present invention having the above structure, it is possible to increase the breakdown voltage while reducing the ON resistance.

【０００９】まず、ＯＮ抵抗を低減できることを説明す
る。本発明において、第３半導体領域はキャリアが流れ
る経路である。第３半導体領域における第２導電型の不
純物は高濃度なので、第３半導体領域の抵抗を小さくす
ることができる。よって、本発明によれば、縦型半導体
装置のＯＮ抵抗を下げることができる。First, the fact that the ON resistance can be reduced will be described. In the present invention, the third semiconductor region is a path through which carriers flow. Since the impurity of the second conductivity type in the third semiconductor region has a high concentration, the resistance of the third semiconductor region can be reduced. Therefore, according to the present invention, the ON resistance of the vertical semiconductor device can be reduced.

【００１０】次に、高耐圧にできることを説明する。第
３半導体領域は、トレンチと第２半導体領域との間に位
置している。また、第３半導体領域は、第２半導体領域
と接合している。このため、縦型半導体装置のＯＦＦ動
作時において、第３半導体領域には、ゲートの作用によ
りトレンチの壁面から延びてくる空乏層および上記接合
から延びてくる空乏層が広がる。よって、第３半導体領
域における第２導電型の不純物は高濃度であるが、第３
半導体領域に空乏層を広げることができる。一方、第２
半導体領域は、第１導電型の不純物が低濃度なので、上
記接合からの空乏層が広がりやすい。Next, the fact that a high breakdown voltage can be achieved will be described. The third semiconductor region is located between the trench and the second semiconductor region. Further, the third semiconductor region is joined to the second semiconductor region. Therefore, during the OFF operation of the vertical semiconductor device, a depletion layer extending from the wall surface of the trench and a depletion layer extending from the junction spread in the third semiconductor region due to the action of the gate. Therefore, the impurity of the second conductivity type in the third semiconductor region has a high concentration,
The depletion layer can be extended in the semiconductor region. On the other hand, the second
Since the semiconductor region has a low concentration of impurities of the first conductivity type, the depletion layer from the junction tends to spread.

【００１１】以上のように、本発明によれば、第２半導
体領域および第３半導体領域に空乏層を広げることがで
きる。As described above, according to the present invention, the depletion layer can be expanded in the second semiconductor region and the third semiconductor region.

【００１２】本発明において、上記各半導体領域の不純
物濃度および寸法を所定の条件にすれば、第２半導体領
域および第３半導体領域の完全空乏化が可能となる。こ
れにより、縦型半導体装置の高耐圧化ができる。In the present invention, when the impurity concentration and the size of each of the semiconductor regions are set to predetermined conditions, the second semiconductor region and the third semiconductor region can be completely depleted. Thereby, the withstand voltage of the vertical semiconductor device can be increased.

【００１３】本発明は、次の構成を加えることもでき
る。すなわち、本発明は、第２導電型の他の半導体領域
を備え、前記他の半導体領域は、前記第２半導体領域と
接合し、前記他の半導体領域は、第２導電型の不純物が
低濃度である、縦型半導体装置である。According to the present invention, the following configuration can be added. That is, the present invention includes another semiconductor region of the second conductivity type, wherein the other semiconductor region is bonded to the second semiconductor region, and the other semiconductor region has a low concentration of impurities of the second conductivity type. Is a vertical semiconductor device.

【００１４】上記構成を加えた本発明によれば、他の半
導体領域と第２半導体領域との接合から形成される空乏
層も、第２半導体領域に広がるので、第２半導体領域に
おける空乏層の広がりをより大きくすることができる。
また、他の半導体領域は第２導電型の不純物が低濃度な
ので、上記接合から形成される空乏層は、他の半導体領
域にも広がる。よって、第２半導体領域、第３半導体領
域および他の半導体領域を全て空乏化することができ、
縦型半導体装置を高耐圧にすることができる。According to the present invention having the above configuration, the depletion layer formed from the junction between the other semiconductor region and the second semiconductor region also extends to the second semiconductor region. Spread can be made larger.
Further, since the other semiconductor region has a low concentration of the second conductivity type impurity, the depletion layer formed from the junction spreads to the other semiconductor region. Therefore, the second semiconductor region, the third semiconductor region, and the other semiconductor regions can all be depleted,
The vertical semiconductor device can have a high breakdown voltage.

【００１５】なお、他の半導体領域は、第３半導体領域
と同じようにキャリアが流れる経路となる。これによれ
ば、縦型半導体装置のＯＮ抵抗をより下げることが可能
となる。The other semiconductor region is a path through which carriers flow as in the third semiconductor region. According to this, it is possible to further reduce the ON resistance of the vertical semiconductor device.

【００１６】本発明は、次の構成を加えることもでき
る。すなわち、本発明は、埋め込み電極および絶縁層を
備え、前記埋め込み電極は、前記トレンチに埋め込まれ
ており、前記絶縁層は、前記埋め込み電極と前記トレン
チの内壁との間に形成され、前記絶縁層の誘電率は、前
記第３半導体領域に蓄積層が形成可能な値である、縦型
半導体装置である。According to the present invention, the following configuration can be added. That is, the present invention includes a buried electrode and an insulating layer, wherein the buried electrode is buried in the trench, the insulating layer is formed between the buried electrode and an inner wall of the trench, and the insulating layer Is a value that allows a storage layer to be formed in the third semiconductor region.

【００１７】上記構成を加えた本発明によれば、第３半
導体領域に蓄積層を形成することが可能となるので、Ｏ
Ｎ抵抗をさらに下げることができる。ＯＮ抵抗を下げる
ことができる説明の前に、まず、蓄積層について説明す
る。According to the present invention having the above structure, the storage layer can be formed in the third semiconductor region.
The N resistance can be further reduced. Before explaining that the ON resistance can be reduced, the accumulation layer will be described first.

【００１８】蓄積層とは、ＭＯＳ構造のゲート作用によ
り、第２導電型の半導体領域の絶縁層近傍に、第２導電
型のキャリアが集まることにより形成された層のことで
ある。例えば、半導体領域がｎ型の場合、蓄積層には、
ｎ型のキャリアが集まっている。また、半導体領域がｐ
型の場合、蓄積層には、ｐ型のキャリアが集まってい
る。The storage layer is a layer formed by collecting the second conductivity type carriers near the insulating layer in the second conductivity type semiconductor region by the gate function of the MOS structure. For example, if the semiconductor region is n-type,
N-type carriers are gathered. The semiconductor region is p
In the case of the p-type, p-type carriers are collected in the accumulation layer.

【００１９】本発明にかかる縦型半導体装置に備えられ
る上記絶縁層の誘電率によれば、第３半導体領域に蓄積
層が形成可能となる。蓄積層は、本来の第３半導体領域
よりも抵抗が小さいので、第３半導体領域に蓄積層を形
成することができれば、ＯＮ抵抗をより下げることがで
きる。According to the dielectric constant of the insulating layer provided in the vertical semiconductor device according to the present invention, a storage layer can be formed in the third semiconductor region. Since the storage layer has lower resistance than the original third semiconductor region, the ON resistance can be further reduced if the storage layer can be formed in the third semiconductor region.

【００２０】上記絶縁層としては、一般にシリコン酸化
層が用いられる。なお、シリコン酸化層よりも誘電率の
高いシリコン窒化層、さらには高誘電率膜であるＳＴＯ
（ＳｒＴｉＯ3）膜やＢＳＴ（ＢａＳｒＴｉＯ3）膜を用
いることにより、より蓄積層のキャリア濃度を増加させ
ることができ、ＯＮ抵抗の低減が図れる。As the insulating layer, a silicon oxide layer is generally used. It should be noted that a silicon nitride layer having a higher dielectric constant than the silicon oxide layer and a high dielectric constant film STO
By using the (SrTiO 3 ) film or the BST (BaSrTiO 3 ) film, the carrier concentration of the storage layer can be further increased, and the ON resistance can be reduced.

【００２１】[0021]

【発明の実施の形態】［第１実施形態］ ｛デバイスの構造｝図１は、本発明の第１実施形態にか
かる縦型ＭＯＳ電界効果トランジスタ１の断面図であ
る。縦型ＭＯＳ電界効果トランジスタ１は、縦型半導体
装置の一例である。縦型ＭＯＳ電界効果トランジスタ１
は、ｎ+型ドレイン領域１５、ｎ+型ソース領域１３ａ、
１３ｂおよび埋め込み電極１１を含む。DESCRIPTION OF THE PREFERRED EMBODIMENTS [First Embodiment] {Structure of Device} FIG. 1 is a sectional view of a vertical MOS field-effect transistor 1 according to a first embodiment of the present invention. The vertical MOS field effect transistor 1 is an example of a vertical semiconductor device. Vertical MOS field effect transistor 1
Are the n + -type drain region 15, the n + -type source region 13a,
13b and the buried electrode 11 are included.

【００２２】ｎ+型ドレイン領域１５は、シリコン基板
に形成されている。ｎ+型ドレイン領域１５上には、所
定の間隔で、ｐ-型シリコン単結晶領域１７が位置して
いる。ｐ-型シリコン単結晶領域１７は、第２半導体領
域の一例である。ｐ-型シリコン単結晶領域１７の幅と
しては、例えば、２〜４μｍである。ｐ-型シリコン単
結晶領域１７のｐ型不純物濃度としては、例えば、１Ｅ
１５〜１Ｅ１６／ｃｍ3である。ｐ-型シリコン単結晶領
域１７の寸法およびｐ型不純物濃度は、ｐ-型シリコン
単結晶領域１７を完全空乏化できる数値が選択される。The n + type drain region 15 is formed on a silicon substrate. On n + type drain region 15, p − type silicon single crystal region 17 is positioned at a predetermined interval. The p − type silicon single crystal region 17 is an example of a second semiconductor region. The width of the p − type silicon single crystal region 17 is, for example, 2 to 4 μm. As the p-type impurity concentration of the p − -type silicon single crystal region 17, for example, 1E
15 to 1E16 / cm 3 . p - dimensions and p-type impurity concentration of -type silicon single crystal region 17, p - numerical value type silicon single crystal region 17 can be completely depleted is selected.

【００２３】ｎ+型ドレイン領域１５上であって、ｐ-型
シリコン単結晶領域１７間には、トレンチ１９が位置し
ている。A trench 19 is located on n + type drain region 15 and between p − type silicon single crystal regions 17.

【００２４】ｎ+型ドレイン領域１５上であって、トレ
ンチ１９とｐ-型シリコン単結晶領域１７との間には、
ｎ+型ドリフト領域２１が位置している。ｎ+型ドリフト
領域２１は、ｐ-型シリコン単結晶領域１７と接合して
いる。この接合を接合部２３とする。また、ｎ+型ドリ
フト領域２１は、トレンチ１９の側面と接触している。On the n + type drain region 15 and between the trench 19 and the p − type silicon single crystal region 17,
An n + type drift region 21 is located. N + type drift region 21 is joined to p − type silicon single crystal region 17. This joint is referred to as a joint 23. Further, n + type drift region 21 is in contact with the side surface of trench 19.

【００２５】ｎ+型ドリフト領域２１は、第３半導体領
域の一例である。ｎ+型ドリフト領域２１の幅として
は、例えば、０．１〜０．５μｍである。ｎ+型ドリフ
ト領域２１のｎ型不純物濃度としては、例えば、１Ｅ１
７〜１Ｅ１８／ｃｍ3である。ｎ+型ドリフト領域２１の
寸法およびｎ型不純物濃度は、ｎ+型ドリフト領域２１
を完全空乏化できる数値が選択される。The n + type drift region 21 is an example of a third semiconductor region. The width of the n + -type drift region 21 is, for example, 0.1 to 0.5 μm. The n-type impurity concentration of the n + -type drift region 21, for example, 1E1
7 to 1E18 / cm 3 . The dimensions and the n-type impurity concentration of the n + -type drift region 21, n + -type drift region 21
Are selected to be completely depleted.

【００２６】トレンチ１９間であって、ｎ+型ドリフト
領域２１およびｐ-型シリコン単結晶領域１７上には、
ｐ型ボディ領域２５が位置している。ｐ型ボディ領域２
５は、第１半導体領域の一例である。ｐ型ボディ領域２
５のうち、トレンチ１９の近傍に位置する部分を領域３
１とする。Between the trenches 19 and on the n + type drift region 21 and the p − type silicon single crystal region 17,
A p-type body region 25 is located. p-type body region 2
5 is an example of a first semiconductor region. p-type body region 2
5 is located in the vicinity of trench 19 in region 3
Let it be 1.

【００２７】ｎ+型ソース領域１３ａ、１３ｂは、トレ
ンチ１９間であって、ｐ型ボディ領域２５上に位置して
いる。ｎ+型ソース領域１３ａ、１３ｂは、互いに間隔
を設けて形成されている。ｎ+型ソース領域１３ａ、１
３ｂは、それぞれ、トレンチ１９と隣接している。The n + type source regions 13a and 13b are located between the trenches 19 and on the p type body region 25. The n + -type source regions 13a and 13b are formed with an interval therebetween. n + type source regions 13a, 1
3b are adjacent to the trench 19, respectively.

【００２８】ｎ+型ソース領域１３ａとｎ+型ソース領域
１３ｂとの間であって、ｐ型ボディ領域２５上には、ｐ
+型ボディコンタクト領域２７が位置している。Between the n + type source region 13a and the n + type source region 13b and on the p type body region 25, p
The + type body contact region 27 is located.

【００２９】埋め込み電極１１は、トレンチ１９に埋め
込まれている。トレンチ１９と埋め込み電極１１との間
には、シリコン酸化層２９が形成されている。埋め込み
電極１１は、埋め込み電極１１ａおよび埋め込み電極１
１ｂを含む。また、シリコン酸化層２９は、シリコン酸
化層２９ａおよびシリコン酸化層２９ｂを含む。The buried electrode 11 is buried in the trench 19. A silicon oxide layer 29 is formed between the trench 19 and the buried electrode 11. The embedded electrode 11 includes an embedded electrode 11 a and an embedded electrode 1.
1b. The silicon oxide layer 29 includes a silicon oxide layer 29a and a silicon oxide layer 29b.

【００３０】埋め込み電極１１ａおよびシリコン酸化層
２９ａは、ｐ-型シリコン単結晶領域１７とｐ型ボディ
領域２５との境界より下に位置している。シリコン酸化
層２９ａの厚みは、ｎ+型ドレイン領域１５と埋め込み
電極１１との電位差に耐えうる値が選択される。例え
ば、２００Ｖ耐圧の場合は、１μｍである。The buried electrode 11 a and the silicon oxide layer 29 a are located below the boundary between the p − type silicon single crystal region 17 and the p type body region 25. The thickness of silicon oxide layer 29a is selected to be a value that can withstand the potential difference between n + -type drain region 15 and embedded electrode 11. For example, in the case of a withstand voltage of 200 V, it is 1 μm.

【００３１】一方、埋め込み電極１１ｂおよびシリコン
酸化層２９ｂは、ｐ-型シリコン単結晶領域１７とｐ型
ボディ領域２５との境界より上に形成されている。シリ
コン酸化層２９ｂはゲート酸化膜として機能する。この
ため、シリコン酸化層２９ｂの厚みは、要求されるしき
い値電圧に応じて選択される。一般的には、０．１〜
０．２μｍ程度である。On the other hand, buried electrode 11b and silicon oxide layer 29b are formed above the boundary between p − type silicon single crystal region 17 and p type body region 25. The silicon oxide layer 29b functions as a gate oxide film. Therefore, the thickness of silicon oxide layer 29b is selected according to the required threshold voltage. Generally, 0.1 to
It is about 0.2 μm.

【００３２】｛デバイスの動作｝次に、縦型ＭＯＳ電界
効果トランジスタ１の動作を説明する。まず、縦型ＭＯ
Ｓ電界効果トランジスタ１のＯＮ動作から説明する。{Operation of Device} Next, the operation of the vertical MOS field effect transistor 1 will be described. First, vertical MO
The description starts with the ON operation of the S field effect transistor 1.

【００３３】ｎ+型ドレイン領域１５には、正電圧が印
加される。ｎ+型ソース領域１３ａ、１３ｂおよびｐ+型
ボディコンタクト領域２７は、接地される。この状態に
おいて、埋め込み電極１１に正電圧を印加すると、ｐ型
ボディ領域２５中の電子が、領域３１に集まり、ｎ型チ
ャネルが形成される。これにより、ｎ+型ソース領域１
３ａ、１３ｂから供給された電子は、ｎ型チャネル、ｎ
+型ドリフト領域２１を流れ、ｎ+型ドレイン領域１５に
到達する。すなわち、縦型ＭＯＳ電界効果トランジスタ
１は、ｎ+型ドレイン領域１５からｎ+型ソース領域１３
ａ、１３ｂへ電流を流す動作をする。A positive voltage is applied to the n + type drain region 15. N + type source regions 13a and 13b and p + type body contact region 27 are grounded. When a positive voltage is applied to the buried electrode 11 in this state, electrons in the p-type body region 25 gather in the region 31 and an n-type channel is formed. Thereby, the n + type source region 1
Electrons supplied from 3a and 13b are n-type channels, n
It flows through the + type drift region 21 and reaches the n + type drain region 15. That is, the vertical MOS field-effect transistor 1, n + -type drain region 15 of n + -type source region 13
a, an operation of flowing a current to 13b.

【００３４】縦型ＭＯＳ電界効果トランジスタ１によれ
ば、ＯＮ動作時の抵抗を下げることができる。すなわ
ち、ｎ型+ドリフト領域２１のｎ型不純物濃度は、高濃
度なので、ｎ+型ドリフト領域２１の抵抗は低くなる。
したがって、その分だけ、縦型ＭＯＳ電界効果トランジ
スタ１のＯＮ動作時の抵抗を下げることができる。この
ように、縦型ＭＯＳ電界効果トランジスタ１によれば、
ＯＮ動作時の抵抗を下げることができるので、縦型ＭＯ
Ｓ電界効果トランジスタ１の消費電力を下げることが可
能となる。この効果は、後で説明する他の実施形態でも
生じる。According to the vertical MOS field effect transistor 1, the resistance during the ON operation can be reduced. That, n-type impurity concentration of the n-type + drift region 21, the high concentration, the resistance of the n + -type drift region 21 becomes lower.
Therefore, the resistance of the vertical MOS field effect transistor 1 during the ON operation can be reduced accordingly. Thus, according to the vertical MOS field effect transistor 1,
Since the resistance during ON operation can be reduced, the vertical MO
The power consumption of the S field effect transistor 1 can be reduced. This effect also occurs in other embodiments described later.

【００３５】次に、縦型ＭＯＳ電界効果トランジスタ１
のＯＦＦ動作を説明する。埋め込み電極１１を正電圧か
ら接地にすると、領域３１のｎ型チャネルはなくなる。
これにより、縦型ＭＯＳ電界効果トランジスタ１は、ｎ
+型ドレイン領域１５からｎ+型ソース領域１３ａ、１３
ｂへ電流を流さない動作をする。Next, the vertical MOS field effect transistor 1
Will be described. When the buried electrode 11 is grounded from a positive voltage, the n-type channel in the region 31 disappears.
Thus, the vertical MOS field effect transistor 1 has n
From the + type drain region 15 to the n + type source regions 13a, 13
The operation is performed such that no current flows to b.

【００３６】パワーＭＯＳ電界効果トランジスタ１がＯ
ＦＦのとき、ドレインに正の電圧が加えられると、その
電圧の増加に伴い空乏層が、ｐ-型シリコン単結晶領域
１７およびｎ+型ドリフト領域２１中に広まっていく。
つまり、ｐ-型シリコン単結晶領域１７中には、接合部
２３から延びてきた空乏層が広がる。ｎ+型ドリフト領
域２１中には、接合部２３から延びてきた空乏層および
ＭＯＳのゲート作用によりトレンチ１９の側面から延び
てきた空乏層が広がる。When the power MOS field effect transistor 1 is O
When a positive voltage is applied to the drain at the time of the FF, the depletion layer spreads in the p − -type silicon single crystal region 17 and the n + -type drift region 21 as the voltage increases.
That is, the depletion layer extending from the junction 23 expands in the p − -type silicon single crystal region 17. In the n + -type drift region 21, a depletion layer extending from the junction 23 and a depletion layer extending from the side surface of the trench 19 due to the gate action of the MOS are spread.

【００３７】縦型ＭＯＳ電界効果トランジスタ１によれ
ば、耐圧は、ｎ+型ドリフト領域２１およびｐ-型シリコ
ン単結晶領域１７を完全空乏化することによって得られ
る。ｎ+型ドリフト領域２１は、接合部２３から延びて
きた空乏層およびトレンチ１９の側面から延びてきた空
乏層が広がる。ｎ+型ドリフト領域２１は、ｎ型不純物
濃度とその幅を適切に設定すれば、完全空乏化すること
ができる。一方、ｐ -型シリコン単結晶領域１７中に
は、接合部２３から延びてきた空乏層が広がる。ｐ-型
シリコン単結晶領域１７中のｐ型不純物濃度は、ｐ-型
シリコン単結晶領域１７を完全空乏化することができる
ように、低い値に設定される。According to the vertical MOS field effect transistor 1,
Then, the withstand voltage is n+Type drift region 21 and p-Type silico
Is obtained by completely depleting the single crystal region 17.
You. n+Mold drift region 21 extends from junction 23
Depletion layer and the sky extending from the side of the trench 19
The poor layer spreads. n+Type drift region 21 is an n-type impurity
Complete depletion with proper setting of concentration and width
Can be. On the other hand, p -Type silicon single crystal region 17
The depletion layer extending from the junction 23 expands. p-Type
The p-type impurity concentration in the silicon single crystal region 17 is p-Type
The silicon single crystal region 17 can be completely depleted
So that it is set to a low value.

【００３８】このように、縦型ＭＯＳ電界効果トランジ
スタ１によれば、ｎ+型ドリフト領域２１およびｐ-型シ
リコン単結晶領域１７を完全空乏化することによって、
耐圧を高くすることができる。この効果は、後で説明す
る他の実施形態でも生じる。As described above, according to the vertical MOS field effect transistor 1, by completely depleting the n + -type drift region 21 and the p -- type silicon single crystal region 17,
The withstand voltage can be increased. This effect also occurs in other embodiments described later.

【００３９】｛デバイスの製造方法｝次に、縦型ＭＯＳ
電界効果トランジスタ１の製造工程を説明する。図３、
図４および図５は、これを説明するための工程図であ
る。{Device Manufacturing Method} Next, a vertical MOS
The manufacturing process of the field effect transistor 1 will be described. FIG.
FIGS. 4 and 5 are process diagrams for explaining this.

【００４０】図３（Ａ）に示すように、ｎ+型ドレイン
領域１５を含むシリコン基板を準備する。ドレイン領域
１５上に例えば、エピタキシャル成長により、厚さ１０
〜１５μｍのｐ-型シリコン単結晶領域１７を形成す
る。As shown in FIG. 3A, a silicon substrate including an n + type drain region 15 is prepared. On the drain region 15, for example, a thickness of 10
-Type silicon single crystal region 17 - p of 15 m.

【００４１】次に、公知の方法を用いてｐ型ボディ領域
２５を形成する。さらに、ｐ-型シリコン単結晶領域１
７とｐ型ボディ領域２５を選択的にエッチングし、所定
の間隔でトレンチ１９を形成する。トレンチ１９はｎ+
型ドレイン領域１５に到達している。Next, a p-type body region 25 is formed by using a known method. Further, the p - type silicon single crystal region 1
7 and the p-type body region 25 are selectively etched to form trenches 19 at predetermined intervals. Trench 19 is n +
Has reached the mold drain region 15.

【００４２】図３（Ｂ）に示すように、トレンチ１９に
薄い酸化膜３３を形成し、その後、リン酸ガラス（ＰＳ
Ｇ：Ｐｈｏｓｐｈｏｓｉｌｉｃａｔｅ ｇｌａｓｓ）膜
３５をＣＶＤ法によりトレンチ１９に埋め込む。As shown in FIG. 3B, a thin oxide film 33 is formed in the trench 19, and thereafter, a phosphate glass (PS) is formed.
G: Phosphosilicate glass film 35 is buried in the trench 19 by the CVD method.

【００４３】図３（Ｃ）に示すように、その後、アニー
ル処理を行い、ｐ-型シリコン単結晶領域１７のうち、
トレンチ１９近傍にｎ+型ドリフト領域２１を形成す
る。ｎ+型ドリフト領域２１の寸法およびｎ型不純物濃
度は、埋め込むＰＳＧ膜３５のリン濃度、トレンチ１９
側壁の酸化膜３３の厚み、アニール温度によって制御す
ることができる。Then, as shown in FIG. 3C, an annealing process is performed, and the p - type silicon single crystal region 17 is
An n + -type drift region 21 is formed near the trench 19. The dimensions of the n + type drift region 21 and the n type impurity concentration are determined by the phosphorus concentration of the PSG film 35 to be embedded and the trench 19.
It can be controlled by the thickness of the oxide film 33 on the side wall and the annealing temperature.

【００４４】図４（Ａ）に示すように、公知の方法を用
いて、埋め込んだＰＳＧ膜３５と酸化膜３３とを取り除
く。As shown in FIG. 4A, the buried PSG film 35 and oxide film 33 are removed by a known method.

【００４５】図４（Ｂ）に示すように、例えば、熱酸化
により、トレンチ１９の内壁に、厚さ約１μｍのシリコ
ン酸化層２９ａを形成する。次に、例えば、ＣＶＤ法に
より、トレンチ１９が埋まるように、厚さ０．５〜１．
５μｍのｎ+型ポリシリコン層３７を形成する。As shown in FIG. 4B, a silicon oxide layer 29a having a thickness of about 1 μm is formed on the inner wall of the trench 19 by, for example, thermal oxidation. Next, for example, the thickness is set to 0.5 to 1.
An n + -type polysilicon layer 37 of 5 μm is formed.

【００４６】図４（Ｃ）に示すように、公知の方法を用
いて、ポリシリコン層３７およびシリコン酸化層２９ａ
をエッチバックすることにより、ｐ型ボディ領域２５と
ｐ-型シリコン単結晶領域１７との境界より下にのみ、
ポリシリコン層３７およびシリコン酸化層２９ａが残る
ようにする。As shown in FIG. 4C, the polysilicon layer 37 and the silicon oxide layer 29a are formed by a known method.
Is etched back only below the boundary between p-type body region 25 and p − -type silicon single crystal region 17.
The polysilicon layer 37 and the silicon oxide layer 29a are left.

【００４７】図５（Ａ）に示すように、例えば、熱酸化
により、トレンチ１９のうち露出している内壁に、厚さ
０．１μｍ程度のシリコン酸化層２９ｂを形成する。As shown in FIG. 5A, a silicon oxide layer 29b having a thickness of about 0.1 μm is formed on the exposed inner wall of the trench 19 by, for example, thermal oxidation.

【００４８】図５（Ｂ）に示すように、例えば、フォト
リソグラフィとエッチングにより、埋め込み電極１１ａ
上のシリコン酸化層２９ｂを除去する。As shown in FIG. 5B, the buried electrode 11a is formed by photolithography and etching, for example.
The upper silicon oxide layer 29b is removed.

【００４９】次に、例えば、ＣＶＤ法により、トレンチ
１９が埋まるように、ポリシリコン層を形成し、その
後、このポリシリコン層を、エッチバックすることによ
り、図５（Ｃ）に示すように、トレンチ１９内のみにポ
リシリコン層が残るようにする。このポリシリコン層が
埋め込み電極１１ｂとなる。Next, a polysilicon layer is formed by, for example, a CVD method so as to fill the trench 19, and then this polysilicon layer is etched back, as shown in FIG. The polysilicon layer is left only in the trench 19. This polysilicon layer becomes the buried electrode 11b.

【００５０】図１に示すように、公知の方法を用いてｐ
型ボディ領域２５中に、ｎ+型ソース領域１３ａ、１３
ｂおよびｐ+型ボディコンタクト領域２７を形成する。
以上の工程により、縦型ＭＯＳ電界効果トランジスタ１
が完成する。As shown in FIG. 1, p is determined using a known method.
N + type source regions 13a and 13
The b and p + type body contact regions 27 are formed.
Through the above steps, the vertical MOS field effect transistor 1
Is completed.

【００５１】後の実施形態にかかる縦型ＭＯＳ電界効果
トランジスタも、縦型ＭＯＳ電界効果トランジスタ１の
製造方法と同様の方法を用いて作製することができる。The vertical MOS field-effect transistor according to the later embodiment can also be manufactured by using the same method as the manufacturing method of the vertical MOS field-effect transistor 1.

【００５２】なお、第１実施形態にかかる縦型ＭＯＳ電
界効果トランジスタ１における各領域の導電型は、逆の
導電型でもよい。これは、後で説明する他の実施形態で
も言えることである。The conductivity type of each region in the vertical MOS field effect transistor 1 according to the first embodiment may be the opposite conductivity type. This can be applied to other embodiments described later.

【００５３】また、第１実施形態は、縦型ＭＯＳ電界効
果トランジスタである。本発明はこれに限定されず、他
の縦型半導体装置にも適用することができる。これは、
後で説明する他の実施形態でも言えることである。The first embodiment is a vertical MOS field effect transistor. The present invention is not limited to this, and can be applied to other vertical semiconductor devices. this is,
The same can be said for other embodiments described later.

【００５４】［第２実施形態］ ｛デバイスの構造｝図２は、本発明の第２実施形態にか
かる縦型ＭＯＳ電界効果トランジスタ３の断面図であ
る。図１に示す第１実施形態にかかる縦型ＭＯＳ電界効
果トランジスタ１と同等の機能を有する部分には、同一
符号を付してある。縦型ＭＯＳ電界効果トランジスタ３
が縦型ＭＯＳ電界効果トランジスタ１と相違する部分を
説明し、同じ部分については説明を省略する。[Second Embodiment] {Structure of Device} FIG. 2 is a sectional view of a vertical MOS field-effect transistor 3 according to a second embodiment of the present invention. Portions having functions equivalent to those of the vertical MOS field effect transistor 1 according to the first embodiment shown in FIG. 1 are denoted by the same reference numerals. Vertical MOS field effect transistor 3
Will be described for portions different from the vertical MOS field effect transistor 1, and description of the same portions will be omitted.

【００５５】縦型ＭＯＳ電界効果トランジスタ３は、ｎ
-型シリコン単結晶領域３９を備えている。ｎ-型シリコ
ン単結晶領域３９は、ｐ-型シリコン単結晶領域１７と
ｎ+型ドレイン領域１５との間に位置している。ｎ-型シ
リコン単結晶領域３９は、ｐ-型シリコン単結晶領域１
７と接合している。この接合を接合部４１とする。The vertical MOS field effect transistor 3 has n
- and a -type silicon single crystal region 39. N − type silicon single crystal region 39 is located between p − type silicon single crystal region 17 and n + type drain region 15. The n − type silicon single crystal region 39 is a p − type silicon single crystal region 1
7. This joint is referred to as a joint 41.

【００５６】ｎ-型シリコン単結晶領域３９の幅として
は、例えば、２〜４μｍである。ｎ-型シリコン単結晶
領域３９のｎ型不純物濃度としては、例えば、１Ｅ１５
〜１Ｅ１６／ｃｍ3である。ｎ-型シリコン単結晶領域３
９の寸法およびｎ型不純物濃度は、ｎ-型シリコン単結
晶領域３９を完全空乏化できる数値が選択される。The width of n − type silicon single crystal region 39 is, for example, 2 to 4 μm. The n − -type silicon single crystal region 39 has an n-type impurity concentration of, for example, 1E15
１1E16 / cm 3 . n - type silicon single crystal region 3
As the size of 9 and the n-type impurity concentration, a numerical value capable of completely depleting the n − -type silicon single crystal region 39 is selected.

【００５７】縦型ＭＯＳ電界効果トランジスタ１によれ
ば、次の二つの効果が生じる。一つ目から説明する。先
程説明したように、耐圧向上のためには完全空乏化が望
ましい。縦型ＭＯＳ電界効果トランジスタ３は、接合部
４１を備えている。接合部４１からも空乏層が広がるの
で、ｐ-型シリコン単結晶領域１７の完全空乏化が容易
となる。また、ｎ-型シリコン単結晶領域３９中のｎ型
不純物濃度は低いので、ｎ-型シリコン単結晶領域３９
自体にも、空乏層が広まりやすい。よって、ｎ-型シリ
コン単結晶領域３９の完全空乏化も容易となる。According to the vertical MOS field effect transistor 1, the following two effects occur. It will be explained from the first. As described above, complete depletion is desirable for improving the breakdown voltage. The vertical MOS field-effect transistor 3 has a junction 41. Since the depletion layer extends from the junction 41, it is easy to completely deplete the p − -type silicon single crystal region 17. Further, n - since -type silicon n-type impurity concentration in the single crystal region 39 is low, n - -type silicon single crystal region 39
In itself, the depletion layer tends to spread. Therefore, complete depletion of n − -type silicon single crystal region 39 is also facilitated.

【００５８】次に、二つ目を説明する。ｎ-型シリコン
単結晶領域３９はドリフト領域として機能する。その分
だけ、ドリフト領域の面積が広がる。よって、ＯＮ抵抗
を下げることが可能となる。Next, the second will be described. N − type silicon single crystal region 39 functions as a drift region. The area of the drift region is increased accordingly. Therefore, the ON resistance can be reduced.

【００５９】｛デバイス性能のシミュレーション｝縦型
ＭＯＳ電界効果トランジスタ３は、高耐圧でありなが
ら、ＯＮ動作時の抵抗が小さいことを、シミュレーショ
ンにより確認した。まず、シミュレーションの対象とな
る縦型ＭＯＳ電界効果トランジスタ３の条件を、図６を
用いながら説明する。図６は、縦型ＭＯＳ電界効果トラ
ンジスタ３の断面の一部である。{Simulation of Device Performance} It has been confirmed by simulation that the vertical MOS field effect transistor 3 has a high withstand voltage and a small resistance during the ON operation. First, the conditions of the vertical MOS field effect transistor 3 to be simulated will be described with reference to FIG. FIG. 6 is a part of a cross section of the vertical MOS field effect transistor 3.

【００６０】 ｎ+型ドリフト領域２１のｎ型不純物濃度：１×１０17
／ｃｍ3 ｎ+型ドリフト領域２１の幅：０．３μｍ ｎ+型ドリフト領域２１の深さ：１６．５μｍ ｐ-型シリコン単結晶領域１７のｐ型不純物濃度：１×
１０16／ｃｍ3 ｐ-型シリコン単結晶領域１７の幅：１．２μｍ ｐ-型シリコン単結晶領域１７の深さ：１２．５μｍ ｎ-型シリコン単結晶領域３９のｎ型不純物濃度：１×
１０15／ｃｍ3 ｎ-型シリコン単結晶領域３９の幅：１．２μｍ ｎ-型シリコン単結晶領域３９の深さ：４μｍ シリコン酸化層２９ａの厚み：１μｍ シリコン酸化層２９ｂの厚み：０．１μｍ 上記条件は、縦型ＭＯＳ電界効果トランジスタ３の耐圧
が２００Ｖ程度となり、かつｎ+型ドリフト領域２１、
ｎ-型シリコン単結晶領域３９およびｐ-型シリコン単結
晶領域１７が完全空乏化（つまり、Ｒeduced Ｓurface
Ｆield分布）できる条件である。The n-type impurity concentration of the n + -type drift region 21 is 1 × 10 17
/ Cm 3 n + -type drift region 21 width: 0.3 μm n + -type drift region 21 depth: 16.5 μm p - type silicon single crystal region 17 p-type impurity concentration: 1 ×
The width of the 10 16 / cm 3 p − -type silicon single crystal region 17: 1.2 μm The depth of the p − -type silicon single crystal region 17: 12.5 μm The n-type impurity concentration of the n − -type silicon single crystal region 39: 1 ×
10 15 / cm 3 Width of n - type silicon single crystal region 39: 1.2 μm Depth of n - type silicon single crystal region 39: 4 μm Thickness of silicon oxide layer 29a: 1 μm Thickness of silicon oxide layer 29b: 0.1 μm The above condition is that the withstand voltage of the vertical MOS field-effect transistor 3 is about 200 V, and the n + -type drift region 21,
The n − -type silicon single crystal region 39 and the p − -type silicon single crystal region 17 are completely depleted (that is, reduced surface).
Field distribution).

【００６１】なお、シリコン酸化層２９ａの厚みは、ド
レイン電圧が２００Ｖでもシリコン酸化層２９ａが絶縁
破壊しない値を選んだ。また、シリコン酸化層２９ｂの
厚みは、縦型ＭＯＳ電界効果トランジスタ３が所望の立
ち上がり電圧（約１Ｖ）を得られるような値を選んだ。The thickness of the silicon oxide layer 29a was selected so that the silicon oxide layer 29a did not break down even when the drain voltage was 200V. The thickness of the silicon oxide layer 29b is selected so that the vertical MOS field-effect transistor 3 can obtain a desired rising voltage (about 1 V).

【００６２】上記条件の下で、縦型ＭＯＳ電界効果トラ
ンジスタ３の耐圧特性（ドレイン電圧ＶDとドレイン電
流ＩDとの関係）のシミュレーションをした。その結果
を図７のグラフに示す。なお、ゲート電圧などの条件は
次のとおりである。Under the above conditions, a simulation of the breakdown voltage characteristics (the relationship between the drain voltage V D and the drain current I D ) of the vertical MOS field effect transistor 3 was performed. The results are shown in the graph of FIG. The conditions such as the gate voltage are as follows.

【００６３】 ゲート電圧：０Ｖ ドレイン電圧：０〜２５０Ｖの範囲において、０．２Ｖ
づつ電圧を上昇 ソース電圧：０Ｖ ボディ電圧：０Ｖ 図７のグラフから分かるように、ドレイン電圧ＶDが２
１５Ｖで、縦型ＭＯＳ電界効果トランジスタ３はブレー
クダウンしている。よって、上記縦型ＭＯＳ電界効果ト
ランジスタ３の条件によれば、耐圧が２１５Ｖであるこ
とが分かる。Gate voltage: 0 V Drain voltage: 0.2 V in the range of 0 to 250 V
Increments voltage increase source voltage: 0V body voltage: As can be seen from the graph of 0V Figure 7, the drain voltage V D is 2
At 15 V, the vertical MOS field-effect transistor 3 has broken down. Therefore, it is understood that the breakdown voltage is 215 V according to the conditions of the vertical MOS field-effect transistor 3.

【００６４】次に、縦型ＭＯＳ電界効果トランジスタ３
のゲート電圧ＶGとドレイン電流ＩDとの関係のシミュレ
ーションをした。その結果を図８のグラフに示す。な
お、ゲート電圧などの条件は次のとおりである。Next, the vertical MOS field effect transistor 3
Simulation of the relationship between the gate voltage V G and the drain current I D of the. The results are shown in the graph of FIG. The conditions such as the gate voltage are as follows.

【００６５】 ゲート電圧：０〜２０Ｖの範囲において、０．０５Ｖづ
つ電圧を上昇 ドレイン電圧： ０．１Ｖ ソース電圧：０Ｖ ボディ電圧：０Ｖ 図８に示すグラフから、ＶG＝１０Ｖのもとにおける縦
型ＭＯＳ電界効果トランジスタ３のＯＮ抵抗（ＲON）を
計算すると、０．１７８Ω・ｍｍ2となる。計算式は、
次のとおりである。Gate voltage: Increased by 0.05 V in the range of 0 to 20 V Drain voltage: 0.1 V Source voltage: 0 V Body voltage: 0 V From the graph shown in FIG. 8, the vertical direction under V G = 10 V When the ON resistance (R ON ) of the type MOS field effect transistor 3 is calculated, it is 0.178 Ω · mm 2 . The calculation formula is
It is as follows.

【００６６】ＲON＝（ＶD／ＩD）×セルサイズ ここで、 ＶD：０．１Ｖ ＩD：ＶG＝１０Ｖの時の値 セルサイズ：図６では３μｍ 次に、この結果とシリコンリミットとの関係を説明す
る。図９は、シリコンリミットを示すグラフである。横
軸は、ブレークダウン電圧ＶBである。縦軸は、ＯＮ動
作時の抵抗ＲONである。シリコンリミットとは、「ＰＯ
ＷＥＲ ＭＯＳＦＥＴＳ Ｔｈｅｏｒｙ ａｎｄ Ａｐ
ｐｌｉｃａｔｉｏｎｓ」（発行Ｊｏｈｎ Ｗｉｌｅｙ＆
Ｓｏｎｓ社、著者Ｄ．Ａ．Ｇｒａｎｔ）で記述されてい
るように、耐圧によって一義的に決まるＯＮ抵抗の最小
値である。図９から分かるように、ブレークダウン電圧
の上昇に伴い、ＯＮ抵抗は上昇する。[0066] Here R ON = (V D / I D) × cell size, V D: 0.1V I D: the value cell size when V G = 10V: FIG 6 3 [mu] m Then, the result and silicon The relationship with the limit will be described. FIG. 9 is a graph showing the silicon limit. The horizontal axis is the breakdown voltage V B. The vertical axis is the resistance R ON during the ON operation. What is Silicon Limit?
WER MOSFETS Theory and Ap
applications (issued by John Wiley &
Sons, author D.S. A. As described in (Grant), this is the minimum value of the ON resistance uniquely determined by the breakdown voltage. As can be seen from FIG. 9, the ON resistance increases as the breakdown voltage increases.

【００６７】図９のグラフ中の点Ａは、上記実験例結果
を示している。シリコンリミットでは、ブレークダウン
電圧が２１５Ｖのとき、ＯＮ抵抗は、約０．４Ω・ｍｍ
2となる。これに対して、縦型ＭＯＳ電界効果トランジ
スタ３によれば、ブレークダウン電圧が２１５Ｖのと
き、ＯＮ抵抗は、０．１７８Ω・ｍｍ2となる。つま
り、１／２以下となっている。したがって、縦型ＭＯＳ
電界効果トランジスタ３は、高耐圧でありながら、ＯＮ
抵抗は小さいことが分かる。The point A in the graph of FIG. 9 shows the result of the above experimental example. In the silicon limit, when the breakdown voltage is 215 V, the ON resistance is about 0.4 Ω · mm
It becomes 2 . On the other hand, according to the vertical MOS field effect transistor 3, when the breakdown voltage is 215 V, the ON resistance is 0.178 Ω · mm 2 . That is, it is 1/2 or less. Therefore, vertical MOS
The field effect transistor 3 is turned on while having a high withstand voltage.
It can be seen that the resistance is small.

【００６８】このように、縦型ＭＯＳ電界効果トランジ
スタ３によれば、シリコンリミットを越えた性能が得ら
れる。As described above, according to the vertical MOS field effect transistor 3, a performance exceeding the silicon limit can be obtained.

【００６９】次に、縦型ＭＯＳ電界効果トランジスタ３
の電位分布をシミュレーションした。図１０は、ＯＦＦ
動作時において、ドレイン電圧が２００Ｖにおける縦型
ＭＯＳ電界効果トランジスタ３の電位分布を示す図であ
る。Next, the vertical MOS field effect transistor 3
Was simulated. FIG. 10 is OFF
FIG. 7 is a diagram showing a potential distribution of the vertical MOS field-effect transistor 3 when the drain voltage is 200 V during operation.

【００７０】図１０に示すよう空乏層エッジが形成され
ていることから、ｐ-型シリコン単結晶領域１７、ｎ+型
ドリフト領域２１およびｎ-型シリコン単結晶領域３９
の領域が完全空乏化していることが分かる。また、等電
位線がほぼ均一の間隔で分布していることが分かる。Since a depletion layer edge is formed as shown in FIG. 10, p − type silicon single crystal region 17, n + type drift region 21 and n − type silicon single crystal region 39
It can be seen that the region is completely depleted. In addition, it can be seen that equipotential lines are distributed at substantially uniform intervals.

【００７１】［その他］第１および第２実施形態にかか
る縦型ＭＯＳ電界効果トランジスタ１、３では、シリコ
ン酸化層２９ａを用いている。シリコン酸化層２９ａの
かわりに高誘電体絶縁層を用いることにより、ＯＮ抵抗
のさらなる低減が図れる。高誘電体絶縁層としては、例
えば、シリコン窒化層、ＳＴＯ（ＳrＴiＯ3）層、ＢＳ
Ｔ（ＢaＳrＴiＯ3）層がある。ＳＴＯ層やＢＳＴ層のよ
うに、誘電率が高い物質を用いた場合、図１および図２
に示すｎ+型ドリフト領域２１に、よりキャリア濃度の
高い蓄積層が形成可能となる。これにより、ＯＮ抵抗を
さらに低下させることができる。[Others] In the vertical MOS field effect transistors 1 and 3 according to the first and second embodiments, a silicon oxide layer 29a is used. By using a high dielectric insulating layer instead of the silicon oxide layer 29a, the ON resistance can be further reduced. As the high dielectric insulating layer, for example, a silicon nitride layer, an STO (SrTiO 3 ) layer, a BS
There is a T (BaSrTiO 3 ) layer. When a substance having a high dielectric constant such as an STO layer or a BST layer is used, FIGS.
It is possible to form an accumulation layer having a higher carrier concentration in the n + -type drift region 21 shown in FIG. Thereby, the ON resistance can be further reduced.

【００７２】これを具体的に説明する。ＳＴＯ層やＢＳ
Ｔ層で実現可能な比誘電率として、１００を設定し、他
の条件は変えずに、シミュレーションからＯＮ抵抗（Ｒ
ON）を求めると、０．１１３Ω・ｍｍ2となった。これ
からも分かるように、高誘電体絶縁層を用いることによ
り、ＯＮ抵抗がさらに低下する。This will be specifically described. STO layer and BS
The relative dielectric constant achievable in the T layer is set to 100, and the other conditions are not changed, and the ON resistance (R
ON ) was 0.113 Ω · mm 2 . As can be seen from the above, the use of the high dielectric insulating layer further reduces the ON resistance.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の第１実施形態にかかる縦型ＭＯＳ電界
効果トランジスタ１の断面図である。FIG. 1 is a cross-sectional view of a vertical MOS field-effect transistor 1 according to a first embodiment of the present invention.

【図２】本発明の第２実施形態にかかる縦型ＭＯＳ電界
効果トランジスタ３の断面図である。FIG. 2 is a sectional view of a vertical MOS field-effect transistor 3 according to a second embodiment of the present invention.

【図３】本発明の第１実施形態にかかる縦型ＭＯＳ電界
効果トランジスタ１の製造工程を説明するための工程図
である。FIG. 3 is a process diagram for explaining a manufacturing process of the vertical MOS field-effect transistor 1 according to the first embodiment of the present invention.

【図４】本発明の第１実施形態にかかる縦型ＭＯＳ電界
効果トランジスタ１の製造工程を説明するための工程図
である。FIG. 4 is a process diagram for explaining a manufacturing process of the vertical MOS field-effect transistor 1 according to the first embodiment of the present invention.

【図５】本発明の第１実施形態にかかる縦型ＭＯＳ電界
効果トランジスタ１の製造工程を説明するための工程図
である。FIG. 5 is a process diagram for explaining a manufacturing process of the vertical MOS field-effect transistor 1 according to the first embodiment of the present invention.

【図６】本発明の第２実施形態にかかる縦型ＭＯＳ電界
効果トランジスタ３の部分断面図である。FIG. 6 is a partial sectional view of a vertical MOS field-effect transistor 3 according to a second embodiment of the present invention.

【図７】本発明の第２実施形態にかかる縦型ＭＯＳ電界
効果トランジスタ３のドレイン電圧とドレイン電流との
関係をシミュレーションし、その結果を表したグラフで
ある。FIG. 7 is a graph showing a result of simulating a relationship between a drain voltage and a drain current of a vertical MOS field-effect transistor 3 according to a second embodiment of the present invention.

【図８】本発明の第２実施形態にかかる縦型ＭＯＳ電界
効果トランジスタ３のゲート電圧とドレイン電流との関
係をシミュレーションし、その結果を表したグラフであ
る。FIG. 8 is a graph showing a simulation result of a relationship between a gate voltage and a drain current of a vertical MOS field-effect transistor 3 according to a second embodiment of the present invention.

【図９】シリコンリミットを示すグラフである。FIG. 9 is a graph showing a silicon limit.

【図１０】本発明の第２実施形態にかかる縦型ＭＯＳ電
界効果トランジスタ３の電位分布のシミュレーションを
示す図である。FIG. 10 is a diagram showing a simulation of a potential distribution of a vertical MOS field-effect transistor 3 according to a second embodiment of the present invention.

【符号の説明】 １、３ 縦型ＭＯＳ電界効果トランジスタ １１、１１ａ、１１ｂ 埋め込み電極 １３ａ、１３ｂ ｎ+型ソース領域 １５ ｎ+型ドレイン領域 １７ ｐ―型シリコン単結晶領域 １９ トレンチ ２１ ｎ+型ドリフト領域 ２３ 接合部 ２５ ｐ型ボディ領域 ２７ ｐ+型ボディコンタクト領域 ２９、２９ａ、２９ｂ シリコン酸化層 ３１ 領域 ３３ シリコン酸化層 ３５ ｎ+型ポリシリコン層 ３７ ポリシリコン層 ３９ ｎ―型シリコン単結晶領域 ４１ 接合部 ４３ 等電位線[Description of Signs] 1, 3 Vertical MOS field effect transistor 11, 11a, 11b Buried electrode 13a, 13b n + source region 15 n + drain region 17 p- silicon single crystal region 19 trench 21 n + drift Region 23 junction 25 p-type body region 27 p + -type body contact region 29, 29a, 29b silicon oxide layer 31 region 33 silicon oxide layer 35 n + -type polysilicon layer 37 polysilicon layer 39 n-type silicon single crystal region 41 Junction 43 equipotential line

Claims (3)

【特許請求の範囲】[Claims] 【請求項１】 縦型半導体装置であって、 第１導電型の第１半導体領域、トレンチ、第１導電型の
第２半導体領域および第２導電型の第３半導体領域を備
え、 前記第１半導体領域には、チャネルが形成され、 前記第２半導体領域は、第１導電型の不純物が低濃度で
あり、 前記第３半導体領域は、前記トレンチと前記第２半導体
領域との間に位置し、 前記第３半導体領域は、前記第２半導体領域と接合し、 前記第３半導体領域は、キャリアが流れる経路となり、 前記第３半導体領域は、第２導電型の不純物が高濃度で
ある、縦型半導体装置。1. A vertical semiconductor device, comprising: a first semiconductor region of a first conductivity type; a trench; a second semiconductor region of a first conductivity type; and a third semiconductor region of a second conductivity type. A channel is formed in the semiconductor region, the second semiconductor region has a low concentration of impurities of a first conductivity type, and the third semiconductor region is located between the trench and the second semiconductor region. The third semiconductor region is bonded to the second semiconductor region, the third semiconductor region serves as a path through which carriers flow, and the third semiconductor region has a high impurity concentration of a second conductivity type. Type semiconductor device. 【請求項２】 請求項１において、 第２導電型の他の半導体領域を備え、 前記他の半導体領域は、前記第２半導体領域と接合し、 前記他の半導体領域は、第２導電型の不純物が低濃度で
ある、縦型半導体装置。2. The semiconductor device according to claim 1, further comprising another semiconductor region of a second conductivity type, wherein the other semiconductor region is joined to the second semiconductor region, and the other semiconductor region is of a second conductivity type. A vertical semiconductor device having a low impurity concentration. 【請求項３】 請求項１または２において、 埋め込み電極および絶縁層を備え、 前記埋め込み電極は、前記トレンチに埋め込まれてお
り、 前記絶縁層は、前記埋め込み電極と前記トレンチの内壁
との間に形成され、 前記絶縁層の誘電率は、前記第３半導体領域に蓄積層が
形成可能な値である、縦型半導体装置。3. The device according to claim 1, further comprising a buried electrode and an insulating layer, wherein the buried electrode is buried in the trench, and the insulating layer is provided between the buried electrode and an inner wall of the trench. The vertical semiconductor device is formed, wherein the dielectric constant of the insulating layer is a value at which a storage layer can be formed in the third semiconductor region.
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