JP2001111050A - Vertical semiconductor device - Google Patents
Vertical semiconductor deviceInfo
- Publication number
- JP2001111050A JP2001111050A JP29076599A JP29076599A JP2001111050A JP 2001111050 A JP2001111050 A JP 2001111050A JP 29076599 A JP29076599 A JP 29076599A JP 29076599 A JP29076599 A JP 29076599A JP 2001111050 A JP2001111050 A JP 2001111050A
- Authority
- JP
- Japan
- Prior art keywords
- type
- region
- semiconductor region
- effect transistor
- mos field
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 92
- 239000012535 impurity Substances 0.000 claims abstract description 28
- 238000003860 storage Methods 0.000 claims description 8
- 239000000969 carrier Substances 0.000 claims description 7
- 230000005669 field effect Effects 0.000 abstract description 65
- 229910052710 silicon Inorganic materials 0.000 abstract description 57
- 239000010703 silicon Substances 0.000 abstract description 57
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 56
- 239000013078 crystal Substances 0.000 description 49
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 25
- 229910052814 silicon oxide Inorganic materials 0.000 description 25
- 230000015556 catabolic process Effects 0.000 description 15
- 210000000746 body region Anatomy 0.000 description 12
- 238000000034 method Methods 0.000 description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 9
- 229920005591 polysilicon Polymers 0.000 description 9
- 238000010586 diagram Methods 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 6
- 238000004088 simulation Methods 0.000 description 6
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 3
- 108090000699 N-Type Calcium Channels Proteins 0.000 description 3
- 238000009825 accumulation Methods 0.000 description 3
- 230000000779 depleting effect Effects 0.000 description 3
- 238000009826 distribution Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000005360 phosphosilicate glass Substances 0.000 description 3
- 229910015801 BaSrTiO Inorganic materials 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 229910002367 SrTiO Inorganic materials 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 239000005365 phosphate glass Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 108091006146 Channels Proteins 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
- H01L29/0878—Impurity concentration or distribution
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Composite Materials (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、例えば、パワーエ
レクトロニクスに用いることができる縦型半導体装置に
関する。The present invention relates to a vertical semiconductor device that can be used, for example, in power electronics.
【0002】[0002]
【背景技術および発明が解決しようとする課題】縦型M
OS(Metal Oxide Semiconductor)電界効果トランジ
スタは、例えば、家庭用電気機器や自動車のモータの電
力変換や電力制御に使われる半導体素子の一種である。
縦型MOS電界効果トランジスタは、電力用に使用され
るので、高耐圧である必要がある。また、縦型MOS電
界効果トランジスタの低消費電力化のためには、縦型M
OS電界効果トランジスタのON動作時の抵抗を下げる
必要がある。このように、縦型MOS電界効果トランジ
スタの特性としては、高耐圧で、かつON抵抗が低い、
ことが求められる。2. Description of the Related Art Vertical M
An OS (Metal Oxide Semiconductor) field-effect transistor is a type of semiconductor element used for power conversion and power control of, for example, home electric appliances and motors of automobiles.
Since the vertical MOS field effect transistor is used for electric power, it needs to have a high breakdown voltage. In order to reduce the power consumption of the vertical MOS field effect transistor, the vertical M
It is necessary to reduce the resistance of the OS field-effect transistor during the ON operation. As described above, the characteristics of the vertical MOS field-effect transistor include a high withstand voltage and a low ON resistance.
Is required.
【0003】ところで、縦型MOS電界効果トランジス
タにおいて、ドリフト領域に形成された空乏層により、
その絶縁破壊を防いでいる。縦型MOS電界効果トラン
ジスタを高耐圧にするには、空乏層の延びを大きくする
必要がある。このためには、ドリフト領域の不純物濃度
を低くしなければならない。In a vertical MOS field effect transistor, a depletion layer formed in a drift region causes
The dielectric breakdown is prevented. In order to increase the breakdown voltage of the vertical MOS field effect transistor, it is necessary to increase the extension of the depletion layer. For this purpose, the impurity concentration in the drift region must be reduced.
【0004】しかし、ドリフト領域の不純物濃度を低く
すると、ドリフト領域の抵抗が上昇し、それにより、縦
型MOS電界効果トランジスタのON抵抗が上昇する。However, when the impurity concentration of the drift region is reduced, the resistance of the drift region increases, and as a result, the ON resistance of the vertical MOS field effect transistor increases.
【0005】このように、縦型MOS電界効果トランジ
スタにおいては、高耐圧にするとON抵抗が上昇し、O
N抵抗を下げようとすると耐圧が低下するという、耐圧
とON抵抗との間にはトレードオフの関係がある。As described above, in a vertical MOS field-effect transistor, when the breakdown voltage is increased, the ON resistance increases, and
There is a trade-off relationship between the withstand voltage and the ON resistance in that the withstand voltage decreases when the N resistance is reduced.
【0006】本発明の目的は、ON抵抗を下げつつ、高
耐圧にすることができる縦型半導体装置を提供すること
である。An object of the present invention is to provide a vertical semiconductor device capable of achieving a high withstand voltage while reducing the ON resistance.
【0007】[0007]
【課題を解決するための手段】本発明は、縦型半導体装
置であって、第1導電型の第1半導体領域、第1導電型
の第2半導体領域、トレンチおよび第2導電型の第3半
導体領域を備え、前記第1半導体領域には、チャネルが
形成され、前記第2半導体領域は、第1導電型の不純物
が低濃度であり、前記第3半導体領域は、前記トレンチ
と前記第2半導体領域との間に位置し、前記第3半導体
領域は、前記第2半導体領域と接合し、前記第3半導体
領域は、キャリアが流れる経路となり、前記第3半導体
領域は、第2導電型の不純物が高濃度である、縦型半導
体装置である。The present invention is directed to a vertical semiconductor device, comprising a first semiconductor region of a first conductivity type, a second semiconductor region of a first conductivity type, a trench and a third semiconductor region of a second conductivity type. A semiconductor region, a channel is formed in the first semiconductor region, the second semiconductor region has a low concentration of impurities of a first conductivity type, and the third semiconductor region has a trench and the second semiconductor region. A third semiconductor region that is located between the third semiconductor region and the second semiconductor region; and the third semiconductor region is a path through which carriers flow, and the third semiconductor region is a second conductive type. This is a vertical semiconductor device having a high impurity concentration.
【0008】上記構成の本発明にかかる縦型半導体装置
によれば、ON抵抗を下げつつ、高耐圧にすることがで
きる。According to the vertical semiconductor device of the present invention having the above structure, it is possible to increase the breakdown voltage while reducing the ON resistance.
【0009】まず、ON抵抗を低減できることを説明す
る。本発明において、第3半導体領域はキャリアが流れ
る経路である。第3半導体領域における第2導電型の不
純物は高濃度なので、第3半導体領域の抵抗を小さくす
ることができる。よって、本発明によれば、縦型半導体
装置のON抵抗を下げることができる。First, the fact that the ON resistance can be reduced will be described. In the present invention, the third semiconductor region is a path through which carriers flow. Since the impurity of the second conductivity type in the third semiconductor region has a high concentration, the resistance of the third semiconductor region can be reduced. Therefore, according to the present invention, the ON resistance of the vertical semiconductor device can be reduced.
【0010】次に、高耐圧にできることを説明する。第
3半導体領域は、トレンチと第2半導体領域との間に位
置している。また、第3半導体領域は、第2半導体領域
と接合している。このため、縦型半導体装置のOFF動
作時において、第3半導体領域には、ゲートの作用によ
りトレンチの壁面から延びてくる空乏層および上記接合
から延びてくる空乏層が広がる。よって、第3半導体領
域における第2導電型の不純物は高濃度であるが、第3
半導体領域に空乏層を広げることができる。一方、第2
半導体領域は、第1導電型の不純物が低濃度なので、上
記接合からの空乏層が広がりやすい。Next, the fact that a high breakdown voltage can be achieved will be described. The third semiconductor region is located between the trench and the second semiconductor region. Further, the third semiconductor region is joined to the second semiconductor region. Therefore, during the OFF operation of the vertical semiconductor device, a depletion layer extending from the wall surface of the trench and a depletion layer extending from the junction spread in the third semiconductor region due to the action of the gate. Therefore, the impurity of the second conductivity type in the third semiconductor region has a high concentration,
The depletion layer can be extended in the semiconductor region. On the other hand, the second
Since the semiconductor region has a low concentration of impurities of the first conductivity type, the depletion layer from the junction tends to spread.
【0011】以上のように、本発明によれば、第2半導
体領域および第3半導体領域に空乏層を広げることがで
きる。As described above, according to the present invention, the depletion layer can be expanded in the second semiconductor region and the third semiconductor region.
【0012】本発明において、上記各半導体領域の不純
物濃度および寸法を所定の条件にすれば、第2半導体領
域および第3半導体領域の完全空乏化が可能となる。こ
れにより、縦型半導体装置の高耐圧化ができる。In the present invention, when the impurity concentration and the size of each of the semiconductor regions are set to predetermined conditions, the second semiconductor region and the third semiconductor region can be completely depleted. Thereby, the withstand voltage of the vertical semiconductor device can be increased.
【0013】本発明は、次の構成を加えることもでき
る。すなわち、本発明は、第2導電型の他の半導体領域
を備え、前記他の半導体領域は、前記第2半導体領域と
接合し、前記他の半導体領域は、第2導電型の不純物が
低濃度である、縦型半導体装置である。According to the present invention, the following configuration can be added. That is, the present invention includes another semiconductor region of the second conductivity type, wherein the other semiconductor region is bonded to the second semiconductor region, and the other semiconductor region has a low concentration of impurities of the second conductivity type. Is a vertical semiconductor device.
【0014】上記構成を加えた本発明によれば、他の半
導体領域と第2半導体領域との接合から形成される空乏
層も、第2半導体領域に広がるので、第2半導体領域に
おける空乏層の広がりをより大きくすることができる。
また、他の半導体領域は第2導電型の不純物が低濃度な
ので、上記接合から形成される空乏層は、他の半導体領
域にも広がる。よって、第2半導体領域、第3半導体領
域および他の半導体領域を全て空乏化することができ、
縦型半導体装置を高耐圧にすることができる。According to the present invention having the above configuration, the depletion layer formed from the junction between the other semiconductor region and the second semiconductor region also extends to the second semiconductor region. Spread can be made larger.
Further, since the other semiconductor region has a low concentration of the second conductivity type impurity, the depletion layer formed from the junction spreads to the other semiconductor region. Therefore, the second semiconductor region, the third semiconductor region, and the other semiconductor regions can all be depleted,
The vertical semiconductor device can have a high breakdown voltage.
【0015】なお、他の半導体領域は、第3半導体領域
と同じようにキャリアが流れる経路となる。これによれ
ば、縦型半導体装置のON抵抗をより下げることが可能
となる。The other semiconductor region is a path through which carriers flow as in the third semiconductor region. According to this, it is possible to further reduce the ON resistance of the vertical semiconductor device.
【0016】本発明は、次の構成を加えることもでき
る。すなわち、本発明は、埋め込み電極および絶縁層を
備え、前記埋め込み電極は、前記トレンチに埋め込まれ
ており、前記絶縁層は、前記埋め込み電極と前記トレン
チの内壁との間に形成され、前記絶縁層の誘電率は、前
記第3半導体領域に蓄積層が形成可能な値である、縦型
半導体装置である。According to the present invention, the following configuration can be added. That is, the present invention includes a buried electrode and an insulating layer, wherein the buried electrode is buried in the trench, the insulating layer is formed between the buried electrode and an inner wall of the trench, and the insulating layer Is a value that allows a storage layer to be formed in the third semiconductor region.
【0017】上記構成を加えた本発明によれば、第3半
導体領域に蓄積層を形成することが可能となるので、O
N抵抗をさらに下げることができる。ON抵抗を下げる
ことができる説明の前に、まず、蓄積層について説明す
る。According to the present invention having the above structure, the storage layer can be formed in the third semiconductor region.
The N resistance can be further reduced. Before explaining that the ON resistance can be reduced, the accumulation layer will be described first.
【0018】蓄積層とは、MOS構造のゲート作用によ
り、第2導電型の半導体領域の絶縁層近傍に、第2導電
型のキャリアが集まることにより形成された層のことで
ある。例えば、半導体領域がn型の場合、蓄積層には、
n型のキャリアが集まっている。また、半導体領域がp
型の場合、蓄積層には、p型のキャリアが集まってい
る。The storage layer is a layer formed by collecting the second conductivity type carriers near the insulating layer in the second conductivity type semiconductor region by the gate function of the MOS structure. For example, if the semiconductor region is n-type,
N-type carriers are gathered. The semiconductor region is p
In the case of the p-type, p-type carriers are collected in the accumulation layer.
【0019】本発明にかかる縦型半導体装置に備えられ
る上記絶縁層の誘電率によれば、第3半導体領域に蓄積
層が形成可能となる。蓄積層は、本来の第3半導体領域
よりも抵抗が小さいので、第3半導体領域に蓄積層を形
成することができれば、ON抵抗をより下げることがで
きる。According to the dielectric constant of the insulating layer provided in the vertical semiconductor device according to the present invention, a storage layer can be formed in the third semiconductor region. Since the storage layer has lower resistance than the original third semiconductor region, the ON resistance can be further reduced if the storage layer can be formed in the third semiconductor region.
【0020】上記絶縁層としては、一般にシリコン酸化
層が用いられる。なお、シリコン酸化層よりも誘電率の
高いシリコン窒化層、さらには高誘電率膜であるSTO
(SrTiO3)膜やBST(BaSrTiO3)膜を用
いることにより、より蓄積層のキャリア濃度を増加させ
ることができ、ON抵抗の低減が図れる。As the insulating layer, a silicon oxide layer is generally used. It should be noted that a silicon nitride layer having a higher dielectric constant than the silicon oxide layer and a high dielectric constant film STO
By using the (SrTiO 3 ) film or the BST (BaSrTiO 3 ) film, the carrier concentration of the storage layer can be further increased, and the ON resistance can be reduced.
【0021】[0021]
【発明の実施の形態】[第1実施形態] {デバイスの構造}図1は、本発明の第1実施形態にか
かる縦型MOS電界効果トランジスタ1の断面図であ
る。縦型MOS電界効果トランジスタ1は、縦型半導体
装置の一例である。縦型MOS電界効果トランジスタ1
は、n+型ドレイン領域15、n+型ソース領域13a、
13bおよび埋め込み電極11を含む。DESCRIPTION OF THE PREFERRED EMBODIMENTS [First Embodiment] {Structure of Device} FIG. 1 is a sectional view of a vertical MOS field-effect transistor 1 according to a first embodiment of the present invention. The vertical MOS field effect transistor 1 is an example of a vertical semiconductor device. Vertical MOS field effect transistor 1
Are the n + -type drain region 15, the n + -type source region 13a,
13b and the buried electrode 11 are included.
【0022】n+型ドレイン領域15は、シリコン基板
に形成されている。n+型ドレイン領域15上には、所
定の間隔で、p-型シリコン単結晶領域17が位置して
いる。p-型シリコン単結晶領域17は、第2半導体領
域の一例である。p-型シリコン単結晶領域17の幅と
しては、例えば、2〜4μmである。p-型シリコン単
結晶領域17のp型不純物濃度としては、例えば、1E
15〜1E16/cm3である。p-型シリコン単結晶領
域17の寸法およびp型不純物濃度は、p-型シリコン
単結晶領域17を完全空乏化できる数値が選択される。The n + type drain region 15 is formed on a silicon substrate. On n + type drain region 15, p − type silicon single crystal region 17 is positioned at a predetermined interval. The p − type silicon single crystal region 17 is an example of a second semiconductor region. The width of the p − type silicon single crystal region 17 is, for example, 2 to 4 μm. As the p-type impurity concentration of the p − -type silicon single crystal region 17, for example, 1E
15 to 1E16 / cm 3 . p - dimensions and p-type impurity concentration of -type silicon single crystal region 17, p - numerical value type silicon single crystal region 17 can be completely depleted is selected.
【0023】n+型ドレイン領域15上であって、p-型
シリコン単結晶領域17間には、トレンチ19が位置し
ている。A trench 19 is located on n + type drain region 15 and between p − type silicon single crystal regions 17.
【0024】n+型ドレイン領域15上であって、トレ
ンチ19とp-型シリコン単結晶領域17との間には、
n+型ドリフト領域21が位置している。n+型ドリフト
領域21は、p-型シリコン単結晶領域17と接合して
いる。この接合を接合部23とする。また、n+型ドリ
フト領域21は、トレンチ19の側面と接触している。On the n + type drain region 15 and between the trench 19 and the p − type silicon single crystal region 17,
An n + type drift region 21 is located. N + type drift region 21 is joined to p − type silicon single crystal region 17. This joint is referred to as a joint 23. Further, n + type drift region 21 is in contact with the side surface of trench 19.
【0025】n+型ドリフト領域21は、第3半導体領
域の一例である。n+型ドリフト領域21の幅として
は、例えば、0.1〜0.5μmである。n+型ドリフ
ト領域21のn型不純物濃度としては、例えば、1E1
7〜1E18/cm3である。n+型ドリフト領域21の
寸法およびn型不純物濃度は、n+型ドリフト領域21
を完全空乏化できる数値が選択される。The n + type drift region 21 is an example of a third semiconductor region. The width of the n + -type drift region 21 is, for example, 0.1 to 0.5 μm. The n-type impurity concentration of the n + -type drift region 21, for example, 1E1
7 to 1E18 / cm 3 . The dimensions and the n-type impurity concentration of the n + -type drift region 21, n + -type drift region 21
Are selected to be completely depleted.
【0026】トレンチ19間であって、n+型ドリフト
領域21およびp-型シリコン単結晶領域17上には、
p型ボディ領域25が位置している。p型ボディ領域2
5は、第1半導体領域の一例である。p型ボディ領域2
5のうち、トレンチ19の近傍に位置する部分を領域3
1とする。Between the trenches 19 and on the n + type drift region 21 and the p − type silicon single crystal region 17,
A p-type body region 25 is located. p-type body region 2
5 is an example of a first semiconductor region. p-type body region 2
5 is located in the vicinity of trench 19 in region 3
Let it be 1.
【0027】n+型ソース領域13a、13bは、トレ
ンチ19間であって、p型ボディ領域25上に位置して
いる。n+型ソース領域13a、13bは、互いに間隔
を設けて形成されている。n+型ソース領域13a、1
3bは、それぞれ、トレンチ19と隣接している。The n + type source regions 13a and 13b are located between the trenches 19 and on the p type body region 25. The n + -type source regions 13a and 13b are formed with an interval therebetween. n + type source regions 13a, 1
3b are adjacent to the trench 19, respectively.
【0028】n+型ソース領域13aとn+型ソース領域
13bとの間であって、p型ボディ領域25上には、p
+型ボディコンタクト領域27が位置している。Between the n + type source region 13a and the n + type source region 13b and on the p type body region 25, p
The + type body contact region 27 is located.
【0029】埋め込み電極11は、トレンチ19に埋め
込まれている。トレンチ19と埋め込み電極11との間
には、シリコン酸化層29が形成されている。埋め込み
電極11は、埋め込み電極11aおよび埋め込み電極1
1bを含む。また、シリコン酸化層29は、シリコン酸
化層29aおよびシリコン酸化層29bを含む。The buried electrode 11 is buried in the trench 19. A silicon oxide layer 29 is formed between the trench 19 and the buried electrode 11. The embedded electrode 11 includes an embedded electrode 11 a and an embedded electrode 1.
1b. The silicon oxide layer 29 includes a silicon oxide layer 29a and a silicon oxide layer 29b.
【0030】埋め込み電極11aおよびシリコン酸化層
29aは、p-型シリコン単結晶領域17とp型ボディ
領域25との境界より下に位置している。シリコン酸化
層29aの厚みは、n+型ドレイン領域15と埋め込み
電極11との電位差に耐えうる値が選択される。例え
ば、200V耐圧の場合は、1μmである。The buried electrode 11 a and the silicon oxide layer 29 a are located below the boundary between the p − type silicon single crystal region 17 and the p type body region 25. The thickness of silicon oxide layer 29a is selected to be a value that can withstand the potential difference between n + -type drain region 15 and embedded electrode 11. For example, in the case of a withstand voltage of 200 V, it is 1 μm.
【0031】一方、埋め込み電極11bおよびシリコン
酸化層29bは、p-型シリコン単結晶領域17とp型
ボディ領域25との境界より上に形成されている。シリ
コン酸化層29bはゲート酸化膜として機能する。この
ため、シリコン酸化層29bの厚みは、要求されるしき
い値電圧に応じて選択される。一般的には、0.1〜
0.2μm程度である。On the other hand, buried electrode 11b and silicon oxide layer 29b are formed above the boundary between p − type silicon single crystal region 17 and p type body region 25. The silicon oxide layer 29b functions as a gate oxide film. Therefore, the thickness of silicon oxide layer 29b is selected according to the required threshold voltage. Generally, 0.1 to
It is about 0.2 μm.
【0032】{デバイスの動作}次に、縦型MOS電界
効果トランジスタ1の動作を説明する。まず、縦型MO
S電界効果トランジスタ1のON動作から説明する。{Operation of Device} Next, the operation of the vertical MOS field effect transistor 1 will be described. First, vertical MO
The description starts with the ON operation of the S field effect transistor 1.
【0033】n+型ドレイン領域15には、正電圧が印
加される。n+型ソース領域13a、13bおよびp+型
ボディコンタクト領域27は、接地される。この状態に
おいて、埋め込み電極11に正電圧を印加すると、p型
ボディ領域25中の電子が、領域31に集まり、n型チ
ャネルが形成される。これにより、n+型ソース領域1
3a、13bから供給された電子は、n型チャネル、n
+型ドリフト領域21を流れ、n+型ドレイン領域15に
到達する。すなわち、縦型MOS電界効果トランジスタ
1は、n+型ドレイン領域15からn+型ソース領域13
a、13bへ電流を流す動作をする。A positive voltage is applied to the n + type drain region 15. N + type source regions 13a and 13b and p + type body contact region 27 are grounded. When a positive voltage is applied to the buried electrode 11 in this state, electrons in the p-type body region 25 gather in the region 31 and an n-type channel is formed. Thereby, the n + type source region 1
Electrons supplied from 3a and 13b are n-type channels, n
It flows through the + type drift region 21 and reaches the n + type drain region 15. That is, the vertical MOS field-effect transistor 1, n + -type drain region 15 of n + -type source region 13
a, an operation of flowing a current to 13b.
【0034】縦型MOS電界効果トランジスタ1によれ
ば、ON動作時の抵抗を下げることができる。すなわ
ち、n型+ドリフト領域21のn型不純物濃度は、高濃
度なので、n+型ドリフト領域21の抵抗は低くなる。
したがって、その分だけ、縦型MOS電界効果トランジ
スタ1のON動作時の抵抗を下げることができる。この
ように、縦型MOS電界効果トランジスタ1によれば、
ON動作時の抵抗を下げることができるので、縦型MO
S電界効果トランジスタ1の消費電力を下げることが可
能となる。この効果は、後で説明する他の実施形態でも
生じる。According to the vertical MOS field effect transistor 1, the resistance during the ON operation can be reduced. That, n-type impurity concentration of the n-type + drift region 21, the high concentration, the resistance of the n + -type drift region 21 becomes lower.
Therefore, the resistance of the vertical MOS field effect transistor 1 during the ON operation can be reduced accordingly. Thus, according to the vertical MOS field effect transistor 1,
Since the resistance during ON operation can be reduced, the vertical MO
The power consumption of the S field effect transistor 1 can be reduced. This effect also occurs in other embodiments described later.
【0035】次に、縦型MOS電界効果トランジスタ1
のOFF動作を説明する。埋め込み電極11を正電圧か
ら接地にすると、領域31のn型チャネルはなくなる。
これにより、縦型MOS電界効果トランジスタ1は、n
+型ドレイン領域15からn+型ソース領域13a、13
bへ電流を流さない動作をする。Next, the vertical MOS field effect transistor 1
Will be described. When the buried electrode 11 is grounded from a positive voltage, the n-type channel in the region 31 disappears.
Thus, the vertical MOS field effect transistor 1 has n
From the + type drain region 15 to the n + type source regions 13a, 13
The operation is performed such that no current flows to b.
【0036】パワーMOS電界効果トランジスタ1がO
FFのとき、ドレインに正の電圧が加えられると、その
電圧の増加に伴い空乏層が、p-型シリコン単結晶領域
17およびn+型ドリフト領域21中に広まっていく。
つまり、p-型シリコン単結晶領域17中には、接合部
23から延びてきた空乏層が広がる。n+型ドリフト領
域21中には、接合部23から延びてきた空乏層および
MOSのゲート作用によりトレンチ19の側面から延び
てきた空乏層が広がる。When the power MOS field effect transistor 1 is O
When a positive voltage is applied to the drain at the time of the FF, the depletion layer spreads in the p − -type silicon single crystal region 17 and the n + -type drift region 21 as the voltage increases.
That is, the depletion layer extending from the junction 23 expands in the p − -type silicon single crystal region 17. In the n + -type drift region 21, a depletion layer extending from the junction 23 and a depletion layer extending from the side surface of the trench 19 due to the gate action of the MOS are spread.
【0037】縦型MOS電界効果トランジスタ1によれ
ば、耐圧は、n+型ドリフト領域21およびp-型シリコ
ン単結晶領域17を完全空乏化することによって得られ
る。n+型ドリフト領域21は、接合部23から延びて
きた空乏層およびトレンチ19の側面から延びてきた空
乏層が広がる。n+型ドリフト領域21は、n型不純物
濃度とその幅を適切に設定すれば、完全空乏化すること
ができる。一方、p -型シリコン単結晶領域17中に
は、接合部23から延びてきた空乏層が広がる。p-型
シリコン単結晶領域17中のp型不純物濃度は、p-型
シリコン単結晶領域17を完全空乏化することができる
ように、低い値に設定される。According to the vertical MOS field effect transistor 1,
Then, the withstand voltage is n+Type drift region 21 and p-Type silico
Is obtained by completely depleting the single crystal region 17.
You. n+Mold drift region 21 extends from junction 23
Depletion layer and the sky extending from the side of the trench 19
The poor layer spreads. n+Type drift region 21 is an n-type impurity
Complete depletion with proper setting of concentration and width
Can be. On the other hand, p -Type silicon single crystal region 17
The depletion layer extending from the junction 23 expands. p-Type
The p-type impurity concentration in the silicon single crystal region 17 is p-Type
The silicon single crystal region 17 can be completely depleted
So that it is set to a low value.
【0038】このように、縦型MOS電界効果トランジ
スタ1によれば、n+型ドリフト領域21およびp-型シ
リコン単結晶領域17を完全空乏化することによって、
耐圧を高くすることができる。この効果は、後で説明す
る他の実施形態でも生じる。As described above, according to the vertical MOS field effect transistor 1, by completely depleting the n + -type drift region 21 and the p -- type silicon single crystal region 17,
The withstand voltage can be increased. This effect also occurs in other embodiments described later.
【0039】{デバイスの製造方法}次に、縦型MOS
電界効果トランジスタ1の製造工程を説明する。図3、
図4および図5は、これを説明するための工程図であ
る。{Device Manufacturing Method} Next, a vertical MOS
The manufacturing process of the field effect transistor 1 will be described. FIG.
FIGS. 4 and 5 are process diagrams for explaining this.
【0040】図3(A)に示すように、n+型ドレイン
領域15を含むシリコン基板を準備する。ドレイン領域
15上に例えば、エピタキシャル成長により、厚さ10
〜15μmのp-型シリコン単結晶領域17を形成す
る。As shown in FIG. 3A, a silicon substrate including an n + type drain region 15 is prepared. On the drain region 15, for example, a thickness of 10
-Type silicon single crystal region 17 - p of 15 m.
【0041】次に、公知の方法を用いてp型ボディ領域
25を形成する。さらに、p-型シリコン単結晶領域1
7とp型ボディ領域25を選択的にエッチングし、所定
の間隔でトレンチ19を形成する。トレンチ19はn+
型ドレイン領域15に到達している。Next, a p-type body region 25 is formed by using a known method. Further, the p - type silicon single crystal region 1
7 and the p-type body region 25 are selectively etched to form trenches 19 at predetermined intervals. Trench 19 is n +
Has reached the mold drain region 15.
【0042】図3(B)に示すように、トレンチ19に
薄い酸化膜33を形成し、その後、リン酸ガラス(PS
G:Phosphosilicate glass)膜
35をCVD法によりトレンチ19に埋め込む。As shown in FIG. 3B, a thin oxide film 33 is formed in the trench 19, and thereafter, a phosphate glass (PS) is formed.
G: Phosphosilicate glass film 35 is buried in the trench 19 by the CVD method.
【0043】図3(C)に示すように、その後、アニー
ル処理を行い、p-型シリコン単結晶領域17のうち、
トレンチ19近傍にn+型ドリフト領域21を形成す
る。n+型ドリフト領域21の寸法およびn型不純物濃
度は、埋め込むPSG膜35のリン濃度、トレンチ19
側壁の酸化膜33の厚み、アニール温度によって制御す
ることができる。Then, as shown in FIG. 3C, an annealing process is performed, and the p - type silicon single crystal region 17 is
An n + -type drift region 21 is formed near the trench 19. The dimensions of the n + type drift region 21 and the n type impurity concentration are determined by the phosphorus concentration of the PSG film 35 to be embedded and the trench 19.
It can be controlled by the thickness of the oxide film 33 on the side wall and the annealing temperature.
【0044】図4(A)に示すように、公知の方法を用
いて、埋め込んだPSG膜35と酸化膜33とを取り除
く。As shown in FIG. 4A, the buried PSG film 35 and oxide film 33 are removed by a known method.
【0045】図4(B)に示すように、例えば、熱酸化
により、トレンチ19の内壁に、厚さ約1μmのシリコ
ン酸化層29aを形成する。次に、例えば、CVD法に
より、トレンチ19が埋まるように、厚さ0.5〜1.
5μmのn+型ポリシリコン層37を形成する。As shown in FIG. 4B, a silicon oxide layer 29a having a thickness of about 1 μm is formed on the inner wall of the trench 19 by, for example, thermal oxidation. Next, for example, the thickness is set to 0.5 to 1.
An n + -type polysilicon layer 37 of 5 μm is formed.
【0046】図4(C)に示すように、公知の方法を用
いて、ポリシリコン層37およびシリコン酸化層29a
をエッチバックすることにより、p型ボディ領域25と
p-型シリコン単結晶領域17との境界より下にのみ、
ポリシリコン層37およびシリコン酸化層29aが残る
ようにする。As shown in FIG. 4C, the polysilicon layer 37 and the silicon oxide layer 29a are formed by a known method.
Is etched back only below the boundary between p-type body region 25 and p − -type silicon single crystal region 17.
The polysilicon layer 37 and the silicon oxide layer 29a are left.
【0047】図5(A)に示すように、例えば、熱酸化
により、トレンチ19のうち露出している内壁に、厚さ
0.1μm程度のシリコン酸化層29bを形成する。As shown in FIG. 5A, a silicon oxide layer 29b having a thickness of about 0.1 μm is formed on the exposed inner wall of the trench 19 by, for example, thermal oxidation.
【0048】図5(B)に示すように、例えば、フォト
リソグラフィとエッチングにより、埋め込み電極11a
上のシリコン酸化層29bを除去する。As shown in FIG. 5B, the buried electrode 11a is formed by photolithography and etching, for example.
The upper silicon oxide layer 29b is removed.
【0049】次に、例えば、CVD法により、トレンチ
19が埋まるように、ポリシリコン層を形成し、その
後、このポリシリコン層を、エッチバックすることによ
り、図5(C)に示すように、トレンチ19内のみにポ
リシリコン層が残るようにする。このポリシリコン層が
埋め込み電極11bとなる。Next, a polysilicon layer is formed by, for example, a CVD method so as to fill the trench 19, and then this polysilicon layer is etched back, as shown in FIG. The polysilicon layer is left only in the trench 19. This polysilicon layer becomes the buried electrode 11b.
【0050】図1に示すように、公知の方法を用いてp
型ボディ領域25中に、n+型ソース領域13a、13
bおよびp+型ボディコンタクト領域27を形成する。
以上の工程により、縦型MOS電界効果トランジスタ1
が完成する。As shown in FIG. 1, p is determined using a known method.
N + type source regions 13a and 13
The b and p + type body contact regions 27 are formed.
Through the above steps, the vertical MOS field effect transistor 1
Is completed.
【0051】後の実施形態にかかる縦型MOS電界効果
トランジスタも、縦型MOS電界効果トランジスタ1の
製造方法と同様の方法を用いて作製することができる。The vertical MOS field-effect transistor according to the later embodiment can also be manufactured by using the same method as the manufacturing method of the vertical MOS field-effect transistor 1.
【0052】なお、第1実施形態にかかる縦型MOS電
界効果トランジスタ1における各領域の導電型は、逆の
導電型でもよい。これは、後で説明する他の実施形態で
も言えることである。The conductivity type of each region in the vertical MOS field effect transistor 1 according to the first embodiment may be the opposite conductivity type. This can be applied to other embodiments described later.
【0053】また、第1実施形態は、縦型MOS電界効
果トランジスタである。本発明はこれに限定されず、他
の縦型半導体装置にも適用することができる。これは、
後で説明する他の実施形態でも言えることである。The first embodiment is a vertical MOS field effect transistor. The present invention is not limited to this, and can be applied to other vertical semiconductor devices. this is,
The same can be said for other embodiments described later.
【0054】[第2実施形態] {デバイスの構造}図2は、本発明の第2実施形態にか
かる縦型MOS電界効果トランジスタ3の断面図であ
る。図1に示す第1実施形態にかかる縦型MOS電界効
果トランジスタ1と同等の機能を有する部分には、同一
符号を付してある。縦型MOS電界効果トランジスタ3
が縦型MOS電界効果トランジスタ1と相違する部分を
説明し、同じ部分については説明を省略する。[Second Embodiment] {Structure of Device} FIG. 2 is a sectional view of a vertical MOS field-effect transistor 3 according to a second embodiment of the present invention. Portions having functions equivalent to those of the vertical MOS field effect transistor 1 according to the first embodiment shown in FIG. 1 are denoted by the same reference numerals. Vertical MOS field effect transistor 3
Will be described for portions different from the vertical MOS field effect transistor 1, and description of the same portions will be omitted.
【0055】縦型MOS電界効果トランジスタ3は、n
-型シリコン単結晶領域39を備えている。n-型シリコ
ン単結晶領域39は、p-型シリコン単結晶領域17と
n+型ドレイン領域15との間に位置している。n-型シ
リコン単結晶領域39は、p-型シリコン単結晶領域1
7と接合している。この接合を接合部41とする。The vertical MOS field effect transistor 3 has n
- and a -type silicon single crystal region 39. N − type silicon single crystal region 39 is located between p − type silicon single crystal region 17 and n + type drain region 15. The n − type silicon single crystal region 39 is a p − type silicon single crystal region 1
7. This joint is referred to as a joint 41.
【0056】n-型シリコン単結晶領域39の幅として
は、例えば、2〜4μmである。n-型シリコン単結晶
領域39のn型不純物濃度としては、例えば、1E15
〜1E16/cm3である。n-型シリコン単結晶領域3
9の寸法およびn型不純物濃度は、n-型シリコン単結
晶領域39を完全空乏化できる数値が選択される。The width of n − type silicon single crystal region 39 is, for example, 2 to 4 μm. The n − -type silicon single crystal region 39 has an n-type impurity concentration of, for example, 1E15
11E16 / cm 3 . n - type silicon single crystal region 3
As the size of 9 and the n-type impurity concentration, a numerical value capable of completely depleting the n − -type silicon single crystal region 39 is selected.
【0057】縦型MOS電界効果トランジスタ1によれ
ば、次の二つの効果が生じる。一つ目から説明する。先
程説明したように、耐圧向上のためには完全空乏化が望
ましい。縦型MOS電界効果トランジスタ3は、接合部
41を備えている。接合部41からも空乏層が広がるの
で、p-型シリコン単結晶領域17の完全空乏化が容易
となる。また、n-型シリコン単結晶領域39中のn型
不純物濃度は低いので、n-型シリコン単結晶領域39
自体にも、空乏層が広まりやすい。よって、n-型シリ
コン単結晶領域39の完全空乏化も容易となる。According to the vertical MOS field effect transistor 1, the following two effects occur. It will be explained from the first. As described above, complete depletion is desirable for improving the breakdown voltage. The vertical MOS field-effect transistor 3 has a junction 41. Since the depletion layer extends from the junction 41, it is easy to completely deplete the p − -type silicon single crystal region 17. Further, n - since -type silicon n-type impurity concentration in the single crystal region 39 is low, n - -type silicon single crystal region 39
In itself, the depletion layer tends to spread. Therefore, complete depletion of n − -type silicon single crystal region 39 is also facilitated.
【0058】次に、二つ目を説明する。n-型シリコン
単結晶領域39はドリフト領域として機能する。その分
だけ、ドリフト領域の面積が広がる。よって、ON抵抗
を下げることが可能となる。Next, the second will be described. N − type silicon single crystal region 39 functions as a drift region. The area of the drift region is increased accordingly. Therefore, the ON resistance can be reduced.
【0059】{デバイス性能のシミュレーション}縦型
MOS電界効果トランジスタ3は、高耐圧でありなが
ら、ON動作時の抵抗が小さいことを、シミュレーショ
ンにより確認した。まず、シミュレーションの対象とな
る縦型MOS電界効果トランジスタ3の条件を、図6を
用いながら説明する。図6は、縦型MOS電界効果トラ
ンジスタ3の断面の一部である。{Simulation of Device Performance} It has been confirmed by simulation that the vertical MOS field effect transistor 3 has a high withstand voltage and a small resistance during the ON operation. First, the conditions of the vertical MOS field effect transistor 3 to be simulated will be described with reference to FIG. FIG. 6 is a part of a cross section of the vertical MOS field effect transistor 3.
【0060】 n+型ドリフト領域21のn型不純物濃度:1×1017
/cm3 n+型ドリフト領域21の幅:0.3μm n+型ドリフト領域21の深さ:16.5μm p-型シリコン単結晶領域17のp型不純物濃度:1×
1016/cm3 p-型シリコン単結晶領域17の幅:1.2μm p-型シリコン単結晶領域17の深さ:12.5μm n-型シリコン単結晶領域39のn型不純物濃度:1×
1015/cm3 n-型シリコン単結晶領域39の幅:1.2μm n-型シリコン単結晶領域39の深さ:4μm シリコン酸化層29aの厚み:1μm シリコン酸化層29bの厚み:0.1μm 上記条件は、縦型MOS電界効果トランジスタ3の耐圧
が200V程度となり、かつn+型ドリフト領域21、
n-型シリコン単結晶領域39およびp-型シリコン単結
晶領域17が完全空乏化(つまり、Reduced Surface
Field分布)できる条件である。The n-type impurity concentration of the n + -type drift region 21 is 1 × 10 17
/ Cm 3 n + -type drift region 21 width: 0.3 μm n + -type drift region 21 depth: 16.5 μm p - type silicon single crystal region 17 p-type impurity concentration: 1 ×
The width of the 10 16 / cm 3 p − -type silicon single crystal region 17: 1.2 μm The depth of the p − -type silicon single crystal region 17: 12.5 μm The n-type impurity concentration of the n − -type silicon single crystal region 39: 1 ×
10 15 / cm 3 Width of n - type silicon single crystal region 39: 1.2 μm Depth of n - type silicon single crystal region 39: 4 μm Thickness of silicon oxide layer 29a: 1 μm Thickness of silicon oxide layer 29b: 0.1 μm The above condition is that the withstand voltage of the vertical MOS field-effect transistor 3 is about 200 V, and the n + -type drift region 21,
The n − -type silicon single crystal region 39 and the p − -type silicon single crystal region 17 are completely depleted (that is, reduced surface).
Field distribution).
【0061】なお、シリコン酸化層29aの厚みは、ド
レイン電圧が200Vでもシリコン酸化層29aが絶縁
破壊しない値を選んだ。また、シリコン酸化層29bの
厚みは、縦型MOS電界効果トランジスタ3が所望の立
ち上がり電圧(約1V)を得られるような値を選んだ。The thickness of the silicon oxide layer 29a was selected so that the silicon oxide layer 29a did not break down even when the drain voltage was 200V. The thickness of the silicon oxide layer 29b is selected so that the vertical MOS field-effect transistor 3 can obtain a desired rising voltage (about 1 V).
【0062】上記条件の下で、縦型MOS電界効果トラ
ンジスタ3の耐圧特性(ドレイン電圧VDとドレイン電
流IDとの関係)のシミュレーションをした。その結果
を図7のグラフに示す。なお、ゲート電圧などの条件は
次のとおりである。Under the above conditions, a simulation of the breakdown voltage characteristics (the relationship between the drain voltage V D and the drain current I D ) of the vertical MOS field effect transistor 3 was performed. The results are shown in the graph of FIG. The conditions such as the gate voltage are as follows.
【0063】 ゲート電圧:0V ドレイン電圧:0〜250Vの範囲において、0.2V
づつ電圧を上昇 ソース電圧:0V ボディ電圧:0V 図7のグラフから分かるように、ドレイン電圧VDが2
15Vで、縦型MOS電界効果トランジスタ3はブレー
クダウンしている。よって、上記縦型MOS電界効果ト
ランジスタ3の条件によれば、耐圧が215Vであるこ
とが分かる。Gate voltage: 0 V Drain voltage: 0.2 V in the range of 0 to 250 V
Increments voltage increase source voltage: 0V body voltage: As can be seen from the graph of 0V Figure 7, the drain voltage V D is 2
At 15 V, the vertical MOS field-effect transistor 3 has broken down. Therefore, it is understood that the breakdown voltage is 215 V according to the conditions of the vertical MOS field-effect transistor 3.
【0064】次に、縦型MOS電界効果トランジスタ3
のゲート電圧VGとドレイン電流IDとの関係のシミュレ
ーションをした。その結果を図8のグラフに示す。な
お、ゲート電圧などの条件は次のとおりである。Next, the vertical MOS field effect transistor 3
Simulation of the relationship between the gate voltage V G and the drain current I D of the. The results are shown in the graph of FIG. The conditions such as the gate voltage are as follows.
【0065】 ゲート電圧:0〜20Vの範囲において、0.05Vづ
つ電圧を上昇 ドレイン電圧: 0.1V ソース電圧:0V ボディ電圧:0V 図8に示すグラフから、VG=10Vのもとにおける縦
型MOS電界効果トランジスタ3のON抵抗(RON)を
計算すると、0.178Ω・mm2となる。計算式は、
次のとおりである。Gate voltage: Increased by 0.05 V in the range of 0 to 20 V Drain voltage: 0.1 V Source voltage: 0 V Body voltage: 0 V From the graph shown in FIG. 8, the vertical direction under V G = 10 V When the ON resistance (R ON ) of the type MOS field effect transistor 3 is calculated, it is 0.178 Ω · mm 2 . The calculation formula is
It is as follows.
【0066】RON=(VD/ID)×セルサイズ ここで、 VD:0.1V ID:VG=10Vの時の値 セルサイズ:図6では3μm 次に、この結果とシリコンリミットとの関係を説明す
る。図9は、シリコンリミットを示すグラフである。横
軸は、ブレークダウン電圧VBである。縦軸は、ON動
作時の抵抗RONである。シリコンリミットとは、「PO
WER MOSFETS Theory and Ap
plications」(発行John Wiley&
Sons社、著者D.A.Grant)で記述されてい
るように、耐圧によって一義的に決まるON抵抗の最小
値である。図9から分かるように、ブレークダウン電圧
の上昇に伴い、ON抵抗は上昇する。[0066] Here R ON = (V D / I D) × cell size, V D: 0.1V I D: the value cell size when V G = 10V: FIG 6 3 [mu] m Then, the result and silicon The relationship with the limit will be described. FIG. 9 is a graph showing the silicon limit. The horizontal axis is the breakdown voltage V B. The vertical axis is the resistance R ON during the ON operation. What is Silicon Limit?
WER MOSFETS Theory and Ap
applications (issued by John Wiley &
Sons, author D.S. A. As described in (Grant), this is the minimum value of the ON resistance uniquely determined by the breakdown voltage. As can be seen from FIG. 9, the ON resistance increases as the breakdown voltage increases.
【0067】図9のグラフ中の点Aは、上記実験例結果
を示している。シリコンリミットでは、ブレークダウン
電圧が215Vのとき、ON抵抗は、約0.4Ω・mm
2となる。これに対して、縦型MOS電界効果トランジ
スタ3によれば、ブレークダウン電圧が215Vのと
き、ON抵抗は、0.178Ω・mm2となる。つま
り、1/2以下となっている。したがって、縦型MOS
電界効果トランジスタ3は、高耐圧でありながら、ON
抵抗は小さいことが分かる。The point A in the graph of FIG. 9 shows the result of the above experimental example. In the silicon limit, when the breakdown voltage is 215 V, the ON resistance is about 0.4 Ω · mm
It becomes 2 . On the other hand, according to the vertical MOS field effect transistor 3, when the breakdown voltage is 215 V, the ON resistance is 0.178 Ω · mm 2 . That is, it is 1/2 or less. Therefore, vertical MOS
The field effect transistor 3 is turned on while having a high withstand voltage.
It can be seen that the resistance is small.
【0068】このように、縦型MOS電界効果トランジ
スタ3によれば、シリコンリミットを越えた性能が得ら
れる。As described above, according to the vertical MOS field effect transistor 3, a performance exceeding the silicon limit can be obtained.
【0069】次に、縦型MOS電界効果トランジスタ3
の電位分布をシミュレーションした。図10は、OFF
動作時において、ドレイン電圧が200Vにおける縦型
MOS電界効果トランジスタ3の電位分布を示す図であ
る。Next, the vertical MOS field effect transistor 3
Was simulated. FIG. 10 is OFF
FIG. 7 is a diagram showing a potential distribution of the vertical MOS field-effect transistor 3 when the drain voltage is 200 V during operation.
【0070】図10に示すよう空乏層エッジが形成され
ていることから、p-型シリコン単結晶領域17、n+型
ドリフト領域21およびn-型シリコン単結晶領域39
の領域が完全空乏化していることが分かる。また、等電
位線がほぼ均一の間隔で分布していることが分かる。Since a depletion layer edge is formed as shown in FIG. 10, p − type silicon single crystal region 17, n + type drift region 21 and n − type silicon single crystal region 39
It can be seen that the region is completely depleted. In addition, it can be seen that equipotential lines are distributed at substantially uniform intervals.
【0071】[その他]第1および第2実施形態にかか
る縦型MOS電界効果トランジスタ1、3では、シリコ
ン酸化層29aを用いている。シリコン酸化層29aの
かわりに高誘電体絶縁層を用いることにより、ON抵抗
のさらなる低減が図れる。高誘電体絶縁層としては、例
えば、シリコン窒化層、STO(SrTiO3)層、BS
T(BaSrTiO3)層がある。STO層やBST層のよ
うに、誘電率が高い物質を用いた場合、図1および図2
に示すn+型ドリフト領域21に、よりキャリア濃度の
高い蓄積層が形成可能となる。これにより、ON抵抗を
さらに低下させることができる。[Others] In the vertical MOS field effect transistors 1 and 3 according to the first and second embodiments, a silicon oxide layer 29a is used. By using a high dielectric insulating layer instead of the silicon oxide layer 29a, the ON resistance can be further reduced. As the high dielectric insulating layer, for example, a silicon nitride layer, an STO (SrTiO 3 ) layer, a BS
There is a T (BaSrTiO 3 ) layer. When a substance having a high dielectric constant such as an STO layer or a BST layer is used, FIGS.
It is possible to form an accumulation layer having a higher carrier concentration in the n + -type drift region 21 shown in FIG. Thereby, the ON resistance can be further reduced.
【0072】これを具体的に説明する。STO層やBS
T層で実現可能な比誘電率として、100を設定し、他
の条件は変えずに、シミュレーションからON抵抗(R
ON)を求めると、0.113Ω・mm2となった。これ
からも分かるように、高誘電体絶縁層を用いることによ
り、ON抵抗がさらに低下する。This will be specifically described. STO layer and BS
The relative dielectric constant achievable in the T layer is set to 100, and the other conditions are not changed, and the ON resistance (R
ON ) was 0.113 Ω · mm 2 . As can be seen from the above, the use of the high dielectric insulating layer further reduces the ON resistance.
【図1】本発明の第1実施形態にかかる縦型MOS電界
効果トランジスタ1の断面図である。FIG. 1 is a cross-sectional view of a vertical MOS field-effect transistor 1 according to a first embodiment of the present invention.
【図2】本発明の第2実施形態にかかる縦型MOS電界
効果トランジスタ3の断面図である。FIG. 2 is a sectional view of a vertical MOS field-effect transistor 3 according to a second embodiment of the present invention.
【図3】本発明の第1実施形態にかかる縦型MOS電界
効果トランジスタ1の製造工程を説明するための工程図
である。FIG. 3 is a process diagram for explaining a manufacturing process of the vertical MOS field-effect transistor 1 according to the first embodiment of the present invention.
【図4】本発明の第1実施形態にかかる縦型MOS電界
効果トランジスタ1の製造工程を説明するための工程図
である。FIG. 4 is a process diagram for explaining a manufacturing process of the vertical MOS field-effect transistor 1 according to the first embodiment of the present invention.
【図5】本発明の第1実施形態にかかる縦型MOS電界
効果トランジスタ1の製造工程を説明するための工程図
である。FIG. 5 is a process diagram for explaining a manufacturing process of the vertical MOS field-effect transistor 1 according to the first embodiment of the present invention.
【図6】本発明の第2実施形態にかかる縦型MOS電界
効果トランジスタ3の部分断面図である。FIG. 6 is a partial sectional view of a vertical MOS field-effect transistor 3 according to a second embodiment of the present invention.
【図7】本発明の第2実施形態にかかる縦型MOS電界
効果トランジスタ3のドレイン電圧とドレイン電流との
関係をシミュレーションし、その結果を表したグラフで
ある。FIG. 7 is a graph showing a result of simulating a relationship between a drain voltage and a drain current of a vertical MOS field-effect transistor 3 according to a second embodiment of the present invention.
【図8】本発明の第2実施形態にかかる縦型MOS電界
効果トランジスタ3のゲート電圧とドレイン電流との関
係をシミュレーションし、その結果を表したグラフであ
る。FIG. 8 is a graph showing a simulation result of a relationship between a gate voltage and a drain current of a vertical MOS field-effect transistor 3 according to a second embodiment of the present invention.
【図9】シリコンリミットを示すグラフである。FIG. 9 is a graph showing a silicon limit.
【図10】本発明の第2実施形態にかかる縦型MOS電
界効果トランジスタ3の電位分布のシミュレーションを
示す図である。FIG. 10 is a diagram showing a simulation of a potential distribution of a vertical MOS field-effect transistor 3 according to a second embodiment of the present invention.
【符号の説明】 1、3 縦型MOS電界効果トランジスタ 11、11a、11b 埋め込み電極 13a、13b n+型ソース領域 15 n+型ドレイン領域 17 p―型シリコン単結晶領域 19 トレンチ 21 n+型ドリフト領域 23 接合部 25 p型ボディ領域 27 p+型ボディコンタクト領域 29、29a、29b シリコン酸化層 31 領域 33 シリコン酸化層 35 n+型ポリシリコン層 37 ポリシリコン層 39 n―型シリコン単結晶領域 41 接合部 43 等電位線[Description of Signs] 1, 3 Vertical MOS field effect transistor 11, 11a, 11b Buried electrode 13a, 13b n + source region 15 n + drain region 17 p- silicon single crystal region 19 trench 21 n + drift Region 23 junction 25 p-type body region 27 p + -type body contact region 29, 29a, 29b silicon oxide layer 31 region 33 silicon oxide layer 35 n + -type polysilicon layer 37 polysilicon layer 39 n-type silicon single crystal region 41 Junction 43 equipotential line
Claims (3)
第2半導体領域および第2導電型の第3半導体領域を備
え、 前記第1半導体領域には、チャネルが形成され、 前記第2半導体領域は、第1導電型の不純物が低濃度で
あり、 前記第3半導体領域は、前記トレンチと前記第2半導体
領域との間に位置し、 前記第3半導体領域は、前記第2半導体領域と接合し、 前記第3半導体領域は、キャリアが流れる経路となり、 前記第3半導体領域は、第2導電型の不純物が高濃度で
ある、縦型半導体装置。1. A vertical semiconductor device, comprising: a first semiconductor region of a first conductivity type; a trench; a second semiconductor region of a first conductivity type; and a third semiconductor region of a second conductivity type. A channel is formed in the semiconductor region, the second semiconductor region has a low concentration of impurities of a first conductivity type, and the third semiconductor region is located between the trench and the second semiconductor region. The third semiconductor region is bonded to the second semiconductor region, the third semiconductor region serves as a path through which carriers flow, and the third semiconductor region has a high impurity concentration of a second conductivity type. Type semiconductor device.
ある、縦型半導体装置。2. The semiconductor device according to claim 1, further comprising another semiconductor region of a second conductivity type, wherein the other semiconductor region is joined to the second semiconductor region, and the other semiconductor region is of a second conductivity type. A vertical semiconductor device having a low impurity concentration.
り、 前記絶縁層は、前記埋め込み電極と前記トレンチの内壁
との間に形成され、 前記絶縁層の誘電率は、前記第3半導体領域に蓄積層が
形成可能な値である、縦型半導体装置。3. The device according to claim 1, further comprising a buried electrode and an insulating layer, wherein the buried electrode is buried in the trench, and the insulating layer is provided between the buried electrode and an inner wall of the trench. The vertical semiconductor device is formed, wherein the dielectric constant of the insulating layer is a value at which a storage layer can be formed in the third semiconductor region.
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