JP2001095240A - Rush-current preventing circuit having input over- voltage limiting function - Google Patents
Rush-current preventing circuit having input over- voltage limiting functionInfo
- Publication number
- JP2001095240A JP2001095240A JP27011899A JP27011899A JP2001095240A JP 2001095240 A JP2001095240 A JP 2001095240A JP 27011899 A JP27011899 A JP 27011899A JP 27011899 A JP27011899 A JP 27011899A JP 2001095240 A JP2001095240 A JP 2001095240A
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- Japan
- Prior art keywords
- circuit
- input
- switch element
- parallel
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Emergency Protection Circuit Devices (AREA)
- Dc-Dc Converters (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】この発明は、スイッチング電
源の入力回路に設けた過電圧制限機能を備えた突入電流
防止回路に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inrush current prevention circuit having an overvoltage limiting function provided in an input circuit of a switching power supply.
【０００２】[0002]
【従来の技術】従来のスイッチング電源の入力回路に設
けた突入電流防止回路の回路構成は、図４に示す通りで
ある。ＤＣ／ＤＣコンバータを構成する主トランス１０
８の１次入力側には、１次コイル１１１と主スイッチ素
子１０９より成る直列回路にコンデンサ１０７が並列接
続してある。また、コンデンサ１０７の入力側には、限
流抵抗１０３と、そのバイパス回路に設けた第１のスイ
ッチ素子１０１と、第１のスイッチ素子１０１のコレク
タ端子〜ベース端子間に設けた抵抗１０４と、前記ベー
ス端子〜１次入力回路のグランド・ライン間に挿入した
抵抗１０５と、コンデンサ１０７に並列接続した入力電
圧監視回路１０６と、コレクタ端子を第１のスイッチ素
子のベース端子に接続すると共にエミッタ端子をグラン
ド・ラインに接続し、ベース端子を入力電圧監視回路１
０６の出力端子に接続した第２のスイッチ素子１０２に
よって突入電流防止回路を構成している。2. Description of the Related Art A circuit configuration of a conventional inrush current prevention circuit provided in an input circuit of a switching power supply is as shown in FIG. Main transformer 10 constituting DC / DC converter
The capacitor 107 is connected in parallel to a series circuit composed of a primary coil 111 and a main switch element 109 on the primary input side of the switch 8. On the input side of the capacitor 107, a current limiting resistor 103, a first switch element 101 provided in a bypass circuit thereof, a resistor 104 provided between a collector terminal and a base terminal of the first switch element 101, A resistor 105 inserted between the base terminal and the ground line of the primary input circuit, an input voltage monitoring circuit 106 connected in parallel to a capacitor 107, a collector terminal connected to the base terminal of the first switch element, and an emitter terminal To the ground line and the base terminal to the input voltage monitoring circuit 1.
The inrush current prevention circuit is constituted by the second switch element 102 connected to the output terminal 06.
【０００３】[0003]
【発明が解決しようとする課題】ＤＣ／ＤＣコンバータ
を起動させると、入力監視回路１０６によって検出され
た電圧に基づいて第２のスイッチ素子１０２がオンとな
るので、第１のスイッチ素子１０１はオフのままであ
る。従って、入力電圧は限流抵抗１０３を介してコンデ
ンサ１０７を充電させ、コンデンサ１０７の両端電圧が
入力電圧Ｖi に近づくと充電は完了する。これに伴って
第２のスイッチ素子１０２がオフとなるので、第１のス
イッチ素子１０１がオンとなり、限流抵抗１０３の両端
を短絡させる。即ち、入力回路に流入した突入電流は限
流抵抗１０３によって限流され、コンデンサ１０７を介
して１次コイル１１１と主スイッチ素子１０９に流入す
ることになる。When the DC / DC converter is started, the second switch element 102 is turned on based on the voltage detected by the input monitoring circuit 106, so that the first switch element 101 is turned off. Remains. Therefore, the input voltage to charge a capacitor 107 through a current limiting resistor 103, charging the voltage across the capacitor 107 approaches the input voltage V i is completed. Accordingly, the second switch element 102 is turned off, so that the first switch element 101 is turned on, and both ends of the current limiting resistor 103 are short-circuited. That is, the inrush current flowing into the input circuit is limited by the current limiting resistor 103, and flows into the primary coil 111 and the main switch element 109 via the capacitor 107.
【０００４】しかし乍ら、突入電流防止回路には入力過
電圧を抑制する機能を備えていないので、入力回路に過
電圧が印加された時は、突入電流防止回路とコンデンサ
１０７を介して、１次コイル１１１と主スイッチ素子１
０９に過電圧が印加されることになる。入力過電圧によ
る主スイッチ素子の破壊を防ぐためには、主スイッチ素
子の耐圧を高めなくてはならない。しかし乍ら、平常時
においては高耐圧のスイッチ素子を低圧で使用すること
になるので、コンバータ効率の低下等の不具合が生ず
る。However, since the inrush current prevention circuit does not have a function of suppressing an input overvoltage, when an overvoltage is applied to the input circuit, the primary coil is connected via the inrush current prevention circuit and the capacitor 107. 111 and main switch element 1
09 will be applied with an overvoltage. In order to prevent the destruction of the main switch element due to the input overvoltage, the breakdown voltage of the main switch element must be increased. However, in normal times, a switch element having a high withstand voltage is used at a low voltage, which causes problems such as a decrease in converter efficiency.
【０００５】[0005]
【課題を解決するための手段】この発明は、上述した従
来の突入電流防止回路に入力過電圧抑制機能を付加しよ
うとするものであって、スイッチ素子を並列接続した限
流抵抗を１次入力回路における一線（グランド・ライン
であってもよい）に直列に挿入しておき、ＤＣ／ＤＣコ
ンバータの起動時においては、限流抵抗によって制限さ
れた電流が１次入力回路へ流入するように限流抵抗に並
列接続してあるスイッチ素子をオフとし、定常状態にお
いては前記スイッチ素子をオンとして限流抵抗を短絡さ
せ抵抗損を減少させる。また、入力電圧が所定の電圧以
上に上昇した場合には上記定電圧設定回路を作動させ、
ＤＣ／ＤＣコンバータの１次入力側には所定の電圧以上
の電圧が印加されないようにした。SUMMARY OF THE INVENTION The present invention is intended to add an input overvoltage suppression function to the above-described conventional inrush current prevention circuit, and comprises a current limiting resistor having a switching element connected in parallel to a primary input circuit. At the start of the DC / DC converter, so that the current limited by the current limiting resistor flows into the primary input circuit. The switch element connected in parallel with the resistor is turned off, and in a steady state, the switch element is turned on to short-circuit the current limiting resistor and reduce the resistance loss. Further, when the input voltage rises above a predetermined voltage, the constant voltage setting circuit is activated,
A voltage higher than a predetermined voltage is not applied to the primary input side of the DC / DC converter.
【０００６】[0006]
【発明の実施の形態】この発明の実施例を図１と図２お
よび図３を参照しながら説明する。図１は、この発明に
よる第１の実施例を示すブロック図である。ＤＣ／ＤＣ
コンバータを構成する主トランス８の１次コイル１１と
主スイッチ素子９より成る直列回路には、コンデンサ７
が並列接続してある。コンデンサ７の入力側には限流抵
抗５と、そのバイパス回路に設けた第１のスイッチ素子
１と、第１のスイッチ素子１のコレクタ端子〜ベース端
子間に設けた抵抗６およびベース端子とグランド・ライ
ン間に設けた定電圧設定回路（例えば、ツエナーダイオ
ードでもよい）３と、限流抵抗５とコンデンサ７との間
に並列接続した入力電圧監視回路４と、コレクタ端子を
第１のスイッチ素子１のベース端子に接続すると共にエ
ミッタ端子をグランド・ラインに接続し、ベース端子を
入力電圧監視回路４の出力端子に接続した第２のスイッ
チ素子２によって入力電圧制限機能を備えた突入電流防
止回路を構成している。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIGS. 1, 2 and 3. FIG. FIG. 1 is a block diagram showing a first embodiment according to the present invention. DC / DC
A series circuit including a primary coil 11 of a main transformer 8 and a main switch element 9 constituting a converter includes a capacitor 7
Are connected in parallel. On the input side of the capacitor 7, a current limiting resistor 5, a first switch element 1 provided in a bypass circuit thereof, a resistor 6 and a base terminal provided between a collector terminal and a base terminal of the first switch element 1, and a ground. A constant voltage setting circuit (for example, a Zener diode) 3 provided between the lines, an input voltage monitoring circuit 4 connected in parallel between the current limiting resistor 5 and the capacitor 7, and a collector terminal connected to the first switch element 1 is connected to the base terminal, the emitter terminal is connected to the ground line, and the base terminal is connected to the output terminal of the input voltage monitoring circuit 4. Is composed.
【０００７】次に、この発明による入力過電圧制限機能
を備えた突入電流防止回路の動作特性を説明する。ＤＣ
／ＤＣコンバータを起動させる時に流入する突入電流
は、突入電流防止回路に設けてある限流抵抗５によって
抑制されることは既述の通りである。Next, the operation characteristics of the inrush current prevention circuit having the input overvoltage limiting function according to the present invention will be described. DC
As described above, the inrush current flowing when the / DC converter is activated is suppressed by the current limiting resistor 5 provided in the inrush current prevention circuit.
【０００８】ＤＣ／ＤＣコンバータの入力電圧Ｖi の許
容電圧範囲を Ｖ1 ≦Ｖi ≦Ｖ2 とし、第１のスイッチ素子１のゲート端子とグランド・
ライン間に設けた定電圧設定回路（例えばツエナー・ダ
イオード）３の設定電圧Ｖz をＶ2 より少し大きい電圧
Ｖ3 にしておくと、入力電圧がＶ1 〜Ｖ3 の範囲では１
次入力回路にそのまま印加されるが、Ｖ3 以上の電圧は
定電圧設定回路３によって阻止される。図３（ａ）は１
次入力回路に流入した過電圧波形を示しており、図３
（ｂ）は定電圧設定回路によって抑制された入力電圧の
並列コンデンサ７における端子電圧波形を示しており、
入力過電圧が定電圧設定回路の設定電圧Ｖz によって抑
制されることを示している。The input voltage V of the DC / DC converteriForgiveness
Capable voltage range is V1≤Vi≤VTwo And the gate terminal of the first switch element 1 and the ground
A constant voltage setting circuit provided between lines (for example, Zener
Set voltage V of 3)zTo VTwoSlightly larger voltage
VThreeIf the input voltage is V1~ VThree1 in the range
It is applied to the next input circuit as it is,ThreeThe above voltage is
Blocked by the constant voltage setting circuit 3. FIG.
FIG. 3 shows an overvoltage waveform flowing into the next input circuit.
(B) is the input voltage suppressed by the constant voltage setting circuit.
5 shows a terminal voltage waveform in a parallel capacitor 7;
The input overvoltage is the set voltage V of the constant voltage setting circuit.zSuppressed by
Is controlled.
【０００９】図２は、この発明による第２の実施例を示
すブロック図であって、並列コンデンサ７の入力側には
分圧抵抗１６と１７より成る第１の分圧抵抗回路が並列
接続してあり、分圧抵抗１６と１７の接続点からの検出
信号は入力電圧監視回路４に入力する。また、第２の分
圧抵抗回路を構成する抵抗１４と１５の接続点からの検
出信号と、入力電圧監視回路４からの検出信号は１次入
力回路に並列接続してある定電圧設定回路３に入力す
る。FIG. 2 is a block diagram showing a second embodiment according to the present invention. A first voltage dividing resistor circuit comprising voltage dividing resistors 16 and 17 is connected in parallel to the input side of a parallel capacitor 7. The detection signal from the connection point between the voltage dividing resistors 16 and 17 is input to the input voltage monitoring circuit 4. The detection signal from the connection point of the resistors 14 and 15 constituting the second voltage-dividing resistor circuit and the detection signal from the input voltage monitoring circuit 4 are connected to the constant voltage setting circuit 3 connected in parallel to the primary input circuit. To enter.
【００１０】１次入力回路のグランド・ラインには限流
抵抗５が直列に挿入してあり、その両端にはＦＥＴ１が
並列接続してある。ＦＥＴ１のソース端子は抵抗６を介
してゲート端子に接続してあり、ゲート端子は抵抗１３
を介して定電圧設定回路３からの検出信号を入力するよ
うに構成してある。入力電圧監視回路４、定電圧設定回
路３、限流抵抗５、およびＦＥＴ１の作用は図１におけ
るものと同一であるので説明は省略する。A current limiting resistor 5 is inserted in series to the ground line of the primary input circuit, and FETs 1 are connected in parallel at both ends. The source terminal of the FET 1 is connected to the gate terminal via the resistor 6, and the gate terminal is connected to the resistor 13.
And a detection signal from the constant voltage setting circuit 3 is inputted thereto. The functions of the input voltage monitoring circuit 4, the constant voltage setting circuit 3, the current limiting resistor 5, and the FET 1 are the same as those in FIG.
【００１１】[0011]
【発明の効果】以上説明したように、１次入力回路にお
ける一線に直列に挿入した限流抵抗の両端に並列接続し
たスイッチ素子をオン・オフ制御することによって突入
電流を制限できる。また、突入電流防止回路に簡単な定
電圧設定回路を並列接続することにより、入力過電圧を
抑制することができる。従って、瞬時的な過電圧からコ
ンバータ破損を防ぐことができるので、コンバータを構
成するスイッチ素子は耐圧の低い安価な素子でよい。。As described above, the inrush current can be limited by controlling the on / off of the switch element connected in parallel to both ends of the current limiting resistor inserted in series with the line in the primary input circuit. Also, by connecting a simple constant voltage setting circuit in parallel to the inrush current prevention circuit, input overvoltage can be suppressed. Therefore, it is possible to prevent the converter from being damaged due to an instantaneous overvoltage, so that the switching element constituting the converter may be an inexpensive element having a low withstand voltage. .
【図１】この発明による第１の実施例を示すブロック
図。FIG. 1 is a block diagram showing a first embodiment according to the present invention.
【図２】この発明による第２の実施例を示すブロック
図。FIG. 2 is a block diagram showing a second embodiment according to the present invention.
【図３】波形図。FIG. 3 is a waveform diagram.
【図４】従来技術による突入電流防止回路のブロック
図。FIG. 4 is a block diagram of a rush current prevention circuit according to the related art.
１，２，９ スイッチ素子 ３ 定電圧設定回路 ４ 入力電圧監視回路 ５，６，１３〜１７ 抵抗 ７ コンデンサ ８ 主トランス 1, 2, 9 switch element 3 constant voltage setting circuit 4 input voltage monitoring circuit 5, 6, 13 to 17 resistor 7 capacitor 8 main transformer
Claims (2)
おけるトランスの１次コイルと主スイッチ素子より成る
直列回路に並列接続したコンデンサと、該コンデンサの
入力側の１次回路に並列接続した入力電圧監視回路と、
該入力電圧監視回路の入力側の１次入力回路に直列に挿
入した限流抵抗と、該限流抵抗のバイパス回路を構成す
るコレクタ端子とベース端子との間に抵抗を接続した第
１のスイッチ素子と、前記入力電圧監視回路からの出力
信号をベース端子に入力して第１のスイッチ素子をオン
・オフ制御する第２のスイッチ素子によって構成した突
入電流防止回路において、 前記第１のスイッチ素子のベース端子と１次入力回路の
グランド・ラインとの間に定電圧設定回路を設け、トラ
ンスの１次コイルと主スイッチ素子より成る１次入力回
路への入力過電圧を制限するようにしたことを特徴とす
る入力過電圧制限機能を備えた突入電流防止回路。1. A capacitor connected in parallel to a series circuit comprising a primary coil of a transformer and a main switch element in a primary input circuit of a DC / DC converter, and an input voltage connected in parallel to a primary circuit on the input side of the capacitor. A monitoring circuit;
A current limiting resistor inserted in series with a primary input circuit on the input side of the input voltage monitoring circuit, and a first switch having a resistor connected between a collector terminal and a base terminal forming a bypass circuit of the current limiting resistor An inrush current prevention circuit comprising an element and a second switch element for inputting an output signal from the input voltage monitoring circuit to a base terminal and controlling on / off of a first switch element, wherein the first switch element A constant voltage setting circuit is provided between the base terminal of the transformer and the ground line of the primary input circuit to limit the input overvoltage to the primary input circuit comprising the primary coil of the transformer and the main switch element. Inrush current prevention circuit with input overvoltage limiting function.
列接続した第１の分圧抵抗回路から入力電圧を検出する
入力電圧監視回路と、前記第１の分圧抵抗回路の入力側
の１次入力回路に並列接続した第２の分圧抵抗回路から
の検出電圧と前記入力電圧監視回路からの出力信号とを
入力する１次入力回路に並列接続した定電圧設定回路
と、１次入力回路におけるグランド・ラインに直列に挿
入した限流抵抗と、前記入力電圧監視回路からの検出信
号を入力してオン・オフ制御されるＦＥＴを前記限流抵
抗の両端に並列接続して構成し、 ＤＣ／ＤＣコンバータの起動に伴う入力電圧を入力電圧
監視回路によって検出すると共に限流抵抗によって突入
電流を制限するようにＦＥＴを機能させ、かつ入力過電
圧を定電圧設定回路によって制限するようにしたことを
特徴とする請求項１に記載の入力過電圧制限機能を備え
た突入電流防止回路。2. An input voltage monitoring circuit for detecting an input voltage from a first voltage dividing resistor circuit connected in parallel to a primary input circuit on an input side of a capacitor; A constant voltage setting circuit connected in parallel to a primary input circuit for inputting a detection voltage from a second voltage dividing resistor circuit connected in parallel to a next input circuit and an output signal from the input voltage monitoring circuit; And a current limiting resistor inserted in series with a ground line and an FET which is supplied with a detection signal from the input voltage monitoring circuit and is turned on and off by being connected in parallel to both ends of the current limiting resistor. The input voltage monitoring circuit detects the input voltage accompanying the start of the / DC converter, and the FET functions to limit the inrush current by the current limiting resistor, and the input overvoltage is limited by the constant voltage setting circuit. Rush current prevention circuit having an input overvoltage limiting function according to claim 1, characterized in that the.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27011899A JP3574599B2 (en) | 1999-09-24 | 1999-09-24 | Inrush current prevention circuit with input overvoltage limit function |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27011899A JP3574599B2 (en) | 1999-09-24 | 1999-09-24 | Inrush current prevention circuit with input overvoltage limit function |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2001095240A true JP2001095240A (en) | 2001-04-06 |
| JP3574599B2 JP3574599B2 (en) | 2004-10-06 |
Family
ID=17481809
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27011899A Expired - Fee Related JP3574599B2 (en) | 1999-09-24 | 1999-09-24 | Inrush current prevention circuit with input overvoltage limit function |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3574599B2 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2002003184A2 (en) * | 2000-07-05 | 2002-01-10 | Koninklijke Philips Electronics N.V. | Device |
| WO2006072216A1 (en) * | 2005-01-08 | 2006-07-13 | Emerson Network Power Energy Systems Ab | A switching power supply with overvoltage protection and its overvoltage protection method |
| US7166933B2 (en) | 2002-10-21 | 2007-01-23 | Nec Corporation | Submarine power feeding branching device for submarine power feeding system having submarine feeding cables arranged in mesh pattern |
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| JPWO2018199042A1 (en) * | 2017-04-24 | 2020-05-14 | パナソニックＩｐマネジメント株式会社 | Power conversion system |
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| US8836287B2 (en) * | 2011-05-03 | 2014-09-16 | Apple Inc. | Time-domain multiplexing of power and data |
-
1999
- 1999-09-24 JP JP27011899A patent/JP3574599B2/en not_active Expired - Fee Related
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2002003184A2 (en) * | 2000-07-05 | 2002-01-10 | Koninklijke Philips Electronics N.V. | Device |
| WO2002003184A3 (en) * | 2000-07-05 | 2002-08-01 | Koninkl Philips Electronics Nv | Device |
| US6665199B2 (en) | 2000-07-05 | 2003-12-16 | Koninklijke Philips Electronics N.V. | Device supplied with current of limited strength |
| US7166933B2 (en) | 2002-10-21 | 2007-01-23 | Nec Corporation | Submarine power feeding branching device for submarine power feeding system having submarine feeding cables arranged in mesh pattern |
| US7276811B2 (en) | 2002-10-21 | 2007-10-02 | Nec Corporation | Submarine power feeding system having submarine feeding cables and power feeding branching devices |
| WO2006072216A1 (en) * | 2005-01-08 | 2006-07-13 | Emerson Network Power Energy Systems Ab | A switching power supply with overvoltage protection and its overvoltage protection method |
| US7932632B2 (en) | 2005-01-08 | 2011-04-26 | Emerson Network Power Energy Systems Ab | Switching power supply with overvoltage protection and overvoltage protection method thereof |
| JPWO2018199042A1 (en) * | 2017-04-24 | 2020-05-14 | パナソニックＩｐマネジメント株式会社 | Power conversion system |
| CN109327182A (en) * | 2018-11-06 | 2019-02-12 | 许昌许继风电科技有限公司 | A kind of DC bus over-pressure safety device, control method and a kind of servo-driver |
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| JP3574599B2 (en) | 2004-10-06 |
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