JP2001016769A - Manufacture fo field electron/emission surge absorber element - Google Patents
Manufacture fo field electron/emission surge absorber elementInfo
- Publication number
- JP2001016769A JP2001016769A JP11186717A JP18671799A JP2001016769A JP 2001016769 A JP2001016769 A JP 2001016769A JP 11186717 A JP11186717 A JP 11186717A JP 18671799 A JP18671799 A JP 18671799A JP 2001016769 A JP2001016769 A JP 2001016769A
- Authority
- JP
- Japan
- Prior art keywords
- substrate member
- substrate
- frame member
- frame
- power supply
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Abstract
Description
【００１】[0101]
【発明の属する技術分野】この発明は、電源線や通信線
等を伝って侵入して来るサージ等の過電圧から電子機器
の電子回路を保護するために、線間あるは各線とグラン
ドとの間に挿入接続されるサージ吸収素子に係り、特
に、電界電子放出現象を用いたサージ吸収素子の製造方
法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for protecting an electronic circuit of an electronic device from an overvoltage such as a surge that enters through a power line or a communication line, or between lines or between each line and a ground. In particular, the present invention relates to a method for manufacturing a surge absorbing element using a field electron emission phenomenon.
【００２】[0092]
【従来の技術】従来、図２２に示すように、電子機器の
電源線や通信線等の線Ｌ1，Ｌ2間、あるいは各線とＧＮ
Ｄ（グランド）との間にサージ吸収素子72を接続し、誘
導雷等のサージから電子回路73を保護することが行われ
ている。すなわち、線Ｌ1，Ｌ2間あるいは線Ｌ1，Ｌ2−
ＧＮＤ間に、サージ吸収素子72の定格以上のサージ電圧
が印加される場合には、上記サージ吸収素子72が導通し
てサージをバイパスし、電子回路73を保護する仕組みで
ある。2. Description of the Related Art Conventionally, as shown in FIG. 22, between a line L1 and a line L2 such as a power supply line and a communication line of an electronic device, or between each line and a GN.
A surge absorbing element 72 is connected between D and ground to protect the electronic circuit 73 from surges such as induced lightning. That is, between the lines L1 and L2 or between the lines L1 and L2-
When a surge voltage higher than the rating of the surge absorbing element 72 is applied between GND, the surge absorbing element 72 conducts to bypass the surge and protect the electronic circuit 73.
【００３】このようなサージ吸収素子72としては、放電
間隙における放電現象を利用するガスアレスタや、電圧
非直線特性を備えた高抵抗体素子であるバリスタ、ある
いはｐｎ接合形半導体のアバランシェ（電子雪崩）効果
を利用したシリコンサージアブソーバなど様々な種類が
存在しているが、最近になって電界電子放出現象を用い
たサージ吸収素子が新たに加えられることとなった。As such a surge absorbing element 72, a gas arrester utilizing a discharge phenomenon in a discharge gap, a varistor which is a high-resistance element having a nonlinear voltage characteristic, or an avalanche (electron avalanche) of a pn junction type semiconductor is used. There are various types such as silicon surge absorbers utilizing the effect, but recently a surge absorbing element using a field electron emission phenomenon has been newly added.
【００４】この電界電子放出現象を用いたサージ吸収素
子は、特開平９−298833号、特開平10−285793号等に記
載されている。図２３に示すように、そこで開示されて
いる電界電子放出型サージ吸収素子74は、ｎ形半導体よ
り成る第１の基板部材75と第２の基板部材76とを所定の
距離を隔てて対向配置させ、両基板部材の対向面周縁部
をスペーサも兼ねた枠部材77を間に介して気密封止する
ことによって形成された外囲器78を備えており、該外囲
器78内は１０-6〜１０-8Torrの高真空状態に維持されて
いる。また、第１の基板部材75の内面には、ｎ形半導体
より成る多数のエミッタ・コーン79が、所定の間隔をお
いて突設されている。該エミッタ・コーン79は先端が尖
った円錐または角錐形状をなしており、その先端部79ａ
が第２の基板部材76の内面に向いている。Surge absorbing elements using this field electron emission phenomenon are described in JP-A-9-298833 and JP-A-10-285793. As shown in FIG. 23, in the field electron emission type surge absorbing element 74 disclosed therein, a first substrate member 75 and a second substrate member 76 made of an n-type semiconductor are opposed to each other at a predetermined distance. And an envelope 78 formed by hermetically sealing the peripheral edges of the opposing surfaces of both substrate members via a frame member 77 also serving as a spacer, and the inside of the envelope 78 is 10 −. It is maintained in a high vacuum state of 6 to 10 -8 Torr. On the inner surface of the first substrate member 75, a number of emitter cones 79 made of an n-type semiconductor are protruded at predetermined intervals. The emitter cone 79 has a pointed cone or pyramid shape, and the tip 79a
Faces the inner surface of the second substrate member 76.
【００５】エミッタ・コーン79の表面をも含んだ第１の
基板部材75の内面と第２の基板部材76の内面には、Ｎ
ｂ、Ｗ、Ｍｏ、Ｃｒ、Ｔｉ、Ｔｈ、Ｓｉ、Ｎｉ、Ｌａ、
Ｇｅ、Ａｌ等よりなる薄膜や、Ｗ及びＺｒの二層構造、
あるいは以上の各物質の中、少なくとも１種類を含んだ
炭化物、酸化物、窒化物、無機化合物より構成される保
護膜80が被覆されている。上記第１の基板部材75及び第
２の基板部材76の外面には、それぞれ第１の外部電極81
及び第２の外部電極82が形成され、各外部電極81，82に
はカソード端子83及びアノード端子84が接続されてい
る。そして、各端子83，84を線Ｌ1，Ｌ2あるいはＧＮＤ
に接続することにより、上記電界電子放出型サージ吸収
素子74は、図２２に示したサージ吸収素子72と同様に、
線Ｌ1，Ｌ2間あるいは線Ｌ1，Ｌ2−ＧＮＤ間に挿入接続
されることとなる。The inner surface of the first substrate member 75 including the surface of the emitter cone 79 and the inner surface of the second substrate member 76 have N
b, W, Mo, Cr, Ti, Th, Si, Ni, La,
A thin film made of Ge, Al, etc., a two-layer structure of W and Zr,
Alternatively, a protective film 80 made of a carbide, oxide, nitride, or inorganic compound containing at least one of the above substances is coated. First external electrodes 81 are provided on the outer surfaces of the first substrate member 75 and the second substrate member 76, respectively.
A second external electrode 82 is formed, and a cathode terminal 83 and an anode terminal 84 are connected to the external electrodes 81 and 82, respectively. Then, each terminal 83, 84 is connected to the line L1, L2 or GND.
By connecting to the above, the field electron emission type surge absorbing element 74 is similar to the surge absorbing element 72 shown in FIG.
It is inserted and connected between the lines L1 and L2 or between the lines L1 and L2 and GND.
【００６】しかして、上記線Ｌ1，Ｌ2間あるいは線Ｌ
1，Ｌ2−ＧＮＤ間にサージ等の定格以上の過電圧が印加
され、カソード側のエミッタ・コーン先端部79ａに強い
電界集中が生じると、量子力学的なトンネル効果によっ
て、ｎ形半導体内の電子がポテンシャル障壁を越えて真
空中に放出される、いわゆる電界電子放出現象が生じ
る。放出された電子は高い電位のアノード側、すなわち
第２の基板部材76の内面で捕捉される結果、第２の基板
部材76及び第１の基板部材75間に電流が流れる先駆放電
が生成され、この先駆放電はその後真空火花放電（真空
アーク放電）に移行することとなる。The line L1 and L2 or the line L
1. When an overvoltage exceeding a rating such as a surge is applied between L2 and GND and a strong electric field concentration occurs at the tip 79a of the emitter cone on the cathode side, electrons in the n-type semiconductor are caused by quantum mechanical tunnel effect. A so-called field electron emission phenomenon that is emitted into a vacuum beyond the potential barrier occurs. The emitted electrons are captured on the anode side of the high potential, that is, on the inner surface of the second substrate member 76, so that a precursor discharge in which a current flows between the second substrate member 76 and the first substrate member 75 is generated, This precursor discharge then shifts to vacuum spark discharge (vacuum arc discharge).
【００７】上記先駆放電が真空火花放電に移行する仕組
みとしては、以下のものが考えられる。すなわち、上記
先駆放電時の電子放出によってエミッタ・コーン先端部
79ａの電流密度が増加して生じた熱エネルギの作用で、
エミッタ・コーン79の表面を覆っている保護膜80を構成
する金属から金属蒸気が発生したり、先駆放電による電
子がアノード側に衝突する結果生じる熱エネルギによっ
て、第２の基板部材76の内面を覆っている保護膜80の金
属から同じく金属蒸気が発生し、これら電荷を帯びた金
属蒸気が電流を形成する素となって真空火花放電が生起
される。また、外囲器78内を完全な真空にするのは実際
上困難であり、放電空間を構成する物質の表面には僅か
ながらガス分子が吸着あるいは付着しているのである
が、これらのガス分子が先駆放電の衝撃で空間内に放出
され、このイオン化されたガス分子が電流を形成する素
となることも、真空火花放電を促進する要因として挙げ
られる。The following is conceivable as a mechanism for shifting the precursor discharge to a vacuum spark discharge. That is, the emission of electrons during the precursor discharge causes the tip of the emitter cone
The effect of the heat energy generated by the increase in the current density of 79a,
The metal constituting the protective film 80 covering the surface of the emitter cone 79 generates metal vapor, and heat energy generated as a result of electrons colliding with the anode side due to the precursor discharge causes the inner surface of the second substrate member 76 to be exposed. Similarly, metal vapor is generated from the metal of the overlying protective film 80, and these charged metal vapors serve as elements for forming a current, thereby generating a vacuum spark discharge. Further, it is practically difficult to make the inside of the envelope 78 a complete vacuum, and gas molecules are slightly adsorbed or adhered to the surface of the material constituting the discharge space. Is released into the space by the impact of the precursor discharge, and the ionized gas molecules serve as elements for forming a current. This is also a factor promoting vacuum spark discharge.
【００８】上記の電界電子放出現象は、エミッタ・コー
ン79に集中する電界強度が所定以上に高まった時点で初
めて生じるものであり、これは所定値以上の電圧が両電
極間に印加された場合にのみ両電極間に電流が流れるこ
とを意味するものである。すなわち、両端子83，84間に
印加される電圧の値と流れる電流との間には非直線的な
関係が現れるため、定格以上の過電圧が印加された場合
にのみ導通して過電圧をバイパスするというサージ吸収
作用を発揮することが可能となる。The above-mentioned field electron emission phenomenon occurs only when the intensity of the electric field concentrated on the emitter cone 79 rises above a predetermined value. This occurs when a voltage higher than a predetermined value is applied between both electrodes. Only means that a current flows between both electrodes. That is, since a non-linear relationship appears between the value of the voltage applied between both terminals 83 and 84 and the flowing current, conduction occurs only when an overvoltage exceeding the rating is applied, thereby bypassing the overvoltage. It is possible to exhibit the surge absorbing effect.
【００９】しかも、半導体中の電子の速度に比べ、真空
中の電子は散乱を受けることなく進行するため、この電
界電子放出型サージ吸収素子74は極めて高速に動作可能
となる。また、ｐ形半導体とｎ形半導体との接合構造を
有していないため、シリコンサージアブソーバのように
静電容量が大きくなるという問題も生じない。Further, compared with the speed of the electrons in the semiconductor, the electrons in the vacuum travel without being scattered, so that the field electron emission type surge absorbing element 74 can operate at an extremely high speed. Further, since the semiconductor device does not have a junction structure between the p-type semiconductor and the n-type semiconductor, there is no problem that the capacitance is increased unlike the silicon surge absorber.
【００１０】図２４は、このような電界電子放出型サー
ジ吸収素子74によるサージ吸収特性を示すものであり、
ピーク電圧値が３ｋＶの原サージ波形に対するサージ吸
収波形を示すグラフである。図示の通り、サージ電圧が
印加されると、瞬時にピークが約２.３２ｋＶの先駆放
電が生成した後、直ちに真空火花放電に移行して約４０
０Ｖの安定したサージ吸収波形が得られる様子が示され
ている。FIG. 24 shows the surge absorption characteristics of such a field electron emission type surge absorbing element 74.
It is a graph which shows the surge absorption waveform with respect to the original surge waveform whose peak voltage value is 3 kV. As shown in the figure, when a surge voltage is applied, a precursor discharge having a peak of about 2.32 kV is instantaneously generated.
A state in which a stable surge absorption waveform of 0 V is obtained is shown.
【００１１】この電界電子放出型サージ吸収素子74にと
って最も重要な構成要素であるエミッタ・コーン79は、
ｎ形Ｓｉ基板の表面に各エミッタ・コーン79に対応した
円形の酸化膜マスクを形成すると共に、該Ｓｉ基板の表
面にエッチング処理を施して酸化膜マスクで覆われてい
ない部分をややオーバーエッチング気味に浸食させ、最
後に酸化膜マスクを除去することによって形成される。The emitter cone 79, which is the most important component of the field emission type surge absorbing element 74,
A circular oxide mask corresponding to each of the emitter cones 79 is formed on the surface of the n-type Si substrate, and the surface of the Si substrate is subjected to an etching process to slightly overetch portions not covered with the oxide mask. And finally removing the oxide mask.
【００１２】この電界電子放出型サージ吸収素子74の場
合、外囲器78の内部を高真空状態に維持しておく必要が
あり、そのためには第１の基板部材75と枠部材77の一方
の端面間の接合、及び第２の基板部材76と枠部材77の他
方の端面間の接合が、十分に高い気密性を保って実現さ
れる必要がある。第１の基板部材75及び第２の基板部材
76と枠部材77とを接合する方法としては、フリットガラ
スや低融点ガラスを用いて融着させる方法、あるいはポ
リイミド系の有機接着剤を用いて接着させる方法があ
る。しかしながら、両者とも接合工程において発生する
余計なガスを除去する工程を設ける必要があり、また特
に有機接着剤を用いた接合方法の場合には使用の過程に
おいても徐々にガス放出が生じるのみならず、比較的高
温の環境下において使用すると接合強度が低下するとい
う問題がある。このため、これら接合方法の欠点を克服
するものとして、最近では陽極接合法が専ら用いられて
いる。In the case of the field emission type surge absorbing element 74, it is necessary to maintain the inside of the envelope 78 in a high vacuum state. For this purpose, one of the first substrate member 75 and one of the frame members 77 is required. The joining between the end faces and the joining between the second substrate member 76 and the other end face of the frame member 77 need to be realized with sufficiently high airtightness. First substrate member 75 and second substrate member
As a method of joining the frame member 77 to the frame member 77, there is a method of fusing using frit glass or low melting point glass, or a method of bonding using a polyimide-based organic adhesive. However, in both cases, it is necessary to provide a step of removing unnecessary gas generated in the bonding step, and particularly in the case of a bonding method using an organic adhesive, not only gas is gradually released even in the use process, but also However, when used in a relatively high temperature environment, there is a problem that the bonding strength is reduced. For this reason, recently, the anodic bonding method is exclusively used to overcome the disadvantages of these bonding methods.
【００１３】この陽極接合法は、大略以下の工程によっ
て実現される。まず、図２５に示すように、ホットプレ
ート85上に第２の基板部材76を、第２の外部電極82を下
にして載置すると共に、内部にＮａ＋やＨ＋などの可動
イオンを含むガラスによって構成した枠部材77の一方の
端面を、第２の基板部材76の対向面周縁に重ねる。この
枠部材77の他方の端面には、電極板86が圧着される。ま
た、上記第２の基板部材76の第２の外部電極82には、ホ
ットプレート85を経由して直流電源87のプラス側が接続
されると共に、上記電極板86には直流電源87のマイナス
側が接続される。そして、上記ホットプレート42によっ
て、第２の基板部材76及び枠部材77が摂氏２００〜６０
０度に加熱された状態で、上記直流電源87より５０〜１
０００Ｖの直流電圧が印加される。This anodic bonding method is realized by the following steps. First, as shown in FIG. 25, a second substrate member 76 is placed on a hot plate 85 with the second external electrode 82 down, and contains mobile ions such as Na + and H + inside. One end surface of the frame member 77 made of glass is overlapped with the peripheral edge of the facing surface of the second substrate member 76. An electrode plate 86 is crimped to the other end surface of the frame member 77. The plus side of the DC power supply 87 is connected to the second external electrode 82 of the second substrate member 76 via the hot plate 85, and the minus side of the DC power supply 87 is connected to the electrode plate 86. Is done. The hot plate 42 causes the second substrate member 76 and the frame member 77 to move from 200 to 60 degrees Celsius.
In the state of being heated to 0 degrees, 50 to 1
A DC voltage of 000 V is applied.
【００１４】この結果、図２６に示すように、一定時間
経過後には枠部材77中の陽イオン88がマイナス側（すな
わち枠部材77の上端面近傍）に移動すると共に、第２の
基板部材76の対向面周縁近傍にマイナスの電荷が集中し
て空間電荷層89が現れ、大きな吸引力を伴う化学結合が
生じて陽極接合が実現される。As a result, as shown in FIG. 26, after a certain period of time, the cations 88 in the frame member 77 move to the minus side (ie, near the upper end surface of the frame member 77), and the second substrate member 76 In the vicinity of the periphery of the opposing surface, the negative charges are concentrated and the space charge layer 89 appears, and a chemical bond accompanied by a large attractive force is generated to realize anodic bonding.
【００１５】以上のようにして、第２の基板部材76の対
向面周縁と枠部材77の一方の端面との強固な接合が完了
した後、図２７に示すように、今度は真空雰囲気中にお
いて、ホットプレート85上に第１の基板部材75を第１の
外部電極81を下にして載置すると共に、枠部材77の他方
の端面を第１の基板部材75の対向面周縁に当接させる。
また、第１の基板部材75の第１の外部電極81には、ホッ
トプレート85経由して直流電源87のプラス側が接続され
ると共に、第２の基板部材76の第２の外部電極82には直
流電源87のマイナス側が接続される。そして、上記ホッ
トプレート85によって、第１の基板部材75及び枠部材77
が摂氏２００〜６００度に加熱された状態で、上記直流
電源87より５０〜１０００Ｖの直流電圧が印加される。
この結果、上記と同様のメカニズムによって、第１の基
板部材75の対向面周縁と枠部材77との強固な陽極接合が
実現され、高い気密性を備えた外囲器78が完成するので
ある。After the strong bonding between the peripheral edge of the second substrate member 76 and one end surface of the frame member 77 is completed as described above, as shown in FIG. Then, the first substrate member 75 is placed on the hot plate 85 with the first external electrode 81 facing down, and the other end surface of the frame member 77 is brought into contact with the peripheral edge of the facing surface of the first substrate member 75. .
The positive side of a DC power supply 87 is connected to the first external electrode 81 of the first substrate member 75 via a hot plate 85, and the second external electrode 82 of the second substrate member 76 is connected to the first external electrode 81 of the first substrate member 75. The negative side of DC power supply 87 is connected. Then, the first substrate member 75 and the frame member 77 are moved by the hot plate 85.
Is heated to 200 to 600 degrees Celsius, and a DC voltage of 50 to 1000 V is applied from the DC power supply 87.
As a result, a strong anodic bonding between the peripheral edge of the first substrate member 75 and the frame member 77 is realized by the same mechanism as described above, and the envelope 78 having high airtightness is completed.
【００１６】この陽極接合法は、溶融ガラスや接着剤を
使用しないため、両基板部材75，76と枠部材77とを高い
位置精度で接合することができると共に、接合後の脱ガ
ス処理が不要である利点を備えている。Since this anodic bonding method does not use a molten glass or an adhesive, the two substrate members 75 and 76 and the frame member 77 can be bonded with high positional accuracy, and degassing after bonding is unnecessary. It has the advantage of being.
【００１７】[0017]
【発明が解決しようとする課題】ところで、この電界電
子放出型サージ吸収素子74の動作電圧（定格電圧）は、
外囲器78内の真空度やエミッタ・コーン79表面の仕事関
数、エミッタ・コーン先端部79ａと第２の基板部材76の
内面との間の距離、あるいはエミッタ・コーン先端部79
ａの尖鋭度によって決定される。すなわち、電界電子放
出型サージ吸収素子74の動作電圧を比較的低く設定する
必要がある場合には、外囲器78内の真空度を高める方
法、エミッタ・コーン79の仕事関数を低下させる方法、
エミッタ・コーン先端部79ａと第２の基板部材76内面と
の間の距離をより短縮化させる方法、あるいはエミッタ
・コーンの先端部79ａをより尖鋭化させる方法が理論上
は考えられる。The operating voltage (rated voltage) of the field electron emission type surge absorbing element 74 is as follows.
The degree of vacuum in the envelope 78, the work function of the surface of the emitter cone 79, the distance between the emitter cone tip 79a and the inner surface of the second substrate member 76, or the emitter cone tip 79
It is determined by the sharpness of a. That is, when it is necessary to set the operating voltage of the field electron emission type surge absorbing element 74 relatively low, a method of increasing the degree of vacuum in the envelope 78, a method of reducing the work function of the emitter cone 79,
A method of shortening the distance between the tip portion 79a of the emitter cone and the inner surface of the second substrate member 76 or a method of sharpening the tip portion 79a of the emitter cone is theoretically conceivable.
【００１８】しかしながら、これらの中、エミッタ・コ
ーンの先端部79ａと第２の基板部材76との間の距離を短
縮化させる方法を実現させるには、上記枠部材77の存在
が障害となっていた。すなわち、上記のように枠部材77
は両基板部材75，76と陽極接合されるため、内部に可動
イオンを含んだガラス（パイレックスガラス等）によっ
て構成されており、これをあまり薄く形成すると割れ易
くなるため、製造過程での取扱いを考慮すると１００μ
ｍ以下にはできないという問題があった。このため、両
基板部材75，76間には少なくとも１００μｍの間隙が存
在することとなり、これが電界電子放出型サージ吸収素
子74の動作電圧を低く設定するための一つの限界となっ
ていた。However, among them, in order to realize a method for shortening the distance between the tip 79a of the emitter cone and the second substrate member 76, the existence of the frame member 77 is an obstacle. Was. That is, as described above, the frame member 77
Is made of glass (such as Pyrex glass) that contains mobile ions inside because it is anodically bonded to both substrate members 75 and 76. Considering 100μ
m or less. For this reason, a gap of at least 100 μm exists between the two substrate members 75 and 76, which is one limit for setting the operating voltage of the field emission type surge absorbing element 74 low.
【００１９】この発明は、従来の上記問題に鑑みてなさ
れたものであり、両基板部材の内面間の距離をより狭め
ることで動作電圧を比較的低く設定することが可能な電
界電子放出型サージ吸収素子の製造方法を実現すること
を目的とする。The present invention has been made in view of the above-mentioned conventional problems, and a field electron emission type surge capable of setting an operating voltage relatively low by further reducing the distance between the inner surfaces of both substrate members. An object of the present invention is to realize a method for manufacturing an absorbing element.
【００２０】[0020]
【課題を解決するための手段】上記の目的を達成するた
め、この発明に係るサージ吸収素子の製造方法は、半導
体よりなる第１の基板部材と第２の基板部材とを対向配
置し、両基板部材の対向面周縁を気密封止して外囲器を
形成し、該外囲器内を高真空状態となすと共に、上記第
１の基板部材の対向面及び第２の基板部材の対向面の少
なくとも一方に多数のエミッタ・コーンを形成し、当該
エミッタ・コーンと他方の基板部材の内面あるいはエミ
ッタ・コーンとの間に所定の間隙を形成し、さらに両基
板部材の外面にそれぞれ外部電極を形成してなる電界電
子放出型サージ吸収素子の製造方法において、上記枠部
材として、内部に可動イオンを含む絶縁材よりなり、上
記第１の基板部材の対向面周縁と接する第１の端面と、
上記第２の基板部材の対向面周縁と接する第２の端面と
を備えたものを用い、該枠部材の第１の端面を上記第１
の基板部材の対向面周縁に接触させた状態で、第１の基
板部材の外部電極に直流電源のプラス側を接続させると
共に、上記枠部材の第２の端面に上記直流電源のマイナ
ス側を接続し、所定の温度に加熱しつつ上記直流電源よ
り所定の電圧を印加して、第１の基板部材の対向面周縁
と枠部材の第１の端面とを陽極接合させ、つぎに、枠部
材の第２の端面を研磨して枠部材の高さを調整し、つぎ
に、真空雰囲気中において、当該枠部材の第２の端面に
上記第２の基板部材の対向面周縁を接触させた状態で、
第２の基板部材の外部電極に直流電源のプラス側を接続
させると共に、第１の基板部材の外部電極に上記直流電
源のマイナス側を接続し、所定の温度に加熱しつつ上記
直流電源より所定の電圧を印加して、第２の基板部材の
対向面周縁と枠部材の第２の端面とを陽極接合させるこ
とを特徴としている。In order to achieve the above object, a method of manufacturing a surge absorbing element according to the present invention comprises a first substrate member made of a semiconductor and a second substrate member arranged opposite to each other. A peripheral edge of the opposing surface of the substrate member is hermetically sealed to form an envelope, the inside of the envelope is brought into a high vacuum state, and the opposing surface of the first substrate member and the opposing surface of the second substrate member. A large number of emitter cones are formed on at least one of them, a predetermined gap is formed between the emitter cone and the inner surface or emitter cone of the other substrate member, and external electrodes are respectively provided on the outer surfaces of both substrate members. In the method for manufacturing a field electron emission type surge absorbing element formed, the frame member is made of an insulating material containing movable ions therein, and a first end face which is in contact with a peripheral edge of the facing surface of the first substrate member;
The second substrate member is provided with a second end surface that is in contact with the periphery of the facing surface of the second substrate member, and the first end surface of the frame member is the first end surface.
The positive side of the DC power supply is connected to the external electrode of the first substrate member while being in contact with the peripheral edge of the opposing surface of the substrate member, and the negative side of the DC power supply is connected to the second end surface of the frame member. Then, while heating to a predetermined temperature, a predetermined voltage is applied from the DC power source, and the peripheral edge of the facing surface of the first substrate member and the first end surface of the frame member are anodically bonded. The second end face is polished to adjust the height of the frame member, and then, in a vacuum atmosphere, the second end face of the frame member is brought into contact with the peripheral edge of the facing surface of the second substrate member. ,
The plus side of the DC power supply is connected to the external electrode of the second substrate member, and the minus side of the DC power supply is connected to the external electrode of the first substrate member. Is applied, and the peripheral edge of the opposing surface of the second substrate member and the second end surface of the frame member are anodically bonded.
【００２１】このように枠部材を第１の基板部材に接合
しておき、その後で厚さを調整する工程を設けるように
すれば、第１の基板部材を枠部材の補強部材として利用
することができる。このため、枠部材の高さを１００μ
ｍ以下に研磨加工し易くなり、続く第２の基板部材との
接合工程においても容易に割れたりしなくなる。In this way, if the frame member is joined to the first substrate member and then a step of adjusting the thickness is provided, the first substrate member can be used as a reinforcing member for the frame member. Can be. Therefore, the height of the frame member is set to 100 μm.
m or less, and it is not easily broken even in the subsequent bonding step with the second substrate member.
【００２２】また、この発明に係る他の製造方法は、半
導体よりなる第１の基板部材と第２の基板部材とを対向
配置し、両基板部材の対向面周縁を気密封止して外囲器
を形成し、該外囲器内を高真空状態となすと共に、上記
第１の基板部材の対向面及び第２の基板部材の対向面の
少なくとも一方に多数のエミッタ・コーンを形成し、当
該エミッタ・コーンと他方の基板部材の内面あるいはエ
ミッタ・コーンとの間に所定の間隙を形成し、さらに両
基板部材の外面にそれぞれ外部電極を形成してなる電界
電子放出型サージ吸収素子の製造方法において、上記第
１の基板部材及び第２の基板部材の少なくとも一方の対
向面周縁に枠状酸化膜を形成する工程と、該枠状酸化膜
が形成された基板部材を硫酸過酸化水中に浸す工程と、
当該基板部材を純水中に浸した後、超音波振動を加えて
洗浄する工程と、真空雰囲気中において、当該基板部材
の枠状酸化膜と他方の基板部材の対向面周縁あるいは枠
状酸化膜とを重ね合わせて加熱し、両接触面同士を共有
結合させることを特徴としている。In another manufacturing method according to the present invention, a first substrate member made of a semiconductor and a second substrate member are arranged to face each other, and the peripheral edges of the opposing surfaces of the two substrate members are hermetically sealed and surrounded. Forming a vessel, making the inside of the envelope into a high vacuum state, and forming a large number of emitter cones on at least one of the opposing surface of the first substrate member and the opposing surface of the second substrate member; A method of manufacturing a field electron emission type surge absorbing element comprising: forming a predetermined gap between an emitter cone and the inner surface of the other substrate member or the emitter cone; and forming external electrodes on outer surfaces of both substrate members. Forming a frame-shaped oxide film on the periphery of at least one of the first substrate member and the second substrate member, and immersing the substrate member on which the frame-shaped oxide film is formed in sulfuric acid peroxide water. Process and
After immersing the substrate member in pure water, a step of applying ultrasonic vibrations for cleaning, and in a vacuum atmosphere, a frame-shaped oxide film of the substrate member and a peripheral edge or a frame-shaped oxide film of the opposite surface of the other substrate member Are heated by overlapping, and the two contact surfaces are covalently bonded to each other.
【００２３】この製造方法によれば、枠部材を用いる代
わりに薄型化が可能な枠状酸化膜を形成し、当該酸化膜
を介して両基板の接合を実現できるため、第１の基板部
材と第２の基板部材との間の間隙を極めて小さく設定で
きる。According to this manufacturing method, a frame-shaped oxide film which can be reduced in thickness is formed instead of using the frame member, and the two substrates can be joined via the oxide film. The gap with the second substrate member can be set extremely small.
【００２４】[0024]
【発明の実施の形態】本発明に係る第１の電界電子放出
型サージ吸収素子10は、図１に示すように、第１の基板
部材11と第２の基板部材12とを所定の距離を隔てて対向
配置させ、両基板部材の内面周縁部をスペーサを兼ねた
枠部材13を間に介して気密封止することによって外囲器
14を形成し、該外囲器14内を１０−６〜１０−８Torrの
高真空状態に維持してなる。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS As shown in FIG. 1, a first field emission type surge absorbing element 10 according to the present invention places a first substrate member 11 and a second substrate member 12 at a predetermined distance. The outer peripheral portions of the two substrates are hermetically sealed with a frame member 13 also serving as a spacer interposed therebetween.
14 is formed, and the inside of the envelope 14 is maintained in a high vacuum state of 10 −6 to 10 −8 Torr.
【００２５】上記第１の基板部材11及び第２の基板部材
12の内面には、多数のエミッタ・コーン15が所定の間隔
をおいて略全面に亘って突設されている。図１は断面図
であるため、一列のエミッタ・コーン15のみが表されて
いるが、エミッタ・コーン15は、実際には一定の間隔を
おいて縦横に整列配置されている。上記第１の基板部材
11及び第２の基板部材12は、Ｓｉ中にＰやＡｓ等の不純
物を混入させてなるｎ形半導体によって形成されてい
る。また、エミッタ・コーン15も同様にｎ形半導体より
成り、第１の基板部材11及び第２の基板部材12と一体的
に形成されている。エミッタ・コーン15は先端が尖った
円錐または角錐形状をなしており、両基板部材11，12に
形成されたエミッタ・コーン15の先端部15ａは、所定の
間隙を隔てて他方の基板部材のエミッタ・コーン15や内
面と対向するように位置決めされている。上記エミッタ
・コーン15の高さは約５μｍに、底面の直径は約３〜１
０μｍに、またエミッタ・コーン15間のピッチは約７.
５〜１５μｍに設定されている。The first substrate member 11 and the second substrate member
On the inner surface of 12, a large number of emitter cones 15 are protruded over a substantially entire surface at predetermined intervals. Although FIG. 1 is a cross-sectional view, only one row of emitter cones 15 is shown. However, the emitter cones 15 are actually arranged vertically and horizontally at regular intervals. The first substrate member
11 and the second substrate member 12 are formed of an n-type semiconductor in which impurities such as P and As are mixed in Si. The emitter cone 15 is also made of an n-type semiconductor and is formed integrally with the first substrate member 11 and the second substrate member 12. The emitter cone 15 has a pointed cone or pyramid shape, and the tip 15a of the emitter cone 15 formed on the two substrate members 11, 12 is separated from the emitter cone of the other substrate member by a predetermined gap. -It is positioned so as to face the cone 15 and the inner surface. The height of the emitter cone 15 is about 5 μm, and the diameter of the bottom is about 3-1.
0 μm and the pitch between the emitter cones 15 is about 7.
It is set to 5 to 15 μm.
【００２６】エミッタ・コーン15の表面をも含んだ第１
の基板部材11及び第２の基板部材12の内面には、保護層
22が被覆されている。この保護層22は、Ｗ、Ｍｏ、Ｎ
ｉ、Ｌａ、Ａｌ等よりなる薄膜、あるいは以上の各物質
の中、少なくとも１種類を含んだ炭化物、酸化物、窒化
物、硼化物、無機化合物より構成される。上記第１の基
板部材11の外面には、ＡｌまたはＣｒを蒸着して形成し
た第１の層23ａと、該第１の層23ａの表面にＮｉを蒸着
して形成した第２の層23ｂからなる第１の外部電極23が
形成されている。また、第２の基板部材12の外面にも、
ＡｌまたはＣｒを蒸着して形成した第１の層24ａと、該
第１の層24ａの表面にＮｉを蒸着して形成した第２の層
24ｂからなる第２の外部電極24が形成されている。この
第１の層23ａ，24ａを構成するＡｌまたはＣｒと、第２
の層23ｂ，24ｂを構成するＮｉとは、良好なオーム接触
（ohmic contact）を実現するものとして選定された。
もっとも、上記第１の外部電極23及び第２の外部電極24
は、必ずしも二層構造とする必要はなく、Ｎｉのみを蒸
着して形成してもよい。上記枠部材13の材質としては、
ｎ形半導体と熱膨張係数が近く、内部に可動イオン（Ｎ
ａ＋）を含んだパイレックスガラス等が用いられる。The first including the surface of the emitter cone 15
The inner surfaces of the substrate member 11 and the second substrate member 12 are provided with a protective layer.
22 are coated. This protective layer 22 is made of W, Mo, N
It is composed of a thin film made of i, La, Al, or the like, or a carbide, oxide, nitride, boride, or inorganic compound containing at least one of the above substances. On the outer surface of the first substrate member 11, a first layer 23a formed by evaporating Al or Cr and a second layer 23b formed by evaporating Ni on the surface of the first layer 23a are formed. A first external electrode 23 is formed. Also, on the outer surface of the second substrate member 12,
A first layer 24a formed by evaporating Al or Cr, and a second layer formed by evaporating Ni on the surface of the first layer 24a.
A second external electrode 24 consisting of 24b is formed. Al or Cr constituting the first layers 23a and 24a,
The Ni constituting the layers 23b and 24b is selected to realize a good ohmic contact.
However, the first external electrode 23 and the second external electrode 24
Need not necessarily have a two-layer structure, and may be formed by evaporating only Ni. As the material of the frame member 13,
The thermal expansion coefficient is close to that of an n-type semiconductor, and mobile ions (N
Pyrex glass containing a + ) is used.
【００２７】上記第１の外部電極23及び第２の外部電極
24には、それぞれ第１の外部端子25及び第２の外部端子
26が接続される。そして、各端子25，26を線Ｌ1，Ｌ2あ
るいはＧＮＤに接続することにより、第１の電界電子放
出型サージ吸収素子10は、図２２に示したサージ吸収素
子72と同様、線Ｌ1，Ｌ2間あるいは線Ｌ1，Ｌ2−ＧＮＤ
間に挿入接続されることとなる。しかして、上記線Ｌ
1，Ｌ2間あるいは線Ｌ1，Ｌ2−ＧＮＤ間に定格以上のサ
ージ電圧が印加されると、エミッタ・コーン15の先端部
15ａに強い電界集中が生じ、電子が表面のポテンシャル
障壁を通過して真空中に放出される。このいわゆる電界
電子放出現象によって生じた電子は、対向する基板部材
の内面で捕捉されるため、第１の基板部材11と第２の基
板部材12との間に電流が流れる先駆放電が生成され、こ
の先駆放電が真空火花放電に移行することでサージの吸
収が実現されるのである。この第１の電界電子放出型サ
ージ吸収素子10の場合、第１の基板部材11及び第２の基
板部材12がそれぞれエミッタ・コーン15を備えており、
双方向に電子放出が可能であるため、回路に接続する際
にその極性を考慮する必要がない。The first external electrode 23 and the second external electrode
24 has a first external terminal 25 and a second external terminal, respectively.
26 is connected. Then, by connecting the terminals 25, 26 to the lines L1, L2 or GND, the first field emission type surge absorbing element 10 can be connected between the lines L1, L2 in the same manner as the surge absorbing element 72 shown in FIG. Or line L1, L2-GND
It will be inserted and connected between them. Then, the line L
When a surge voltage higher than the rated voltage is applied between the terminals 1 and 2 or between the lines L1 and L2 and GND, the tip of the emitter cone 15
A strong electric field concentration occurs at 15a, and electrons are emitted into a vacuum through a potential barrier on the surface. Electrons generated by this so-called field electron emission phenomenon are captured on the inner surface of the opposing substrate member, so that a precursor discharge in which a current flows between the first substrate member 11 and the second substrate member 12 is generated, The transition of the precursor discharge to the vacuum spark discharge realizes the absorption of the surge. In the case of the first field electron emission type surge absorbing element 10, the first substrate member 11 and the second substrate member 12 each have an emitter cone 15,
Since electrons can be emitted in both directions, there is no need to consider the polarity when connecting to a circuit.
【００２８】なお、図示の便宜上、図１においてはエミ
ッタ・コーン15の大きさを強調して描かれているが、実
際には上記のようにエミッタ・コーン15はμｍ単位の大
きさであるのに対し、第１の基板部材11及び第２の基板
部材12はmm単位（例えば２〜６mm角）の大きさであり、
エミッタ・コーン15も数万〜数十万個以上形成されてい
る。因みに、第１の電界電子放出型サージ吸収素子10の
全体の大きさは、６mm角で厚さが０.６mm程度となる。Although the size of the emitter cone 15 is emphasized in FIG. 1 for convenience of illustration, the emitter cone 15 is actually in a size of μm as described above. On the other hand, the first substrate member 11 and the second substrate member 12 have a size of mm unit (for example, 2 to 6 mm square),
Also, tens of thousands to hundreds of thousands of emitter cones 15 are formed. Incidentally, the overall size of the first field emission type surge absorbing element 10 is about 6 mm square and about 0.6 mm thick.
【００２９】つぎに、図２〜図８に基づき、エミッタ・
コーン15の形成方法について説明する。まず、第１の基
板部材11及び第２の基板部材12の素になる抵抗率が０.
０１〜５（Ω・cm）のｎ形Ｓｉ基板27を用意し、その表
面を酸化させて厚さ約１５０〜３０００オングストロー
ムのＳｉＯ２薄膜28を形成する（図２）。つぎに、上記
ＳｉＯ２薄膜28の表面全域に、フォトレジスト29を均一
に塗布する（図３）。また、フォトレジスト29の上方に
遮光塗料30を円形に塗布したフォトマスク31を被せ、紫
外線ＵＶによる露光処理を施す。この結果、遮光塗料30
によって紫外線ＵＶが遮られる部分を除き、フォトレジ
スト29の表面が感光する。つぎに、所定の薬品を用いて
フォトレジスト29の中で感光された部分を除去し、Ｓｉ
Ｏ２薄膜28の表面に円形のフォトレジスト・マスク32を
形成する（図４）。Next, based on FIG. 2 to FIG.
A method for forming the cone 15 will be described. First, the first substrate member 11 and the second substrate member 12 have a resistivity of 0.1.
An n-type Si substrate 27 of 01 to 5 (Ω · cm) is prepared and its surface is oxidized to form a SiO 2 thin film 28 having a thickness of about 150 to 3000 Å (FIG. 2). Next, a photoresist 29 is uniformly applied to the entire surface of the SiO 2 thin film 28 (FIG. 3). Further, a photomask 31 in which a light-shielding paint 30 is applied in a circular shape is placed over the photoresist 29, and an exposure process using ultraviolet rays UV is performed. As a result, the light-shielding paint 30
The surface of the photoresist 29 is exposed except for the part where the ultraviolet rays UV are blocked. Next, the exposed portion of the photoresist 29 is removed using a predetermined chemical, and Si is removed.
On the surface of the O 2 thin film 28 to form a circular photoresist mask 32 (FIG. 4).
【００３０】つぎに、ＢＨＦ（Buffered 弗酸を用いた
ウエットエッチング）により、ＳｉＯ２薄膜28の中でフ
ォトレジスト・マスク32で覆われていない部分を除去し
た後に、フォトレジスト・マスク32を剥離することによ
り、円形のドット状酸化膜マスク33を形成する（図
５）。なお、図においては１個の酸化膜マスク33のみが
表されているが、この酸化膜マスク33はエミッタ・コー
ン15の数に対応して形成されるものであり、実際には15
μｍ間隔でマトリクス状に多数形成されるものである。
また、酸化膜マスク33の直径は約10μｍに設定されてい
る。Next, the portions of the SiO 2 thin film 28 that are not covered with the photoresist mask 32 are removed by BHF (wet etching using buffered hydrofluoric acid), and then the photoresist mask 32 is removed. Thus, a circular dot-shaped oxide film mask 33 is formed (FIG. 5). Although only one oxide film mask 33 is shown in the figure, this oxide film mask 33 is formed corresponding to the number of
Many are formed in a matrix at intervals of μm.
The diameter of the oxide film mask 33 is set to about 10 μm.
【００３１】つぎに、Ｓｉ基板27表面にＲＩＥ（リアク
ティブ・イオン・エッチング）を施して、酸化膜マスク
33で覆われていない部分を侵食させる（図６）。ＲＩＥ
は、図示しない真空チャンバ内に設置した２枚の平行電
極間にＳｉ基板27を配置させた上で、所定のガス媒体を
真空チャンバ内に充填し、両電極間に約150Ｗの電力を
加えて高周波プラズマ放電を発生させ、このプラズマに
よる化学作用とイオン衝撃による物理作用を利用してエ
ッチングを行う方法である。この場合、ガス媒体として
反応性のＯ２とＳＦ６を用いるのが望ましく、両者の体
積比は、２.２×１０−１Torrの圧力下で、例えばＳＦ
６：Ｏ２＝９：１に設定される。ＲＩＥは異方性に優れ
ているため、酸化膜マスク33の裏面側にもエッチングが
進行してしまう、いわゆるアンダーカットの程度が比較
的低くなり、この結果、四角錐状の突出部34が形成され
る。このＲＩＥは、上記の条件下において例えば１５分
間実施される。Next, RIE (reactive ion etching) is performed on the surface of the Si substrate 27 to form an oxide film mask.
The part not covered with 33 is eroded (FIG. 6). RIE
Is a method in which an Si substrate 27 is arranged between two parallel electrodes installed in a vacuum chamber (not shown), a predetermined gas medium is filled in the vacuum chamber, and an electric power of about 150 W is applied between the two electrodes. In this method, high-frequency plasma discharge is generated, and etching is performed using a chemical action of the plasma and a physical action of ion bombardment. In this case, it is desirable to use reactive O 2 and SF 6 as a gas medium, and the volume ratio of both is, for example, SF 2 under a pressure of 2.2 × 10 −1 Torr.
6 : O 2 = 9: 1. Since RIE is excellent in anisotropy, the degree of so-called undercut, in which etching proceeds on the back side of the oxide film mask 33, is relatively low. As a result, a quadrangular pyramid-shaped protrusion 34 is formed. Is done. This RIE is performed, for example, for 15 minutes under the above conditions.
【００３２】つぎに、上記Ｓｉ基板27の表面に異方性ウ
ェットエッチングを施し、上記突出部34の表面を侵食さ
せて先端部を尖鋭化させる（図７）。一般にウェットエ
ッチングというのは、エッチング対象物を所定の化学薬
品に浸し、その化学反応を利用してエッチングを行うも
のであり、等方性が強い（すなわち、エッチング方向を
制御し難く、オーバーエッチングが生じ易い）という特
徴を備えている。これに対し、異方性ウェットエッチン
グは、エッチング液の選定に工夫を凝らすことにより、
ウェットエッチングながらも等方性を弱めてエッチング
方向を制御し易くしたものである。ここでは、異方性ウ
ェットエッチング用のエッチング液として、ＫＯＨとＨ
２Ｏとの混合水溶液を用いており、その溶液温度は摂氏
５０度程度に設定される。また、両者の混合比率として
は、例えば１００mlのＨ２Ｏに対して５０ｇのＫＯＨを
混合することが挙げられる。Next, the surface of the Si substrate 27 is subjected to anisotropic wet etching to erode the surface of the protruding portion 34 to sharpen the tip (FIG. 7). In general, wet etching is a method in which an object to be etched is immersed in a predetermined chemical and etching is performed by using the chemical reaction, and is highly isotropic (that is, it is difficult to control the etching direction, and overetching is difficult). Easily occur). In contrast, anisotropic wet etching is devised by carefully selecting the etchant,
This is to make it easier to control the etching direction by weakening the isotropy while performing wet etching. Here, KOH and H are used as an etchant for anisotropic wet etching.
A mixed aqueous solution with 2 O is used, and the solution temperature is set to about 50 degrees Celsius. As a mixing ratio of both, for example, 50 g of KOH is mixed with 100 ml of H 2 O.
【００３３】上記の異方性ウェットエッチングが進行
し、ある程度のアンダーカット35が生じて突出部34の先
端が極めて尖鋭化すると、酸化膜マスク33は安定性を失
って落下する（図８）。この段階に至れば、突出部34の
先端の角度は25〜30度まで尖鋭化され、エミッタ・コー
ン15として完成しているため、上記異方性ウェットエッ
チングが停止される。ここに至るまでの異方性ウェット
エッチングの所要時間としては、約８分程度が見込まれ
る。When the above-described anisotropic wet etching proceeds and a certain degree of undercut 35 occurs, and the tip of the projection 34 becomes extremely sharp, the oxide film mask 33 loses stability and drops (FIG. 8). At this stage, the angle of the tip of the protrusion 34 is sharpened to 25 to 30 degrees, and the anisotropic wet etching is stopped because the emitter cone 15 is completed. The time required for the anisotropic wet etching up to here is expected to be about 8 minutes.
【００３４】以上のようにしてエミッタ・コーン15を形
成すれば、その先端部15ａを極めて尖鋭に形成すること
ができ、この第１の電界電子放出型サージ吸収素子10の
動作電圧を、使用目的に応じて比較的低い値に設定する
ことが可能となる。When the emitter cone 15 is formed as described above, the tip 15a can be formed extremely sharp, and the operating voltage of the first field-emission type surge absorbing element 10 can be reduced. Can be set to a relatively low value in accordance with.
【００３５】上記のようにして、表面にエミッタ・コー
ン15が形成された第１の基板部材11及び第２の基板部材
12の外面には、それぞれ第１の外部電極23及び第２の外
部電極24が形成される。また、両基板部材11，12の内面
やエミッタ・コーン15の表面には、保護膜22が形成され
る。つぎに、図９に示すように、第１の基板部材11の表
面に枠部材13を重ね合わせる。この枠部材13は、長方形
状のガラス板の真ん中部分を長方形状に大きく切り欠い
た形状を備えており、第１の基板部材11の対向面周縁40
にその第１の端面（下面）13ａが重ねられる。The first substrate member 11 and the second substrate member each having the emitter cone 15 formed on the surface as described above.
A first external electrode 23 and a second external electrode 24 are formed on the outer surface of the substrate 12, respectively. Further, a protective film 22 is formed on the inner surfaces of the two substrate members 11 and 12 and the surface of the emitter cone 15. Next, as shown in FIG. 9, the frame member 13 is overlaid on the surface of the first substrate member 11. The frame member 13 has a shape in which a middle portion of a rectangular glass plate is largely cut out in a rectangular shape.
The first end face (lower face) 13a is superposed on the first end face.
【００３６】つぎに、図１０に示すように、ホットプレ
ート42上に第１の基板部材11を、第１の外部電極23を下
にして載置する。そして、枠部材13の第２の端面13ｂに
は、電極板43が圧着される。また、第１の基板部材11の
第１の外部電極23には、ホットプレート42を経由して直
流電源44のプラス側が接続されると共に、上記電極板43
には直流電源44のマイナス側が接続される。つぎに、上
記ホットプレート42によって、第１の基板部材11及び枠
部材13が摂氏２００〜６００度に加熱された状態で、上
記直流電源44より５０〜１０００Ｖの直流電圧が印加さ
れる。Next, as shown in FIG. 10, the first substrate member 11 is placed on the hot plate 42 with the first external electrode 23 facing down. Then, the electrode plate 43 is crimped to the second end face 13b of the frame member 13. The positive side of a DC power supply 44 is connected to the first external electrode 23 of the first substrate member 11 via a hot plate 42, and the electrode plate 43
Is connected to the negative side of the DC power supply 44. Next, a DC voltage of 50 to 1000 V is applied from the DC power supply 44 while the first substrate member 11 and the frame member 13 are heated to 200 to 600 degrees Celsius by the hot plate 42.
【００３７】この結果、図１１に示すように、一定時間
経過後には枠部材13中の陽イオン45がマイナス側（すな
わち枠部材13の第２の端面13ｂ側）に移動すると共に、
第１の基板部材14の対向面周縁40近傍にマイナスの電荷
が集中して空間電荷層46が現れ、大きな吸引力を伴う化
学結合が生じて陽極接合が実現される。As a result, as shown in FIG. 11, after a certain period of time, the cations 45 in the frame member 13 move to the minus side (ie, the second end surface 13b side of the frame member 13).
Negative charges are concentrated near the peripheral edge 40 of the first substrate member 14 to form the space charge layer 46, and a chemical bond with a large attractive force is generated to realize anodic bonding.
【００３８】以上のようにして、第１の基板部材11の対
向面周縁40と枠部材13の第１の端面13ａとの強固な接合
が完了した後、図１２に示すように、枠部材13の第２の
端面13ｂを砥石車47で研磨し、枠部材13を必要な高さ
（厚さ）に調整する。第１の基板部材11の内面及びエミ
ッタ・コーン15の表面には保護膜22が形成されているた
め、この研磨工程によって損なわれることはない。As described above, after the solid bonding between the peripheral edge 40 of the first substrate member 11 and the first end surface 13a of the frame member 13 is completed, as shown in FIG. The second end face 13b is polished by a grinding wheel 47 to adjust the frame member 13 to a required height (thickness). Since the protective film 22 is formed on the inner surface of the first substrate member 11 and the surface of the emitter cone 15, the polishing film is not damaged.
【００３９】図１３に示すように、今度は真空雰囲気中
において、ホットプレート42上に第２の基板部材12を第
２の外部電極24を下にして載置すると共に、枠部材13の
第２の端面13ｂを第２の基板部材12の対向面周縁48に当
接させる。また、上記第２の基板部材12の第２の外部電
極24には、ホットプレート42経由して直流電源44のプラ
ス側が接続されると共に、第１の基板部材11の第１の外
部電極23には電極板43を介して直流電源44のマイナス側
が接続される。そして、上記ホットプレート42によっ
て、第２の基板部材12及び枠部材13が摂氏２００〜６０
０度に加熱された状態で、上記直流電源44より５０〜１
０００Ｖの直流電圧が印加される。この結果、上記と同
様のメカニズムによって、第２の基板部材12の対向面周
縁48と枠部材13の第２の端面13ｂとの強固な陽極接合が
実現され、高い気密性を備えた外囲器14が完成する。As shown in FIG. 13, this time, in a vacuum atmosphere, the second substrate member 12 is placed on the hot plate 42 with the second external electrode 24 facing down, and the second Is brought into contact with the peripheral edge 48 of the facing surface of the second substrate member 12. Further, the plus side of the DC power supply 44 is connected to the second external electrode 24 of the second substrate member 12 via the hot plate 42, and the second external electrode 24 of the first substrate member 11 is connected to the first external electrode 23 of the first substrate member 11. Is connected to the negative side of the DC power supply 44 via the electrode plate 43. Then, the second substrate member 12 and the frame member 13 are heated by the hot plate 42 to 200 to 60 degrees Celsius.
In the state of being heated to 0 degrees, 50 to 1
A DC voltage of 000 V is applied. As a result, the strong anodic bonding between the peripheral edge 48 of the second substrate member 12 and the second end surface 13b of the frame member 13 is realized by the same mechanism as described above, and the envelope having high airtightness is realized. 14 is completed.
【００４０】このように、枠部材13を第１の基板部材11
に陽極接合した後で、研磨によって枠部材13の高さを調
整する工程を設けることにより、枠部材13の高さを１０
０μｍ以下に形成することができる。一旦第１の基板部
材11に接合させた後で研磨工程を行うものであるため、
例え枠部材13の厚さが１００μｍ以下であっても容易に
割れたりすることがなく、取扱上の不都合は生じない。As described above, the frame member 13 is connected to the first substrate member 11.
After the anodic bonding of the frame member 13, a step of adjusting the height of the frame member 13 by polishing is
It can be formed to a thickness of 0 μm or less. Since the polishing step is performed after being once bonded to the first substrate member 11,
Even if the thickness of the frame member 13 is 100 μm or less, the frame member 13 is not easily broken, and there is no inconvenience in handling.
【００４１】図１４は、この発明に係る第２の電界電子
放出型サージ吸収素子50を示すものである。この第２の
電界電子放出型サージ吸収素子50の場合、ｎ型半導体よ
りなる第１の基板部材11及び第２の基板部材12の対向面
に、それぞれ一定の深さの凹部51が形成されると共に、
この凹部51の底面に多数のエミッタ・コーン15が一体形
成されている。また、第１の基板部材11の対向面周縁40
と第２の基板部材12の対向面周縁48との間を、枠部材13
を介して接合する代わりに、枠状酸化膜52，52を間に介
して接合している点に特徴を備えている。なお、それ以
外の構成は、第１の電界電子放出型サージ吸収素子10と
実質的に等しい。FIG. 14 shows a second field emission type surge absorbing element 50 according to the present invention. In the case of the second field emission type surge absorbing element 50, concave portions 51 having a constant depth are formed on the opposing surfaces of the first substrate member 11 and the second substrate member 12 made of an n-type semiconductor. Along with
A large number of emitter cones 15 are integrally formed on the bottom surface of the concave portion 51. Further, the peripheral edge 40 of the facing surface of the first substrate member 11
Between the outer peripheral edge 48 of the second substrate member 12 and the frame member 13.
This is characterized in that, instead of joining via the frame, the frame-like oxide films 52, 52 are joined via an intervening portion. Other configurations are substantially the same as those of the first field emission type surge absorbing element 10.
【００４２】図１５〜図２１に基づき、第２の電界電子
放出型サージ吸収素子50の製造方法を説明する。まず、
第１の基板部材11及び第２の基板部材12の素となる抵抗
率が０.０１〜５（Ω・cm）のｎ形Ｓｉ基板55を、酸化
雰囲気中で酸化させて表面に約１５０〜３０００オング
ストロームの厚さのＳｉＯ2薄膜56を形成した後、この
ＳｉＯ2薄膜56の表面全域に、フォトレジスト57をスピ
ンナを用いて均一に塗布する（図１５）。つぎに、フォ
トレジスト57の上方に、枠状遮光性パターン58及び多数
のドット状遮光パターン59を備えたフォトマスク60を被
せ、紫外線ＵＶによる露光処理を施す（図１６）。この
結果、遮光パターン58，59によって紫外線が遮られた部
分を除き、フォトレジスト57の表面が感光する。つぎ
に、所定の薬品を用いてフォトレジスト57の中で感光さ
れた部分を除去し、ＳｉＯ2薄膜56の表面に枠状フォト
レジスト・マスク61及びドット状フォトレジスト・マス
ク62を形成する（図１７） 。つぎに、ＢＨＦにより、
Ｓｉ Ｏ2薄膜56の中で枠状フォトレジスト・マスク61及
びドット状フォトレジスト・マスク62で覆われていない
部分を除去した後に、両フォトレジスト・マスク61，62
を剥離することにより、Ｓｉ基板55の表面周縁に沿う枠
状酸化膜52と、多数のドット状酸化膜64が形成される
（図１８）。A method of manufacturing the second field emission type surge absorbing element 50 will be described with reference to FIGS. First,
An n-type Si substrate 55 having a resistivity of 0.01 to 5 (Ω · cm), which is an element of the first substrate member 11 and the second substrate member 12, is oxidized in an oxidizing atmosphere to have a surface of about 150 to After forming the SiO 2 thin film 56 having a thickness of 3000 Å, a photoresist 57 is uniformly applied to the entire surface of the SiO 2 thin film 56 using a spinner (FIG. 15). Next, a photomask 60 provided with a frame-shaped light-shielding pattern 58 and a number of dot-shaped light-shielding patterns 59 is placed over the photoresist 57, and an exposure process using ultraviolet rays UV is performed (FIG. 16). As a result, the surface of the photoresist 57 is exposed except for the portion where the ultraviolet rays are blocked by the light shielding patterns 58 and 59. Next, the exposed portion of the photoresist 57 is removed using a predetermined chemical, and a frame-shaped photoresist mask 61 and a dot-shaped photoresist mask 62 are formed on the surface of the SiO 2 thin film 56 (FIG. 17). Next, by BHF,
After removing portions of the SiO 2 thin film 56 that are not covered with the frame-shaped photoresist mask 61 and the dot-shaped photoresist mask 62, the photoresist masks 61 and 62 are removed.
By stripping, a frame-shaped oxide film 52 along the peripheral edge of the Si substrate 55 and a number of dot-shaped oxide films 64 are formed (FIG. 18).
【００４３】つぎに、Ｓｉ基板55表面にＲＩＥ及び異方
性ウェットエッチングを施して、酸化膜52，64で覆われ
ていない部分を必要な深さ分侵食させ、凹部51及びエミ
ッタ・コーン15を形成する（図示省略）。この際、エミ
ッタ・コーン15の尖鋭化により、ドット状酸化膜64はバ
ランスを失って自然に落下するが（図８参照）、枠状酸
化膜52はそのまま残される。つぎに、上記凹部51及びエ
ミッタ・コーン15の表面に、保護膜22が形成される。Next, RIE and anisotropic wet etching are performed on the surface of the Si substrate 55 to erode portions not covered by the oxide films 52 and 64 to a required depth, thereby forming the concave portions 51 and the emitter cones 15. (Not shown). At this time, due to the sharpening of the emitter cone 15, the dot-shaped oxide film 64 loses balance and falls naturally (see FIG. 8), but the frame-shaped oxide film 52 is left as it is. Next, a protective film 22 is formed on the surface of the concave portion 51 and the emitter cone 15.
【００４４】このようにして、対向面周縁に枠状酸化膜
52が残されると共に、凹部51、多数のエミッタ・コーン
15、及び保護膜22が形成された第１の基板部材11（第２
の基板部材12）を、図１９に示すように、硫酸と過酸化
水の混合溶液を満たした第１の槽65内に浸し、図示しな
いヒータ等によって加熱し、５分間ほど煮沸させる。こ
の硫酸過酸化水の濃度は、５〜20％に設定されている。
この結果、枠状酸化膜52の表面が反応し、所定の粗面が
形成される。なお、エミッタ・コーン15及び凹部51の表
面に形成された保護膜22はこの硫酸過酸化水に反応しな
いため、粗面化はされない。Thus, the frame-shaped oxide film is formed on the peripheral edge of the facing surface.
52 remains, recess 51, many emitter cones
15 and a first substrate member 11 (second
As shown in FIG. 19, the substrate member 12) is immersed in a first tank 65 filled with a mixed solution of sulfuric acid and peroxide water, heated by a heater (not shown), and boiled for about 5 minutes. The concentration of the sulfuric acid peroxide water is set to 5 to 20%.
As a result, the surface of the frame-shaped oxide film 52 reacts to form a predetermined rough surface. Note that the protective film 22 formed on the surfaces of the emitter cone 15 and the concave portion 51 does not react with the sulfuric acid-peroxide solution, and is not roughened.
【００４５】つぎに、この第１の基板部材11（第２の基
板部材12）を第１の槽65から取り出し、図２０に示すよ
うに、第２の槽66内に移す。この第２の槽66内には、純
水が充填されている。また、この第２の槽66の底面裏側
には、圧電素子よりなる超音波発振部材67が密着配置さ
れている。この超音波発振部材67を30秒〜60秒駆動させ
ると、第１の基板部材11（第２の基板部材12）の表面が
洗浄されると共に、上記枠状酸化膜52の表面が親水性に
なる。Next, the first substrate member 11 (second substrate member 12) is taken out of the first tank 65 and transferred into the second tank 66 as shown in FIG. The second tank 66 is filled with pure water. On the back side of the bottom surface of the second tank 66, an ultrasonic oscillation member 67 made of a piezoelectric element is arranged in close contact. When the ultrasonic oscillation member 67 is driven for 30 seconds to 60 seconds, the surface of the first substrate member 11 (second substrate member 12) is cleaned, and the surface of the frame-shaped oxide film 52 becomes hydrophilic. Become.
【００４６】つぎに、図２１に示すように、真空チャン
バ68内において、第１の基板部材11を基台69上に載置さ
せると共に、第２の基板部材12を対向配置させ、それぞ
れの対向面周縁に残された枠状酸化膜52，52同士を接触
させる。この後、ヒータ70をＯＮして摂氏１０００〜１
４００度で加熱する。この結果、両基板部材11，12の枠
状酸化膜52，52同士が共有結合し、以て気密に封止され
た外囲器14が形成される。Next, as shown in FIG. 21, in the vacuum chamber 68, the first substrate member 11 is placed on the base 69, and the second substrate member 12 is arranged to face each other. The frame-shaped oxide films 52 left on the peripheral edge of the surface are brought into contact with each other. After that, the heater 70 is turned on to set the temperature from 1000 to
Heat at 400 degrees. As a result, the frame-shaped oxide films 52 of the two substrate members 11 and 12 are covalently bonded to each other, thereby forming the envelope 14 hermetically sealed.
【００４７】この第２の電界電子放出型サージ吸収素子
50の製造方法によれば、両基板部材11，12の接合におい
て枠部材を用いる必要がなく、両基板部材の対向面周縁
に形成された枠状酸化膜52，52を介して気密に接合でき
るため、エミッタ・コーン15の先端間の距離をより狭め
ることが可能となり、その分動作電圧を低く設定するこ
とが可能となる。なお、上記のように洗浄工程を経て枠
状酸化膜52の表面を親水性にしておくことにより、表面
の濡れ性が良好となり、上記共有結合が容易となる。This second field electron emission type surge absorbing element
According to the manufacturing method of 50, it is not necessary to use a frame member in joining the two substrate members 11 and 12, and the members can be air-tightly joined via the frame-shaped oxide films 52 formed on the peripheral edges of the opposing surfaces of the two substrate members. Therefore, the distance between the tips of the emitter cones 15 can be further reduced, and the operating voltage can be set lower accordingly. By making the surface of the frame-shaped oxide film 52 hydrophilic through the washing step as described above, the wettability of the surface is improved and the covalent bond is facilitated.
【００４８】上記においては、第１の基板部材11及び第
２の基板部材12の対向面周縁にそれぞれ枠状酸化膜52，
52を形成した例を示したが、ＳｉＯ２−Ｓｉ間において
も共有結合は可能であるため、何れか一方の基板部材に
枠状酸化膜52を形成しておけば足りる。In the above, the frame-shaped oxide films 52, 52 are formed on the peripheral edges of the opposing surfaces of the first substrate member 11 and the second substrate member 12, respectively.
Although an example in which 52 is formed has been shown, since a covalent bond can be formed between SiO 2 and Si, it is sufficient to form the frame-shaped oxide film 52 on one of the substrate members.
【００４９】上記第１の電界電子放出型サージ吸収素子
10及び第２の電界電子放出型サージ吸収素子50は、共に
両基板部材11，12の対向面にエミッタ・コーン15が形成
されたタイプのものであるが、この発明はこの種の電界
電子放出型サージ吸収素子に限定されるものではない。
すなわち、従来技術で説明したような、一方の基板部材
の対向面に形成されたエミッタ・コーンが他方の基板部
材の内面と対向するように構成された電界電子放出型サ
ージ吸収素子にも応用できる。また、エミッタ・コーン
に関しても、上記のようにシリコン製の基板部材と一体
形成する場合に限られず、ダイヤモンド結晶によってエ
ミッタ・コーンを形成するタイプの電界電子放出型サー
ジ吸収素子にも応用可能である。The first field emission type surge absorbing element
The 10 and the second field emission type surge absorbing element 50 are both of the type in which the emitter cone 15 is formed on the opposing surface of both substrate members 11 and 12. It is not limited to the type surge absorbing element.
That is, as described in the prior art, the present invention can also be applied to a field emission type surge absorbing element in which the emitter cone formed on the facing surface of one substrate member faces the inner surface of the other substrate member. . Further, the emitter cone is not limited to the case where the emitter cone is integrally formed with the silicon substrate member as described above, and can be applied to a field electron emission type surge absorbing element of a type in which the emitter cone is formed by a diamond crystal. .
【００５０】[0050]
【発明の効果】この発明に係る電界電子放出型サージ吸
収素子の製造方法にあっては、上記のように第１の基板
部材及び第２の基板部材間の間隔を従来よりも狭く設定
することが容易であり、その分動作電圧を低く設定する
ことができる。According to the method of manufacturing the field emission type surge absorbing element of the present invention, the distance between the first substrate member and the second substrate member is set to be narrower than before. And the operating voltage can be set lower accordingly.
【図１】この発明に係る第１の電界電子放出型サージ吸
収素子を示す断面図である。FIG. 1 is a sectional view showing a first field emission type surge absorbing element according to the present invention.
【図２】エミッタ・コーンの形成過程を示す部分断面図
である。FIG. 2 is a partial cross-sectional view showing a process of forming an emitter cone.
【図３】エミッタ・コーンの形成過程を示す部分断面図
である。FIG. 3 is a partial cross-sectional view showing a process of forming an emitter cone.
【図４】エミッタ・コーンの形成過程を示す部分断面図
である。FIG. 4 is a partial cross-sectional view showing a process of forming an emitter cone.
【図５】エミッタ・コーンの形成過程を示す部分断面図
である。FIG. 5 is a partial sectional view showing a process of forming an emitter cone.
【図６】エミッタ・コーンの形成過程を示す部分断面図
である。FIG. 6 is a partial cross-sectional view showing a process of forming an emitter cone.
【図７】エミッタ・コーンの形成過程を示す部分断面図
である。FIG. 7 is a partial cross-sectional view showing a process of forming an emitter cone.
【図８】エミッタ・コーンの形成過程を示す部分断面図
である。FIG. 8 is a partial cross-sectional view showing a process of forming an emitter cone.
【図９】第１の基板部材と枠部材との接合過程を示す斜
視図である。FIG. 9 is a perspective view showing a joining process of the first substrate member and the frame member.
【図１０】第１の基板部材と枠部材との接合過程を示す
説明図である。FIG. 10 is an explanatory diagram showing a joining process between the first substrate member and the frame member.
【図１１】第１の基板部材と枠部材との接合原理を示す
概念図である。FIG. 11 is a conceptual diagram showing the principle of joining the first substrate member and the frame member.
【図１２】枠部材の研磨工程を示す説明図である。FIG. 12 is an explanatory view showing a polishing step of the frame member.
【図１３】第２の基板部材と枠部材との接合過程を示す
説明図である。FIG. 13 is an explanatory diagram showing a joining process between a second substrate member and a frame member.
【図１４】この発明に係る第２の電界電子放出型サージ
吸収素子を示す断面図である。FIG. 14 is a sectional view showing a second field-emission-type surge absorbing element according to the present invention.
【図１５】エミッタ・コーン及び凹部の形成過程を示す
部分断面図である。FIG. 15 is a partial sectional view showing a process of forming an emitter cone and a concave portion.
【図１６】エミッタ・コーン及び凹部の形成過程を示す
部分断面図である。FIG. 16 is a partial cross-sectional view showing a process of forming an emitter cone and a concave portion.
【図１７】エミッタ・コーン及び凹部の形成過程を示す
部分断面図である。FIG. 17 is a partial cross-sectional view showing a process of forming an emitter cone and a concave portion.
【図１８】エミッタ・コーン及び凹部の形成過程を示す
部分断面図である。FIG. 18 is a partial cross-sectional view showing a process of forming an emitter cone and a concave portion.
【図１９】基板部材を第１の槽内に浸した状態を示す説
明図である。FIG. 19 is an explanatory diagram showing a state where a substrate member is immersed in a first tank.
【図２０】基板部材を第２の槽内に浸した状態を示す説
明図である。FIG. 20 is an explanatory diagram showing a state where a substrate member is immersed in a second tank.
【図２１】第１の基板部材、枠部材、第２の基板部材の
接合過程を示す説明図である。FIG. 21 is an explanatory diagram showing a joining process of a first substrate member, a frame member, and a second substrate member.
【図２２】サージ吸収素子一般の使用例を示す回路図で
ある。FIG. 22 is a circuit diagram showing a general use example of a surge absorbing element.
【図２３】従来の電界電子放出型サージ吸収素子を示す
断面図である。FIG. 23 is a sectional view showing a conventional field emission type surge absorbing element.
【図２４】電界電子放出形サージ吸収素子一般のサージ
吸収特性を示す波形図である。FIG. 24 is a waveform chart showing surge absorption characteristics of a general field emission type surge absorbing element.
【図２５】従来における基板部材と枠部材との接合過程
を示す説明図である。FIG. 25 is an explanatory diagram showing a conventional joining process between a substrate member and a frame member.
【図２６】従来における基板部材と枠部材との接合過程
を示す説明図である。FIG. 26 is an explanatory view showing a conventional joining process between a substrate member and a frame member.
【図２７】従来における基板部材と枠部材との接合過程
を示す説明図である。FIG. 27 is an explanatory diagram showing a conventional joining process between a substrate member and a frame member.
10 第１の電界電子放出型サージ吸収素子 11 第１の基板部材 12 第２の基板部材 13 枠部材 13ａ 枠部材の第１の端面 13ｂ 枠部材の第２の端面 14 外囲器 15 エミッタ・コーン 15ａ エミッタ・コーンの先端部 23 第１の外部電極 24 第２の外部電極 40 第１の基板部材の対向面周縁 42 ホットプレート 44 直流電源 48 第２の基板部材の対向面周縁 50 第２の電界電子放出型サージ吸収素子 52 枠状酸化膜 65 第１の槽 66 第２の槽 67 超音波発振部材 68 真空チャンバ 70 ヒータ 10 first field emission type surge absorbing element 11 first substrate member 12 second substrate member 13 frame member 13a first end face 13b of frame member second end face of frame member 14 envelope 15 emitter cone 15a Tip end of emitter cone 23 First external electrode 24 Second external electrode 40 Peripheral edge of first substrate member facing surface 42 Hot plate 44 DC power supply 48 Peripheral edge of second substrate member facing surface 50 Second electric field Electron emission type surge absorbing element 52 Frame-shaped oxide film 65 First tank 66 Second tank 67 Ultrasonic oscillation member 68 Vacuum chamber 70 Heater
───────────────────────────────────────────────────── フロントページの続き (72)発明者 丸山 光晴 長野県岡谷市天竜町３−20−32 岡谷電機 産業株式会社長野製作所内 (72)発明者 三沢 雅芳 長野県伊那市大字手良中坪449 (72)発明者 米久保 荘 長野県塩尻市大字片丘4691 Ｆターム(参考） 5C012 AA05 BC03 5G013 AA05 BA02 CB02 CB21 DA05 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Mitsuharu Maruyama 3-20-32 Tenryucho, Okaya-shi, Nagano Okaya Electric Industrial Co., Ltd.Nagano Works (72) Inventor Masayoshi Misawa 449 Teranakatsubo, Ina-shi, Nagano (72) Inventor Sou Yonekubo 4691 Kataoka, Shiojiri-shi, Nagano F-term (reference) 5C012 AA05 BC03 5G013 AA05 BA02 CB02 CB21 DA05
Claims (2)
板部材とを対向配置し、両基板部材の対向面周縁を気密
封止して外囲器を形成し、該外囲器内を高真空状態とな
すと共に、上記第１の基板部材の対向面及び第２の基板
部材の対向面の少なくとも一方に多数のエミッタ・コー
ンを形成し、当該エミッタ・コーンと他方の基板部材の
内面あるいはエミッタ・コーンとの間に所定の間隙を形
成し、さらに両基板部材の外面にそれぞれ外部電極を形
成してなる電界電子放出型サージ吸収素子の製造方法に
おいて、 上記枠部材として、内部に可動イオンを含む絶縁材より
なり、上記第１の基板部材の対向面周縁と接する第１の
端面と、上記第２の基板部材の対向面周縁と接する第２
の端面とを備えたものを用い、 該枠部材の第１の端面を上記第１の基板部材の対向面周
縁に接触させた状態で、第１の基板部材の外部電極に直
流電源のプラス側を接続させると共に、上記枠部材の第
２の端面に上記直流電源のマイナス側を接続し、所定の
温度に加熱しつつ上記直流電源より所定の電圧を印加し
て、第１の基板部材の対向面周縁と枠部材の第１の端面
とを陽極接合させ、 つぎに、枠部材の第２の端面を研磨して枠部材の高さを
調整し、 つぎに、真空雰囲気中において、当該枠部材の第２の端
面に上記第２の基板部材の対向面周縁を接触させた状態
で、第２の基板部材の外部電極に直流電源のプラス側を
接続させると共に、第１の基板部材の外部電極に上記直
流電源のマイナス側を接続し、所定の温度に加熱しつつ
上記直流電源より所定の電圧を印加して、第２の基板部
材の対向面周縁と枠部材の第２の端面とを陽極接合させ
ることを特徴とする電界電子放出型サージ吸収素子の製
造方法。A first substrate member and a second substrate member made of a semiconductor are arranged to face each other, and the peripheral edges of the opposing surfaces of both substrate members are hermetically sealed to form an envelope. Is formed in a high vacuum state, and a large number of emitter cones are formed on at least one of the opposing surface of the first substrate member and the opposing surface of the second substrate member, and the inner surfaces of the emitter cone and the other substrate member are formed. Alternatively, in a method for manufacturing a field electron emission type surge absorbing element in which a predetermined gap is formed between an emitter and a cone and external electrodes are formed on outer surfaces of both substrate members, the frame member is movable inside. A first end surface made of an insulating material containing ions and in contact with a peripheral edge of the opposing surface of the first substrate member; and a second end surface in contact with the peripheral edge of the opposing surface of the second substrate member.
With the first end face of the frame member in contact with the periphery of the facing surface of the first substrate member, the positive electrode of the DC power supply is connected to the external electrode of the first substrate member. And a minus side of the DC power supply is connected to the second end face of the frame member, and a predetermined voltage is applied from the DC power supply while heating to a predetermined temperature, so that the first substrate member faces the first substrate member. The peripheral edge of the surface and the first end face of the frame member are anodically bonded. Next, the second end face of the frame member is polished to adjust the height of the frame member. The positive side of the DC power supply is connected to the external electrode of the second substrate member while the peripheral edge of the opposing surface of the second substrate member is in contact with the second end surface of the second substrate member. The negative side of the DC power supply is connected to And more a predetermined voltage is applied, a method of manufacturing a field electron emission type surge absorber and a second end surface of the opposing surface perimeter and the frame member of the second substrate member, characterized in that to anodic bonding.
板部材とを対向配置し、両基板部材の対向面周縁を気密
封止して外囲器を形成し、該外囲器内を高真空状態とな
すと共に、上記第１の基板部材の対向面及び第２の基板
部材の対向面の少なくとも一方に多数のエミッタ・コー
ンを形成し、当該エミッタ・コーンと他方の基板部材の
内面あるいはエミッタ・コーンとの間に所定の間隙を形
成し、さらに両基板部材の外面にそれぞれ外部電極を形
成してなる電界電子放出型サージ吸収素子の製造方法に
おいて、 上記第１の基板部材及び第２の基板部材の少なくとも一
方の対向面周縁に枠状酸化膜を形成する工程と、 該枠状酸化膜が形成された基板部材を硫酸過酸化水中に
浸す工程と、 当該基板部材を純水中に浸した後、超音波振動を加えて
洗浄する工程と、 真空雰囲気中において、当該基板部材の枠状酸化膜と他
方の基板部材の対向面周縁あるいは枠状酸化膜とを重ね
合わせて加熱し、両接触面同士を共有結合させることを
特徴とする電界電子放出型サージ吸収素子の製造方法。A first substrate member and a second substrate member made of a semiconductor are arranged to face each other, and the peripheral edges of the opposing surfaces of the two substrate members are hermetically sealed to form an envelope; Is formed in a high vacuum state, and a large number of emitter cones are formed on at least one of the opposing surface of the first substrate member and the opposing surface of the second substrate member, and the inner surfaces of the emitter cone and the other substrate member are formed. Alternatively, in the method of manufacturing a field electron emission type surge absorbing element in which a predetermined gap is formed between the emitter and the cone, and external electrodes are respectively formed on outer surfaces of both substrate members, Forming a frame-shaped oxide film on the periphery of at least one of the opposing surfaces of the second substrate member; immersing the substrate member on which the frame-shaped oxide film is formed in sulfuric acid peroxide water; And then apply ultrasonic vibration And heating the frame-shaped oxide film of the substrate member and the periphery of the facing surface of the other substrate member or the frame-shaped oxide film in a vacuum atmosphere so that the two contact surfaces are covalently bonded to each other. A method for manufacturing a field electron emission type surge absorbing element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11186717A JP2001016769A (en) | 1999-06-30 | 1999-06-30 | Manufacture fo field electron/emission surge absorber element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11186717A JP2001016769A (en) | 1999-06-30 | 1999-06-30 | Manufacture fo field electron/emission surge absorber element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2001016769A true JP2001016769A (en) | 2001-01-19 |
Family
ID=16193415
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11186717A Ceased JP2001016769A (en) | 1999-06-30 | 1999-06-30 | Manufacture fo field electron/emission surge absorber element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2001016769A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007242612A (en) * | 2006-03-04 | 2007-09-20 | Samsung Sdi Co Ltd | Display device, and manufacturing method of the same |
-
1999
- 1999-06-30 JP JP11186717A patent/JP2001016769A/en not_active Ceased
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007242612A (en) * | 2006-03-04 | 2007-09-20 | Samsung Sdi Co Ltd | Display device, and manufacturing method of the same |
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