JP2000353779A - Compound semiconductor device - Google Patents

Compound semiconductor device

Info

Publication number
JP2000353779A
JP2000353779A JP11164177A JP16417799A JP2000353779A JP 2000353779 A JP2000353779 A JP 2000353779A JP 11164177 A JP11164177 A JP 11164177A JP 16417799 A JP16417799 A JP 16417799A JP 2000353779 A JP2000353779 A JP 2000353779A
Authority
JP
Japan
Prior art keywords
compound semiconductor
layer
metal
semiconductor device
buffer layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11164177A
Other languages
Japanese (ja)
Inventor
Shigehiro Hosoi
重広 細井
Hideyuki Hagiwara
秀幸 萩原
Hidetoshi Asahara
英敏 浅原
Masanori Ochi
雅範 越智
Yutaka Ueno
豊 上野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP11164177A priority Critical patent/JP2000353779A/en
Publication of JP2000353779A publication Critical patent/JP2000353779A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48475—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball
    • H01L2224/48476—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area
    • H01L2224/48491—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being an additional member attached to the bonding area through an adhesive or solder, e.g. buffer pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/10329—Gallium arsenide [GaAs]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13063—Metal-Semiconductor Field-Effect Transistor [MESFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/141—Analog devices
    • H01L2924/1423—Monolithic Microwave Integrated Circuit [MMIC]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PROBLEM TO BE SOLVED: To reduce the chip area of a compound semiconductor device by reducing the size of an area required for grounding, by providing a connecting section which connects an upper-layer metallic electrode to grounding wiring in the vertical direction of the upper-layer metallic electrode with respect to a substrate. SOLUTION: A buffer layer 5 is formed on an upper-layer metal 4, which is one electrode of a compound semiconductor device. The buffer layer 5 functions to relieve the impact applied to the metal 4 at bonding time. Since the relatively soft metal of the buffer layer 5 is crushed by the pressure applied to the metal 4 at bonding time, the impact applied to a dielectric layer 3 at bonding time is moderated, and the occurrence of such failures as cracks, etc., in the dielectric layer 3 is prevented. In addition, a flat layer 6 is formed on the buffer layer 5 as necessary. Then the upper-layer metal 4 is grounded by directly bonding a wire to the flat layer 6 or buffer layer 5, by using the flat layer 6 or buffer layer 5 as a bonding pad. Therefore, the area required for grounding can be reduced significantly.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】この発明は、化合物半導体基
板に形成されたＭＭＩＣ（Monolithic MicrowaveIntegr
ated Circuit）の受動素子の容量となるＭＩＭ（Metal
Insulator Metal）の構造を改善した化合物半導体装置
に関する。The present invention relates to an MMIC (Monolithic Microwave Integrated) formed on a compound semiconductor substrate.
MIM (Metal) that is the capacitance of the passive element of the ated circuit
The present invention relates to a compound semiconductor device having an improved structure of Insulator Metal).

【０００２】[0002]

【従来の技術】従来この種のＭＩＭキャパシタとして
は、下層金属に例えばＴｉ（チタン）＼Ａｕ（金）＼Ｔ
ｉの蒸着膜、誘電層にＳｉ（シリコン）の窒化膜、上層
金属にＴｉ＼Ｐｔ（白金）＼Ａｕの膜を用いて、化合物
半導体基板上に下層金属と上層金属で誘電層を挟んで形
成されたものがある。このような構造のＭＩＭキャパシ
タを用いて、ＭＭＩＣの能動素子として用いられた例え
ばＧａＡｓ系ＭＥＳＦＥＴのソース電極を接地する場合
には、例えば図５に示すような回路ならびに図６に示す
ようなレイアウトパターンとなる。図５ならびに図６に
おいて、ＦＥＴ１００のソース配線となる金属配線１０
１の途中から引き出された金属配線１０１を下層金属電
極としてＭＩＭキャパシタ１０２を形成し、ＭＩＭキャ
パシタ１０２の上層金属電極１０３がボンディングパッ
ド１０４を介してワイヤボンディングされて接地され
る。2. Description of the Related Art Conventionally, as a MIM capacitor of this type, for example, Ti (titanium) / Au (gold) / T
Using a deposited film of i, a nitride film of Si (silicon) for the dielectric layer, and a film of Ti / Pt (platinum) / Au for the upper metal, formed on the compound semiconductor substrate with the dielectric layer between the lower metal and the upper metal Something was done. When the MIM capacitor having such a structure is used to ground the source electrode of, for example, a GaAs-based MESFET used as an active element of the MMIC, for example, a circuit as shown in FIG. 5 and a layout pattern as shown in FIG. Becomes 5 and 6, a metal wiring 10 serving as a source wiring of the FET 100 is formed.
The MIM capacitor 102 is formed using the metal wiring 101 drawn out from the middle of the MIM 1 as a lower metal electrode, and the upper metal electrode 103 of the MIM capacitor 102 is wire-bonded via a bonding pad 104 and grounded.

【０００３】ここで、ボンディングパッド１０４にワイ
ヤボンディングする際に、ボンディング時の位置精度を
考慮して、ボンディングパッド１０４の周囲に余裕をも
たせたレイアウトをする必要がある。例えばボンディン
グワイヤ径が25μmφ を用いてボールボンディングした
場合に、パッド径は直径75μmφ 以上、クリアランスと
しては直径150μmφ以上の領域が必要となり、これらの
領域内に他の素子を形成ことはできない。したがって、
図５に示すような回路を構成するには、図６に示すよう
にＭＩＭキャパシタ１０２本体の形成領域、ボンディン
グパッド１０４の形成領域ならびにこれらの間のクリア
ランスの領域が必要となり、大きな面積を必要としてい
た。このため、図５に示す回路構成が増えるほど回路全
体の面積が大きくなり、チップ面積も増大し、高価な化
合物半導体基板のチップ単価も上昇し、またパッケージ
の小型化も困難にしていた。Here, when performing wire bonding to the bonding pad 104, it is necessary to provide a layout with a margin around the bonding pad 104 in consideration of positional accuracy during bonding. For example, when ball bonding is performed using a bonding wire having a diameter of 25 μmφ, a pad diameter of 75 μmφ or more and a clearance of 150 μmφ or more are required, and other elements cannot be formed in these areas. Therefore,
In order to form a circuit as shown in FIG. 5, a formation region of the MIM capacitor 102, a formation region of the bonding pad 104, and a clearance region therebetween are required as shown in FIG. Was. Therefore, as the circuit configuration shown in FIG. 5 increases, the area of the entire circuit increases, the chip area also increases, the cost per chip of the expensive compound semiconductor substrate increases, and it is difficult to reduce the size of the package.

【０００４】[0004]

【発明が解決しようとする課題】以上説明したように、
従来のＭＩＭキャパシタにおいて、一方の金属電極を接
地するためのボンディング領域は、ＭＩＭキャパシタ本
体の形成領域の周囲に所定の間隔を空けて設けられてい
たため、一方の金属電極が接地されたＭＩＭキャパシタ
を形成するためには大きな面積が必要になっていた。こ
のため、チップ面積が大きくなり、チップ面積の縮小化
を妨げるといった不具合を招いていた。As described above,
In a conventional MIM capacitor, a bonding region for grounding one metal electrode is provided at a predetermined interval around a region where the MIM capacitor body is formed. A large area was required to form. For this reason, the chip area is increased, which causes a problem of preventing the chip area from being reduced.

【０００５】そこで、この発明は、上記に鑑みてなされ
たものであり、その目的とするところは、金属電極と接
地配線との接続に必要となる領域を削減して、チップ面
積の縮小化を達成し得るＭＩＭキャパシタの化合物半導
体装置を提供することにある。Accordingly, the present invention has been made in view of the above, and an object of the present invention is to reduce a region required for connecting a metal electrode and a ground wiring to reduce a chip area. An object of the present invention is to provide a compound semiconductor device of an MIM capacitor that can be achieved.

【０００６】[0006]

【課題を解決するための手段】上記目的を達成するため
に、課題を解決する第１の手段は、化合物半導体基板上
に２つの金属電極で誘電層を挟んで形成されたＭＩＭキ
ャパシタの化合物半導体装置において、一方の前記金属
電極と接地配線とを接続する接続部が、前記化合物半導
体基板に対して前記一方の金属電極の鉛直方向に設けら
れてなることを特徴とする。Means for Solving the Problems To achieve the above object, a first means for solving the problems is to provide a compound semiconductor for an MIM capacitor formed on a compound semiconductor substrate by sandwiching a dielectric layer between two metal electrodes. The device is characterized in that a connecting portion for connecting one of the metal electrodes and a ground wiring is provided in a direction perpendicular to the one of the metal electrodes with respect to the compound semiconductor substrate.

【０００７】第２の手段は、前記第１の手段において、
前記一方の金属電極は、前記２つの金属電極の内、前記
化合物半導体基板からより離れて形成された金属電極か
らなり、前記接続部には、一方の前記金属電極と前記接
地配線との接続時の衝撃を緩和する緩衝層が設けられて
なることを特徴とする。[0007] The second means is the first means,
The one metal electrode is formed of a metal electrode formed more distant from the compound semiconductor substrate among the two metal electrodes, and the connection portion is connected to one of the metal electrodes and the ground wiring. Characterized in that a shock-absorbing layer is provided to reduce the impact.

【０００８】第３の手段は、前記第２の手段において、
前記緩衝層は、断面が凹凸状に形成され接続時に潰れて
なることを特徴とする。[0008] The third means is the second means,
The buffer layer is characterized in that its cross section is formed in an uneven shape and collapsed at the time of connection.

【０００９】第４の手段は、前記第２の手段において、
前記緩衝層は、ボール状に形成され接続時に潰れてなる
ことを特徴とする。A fourth means is the second means,
The buffer layer is formed in a ball shape and collapsed at the time of connection.

【００１０】第５の手段は、前記第１の手段において、
前記誘電層ならびに前記一方の金属電極は前記化合物半
導体基板に埋め込まれて形成され、前記接続部には、給
電用電極が前記化合物半導体基板に埋め込まれて前記一
方の金属電極に積層形成され、前記給電用電極の一方の
面は前記化合物半導体基板の裏面に露出されてなること
を特徴とする。The fifth means is the first means,
The dielectric layer and the one metal electrode are formed by being embedded in the compound semiconductor substrate, and in the connection portion, a power supply electrode is embedded in the compound semiconductor substrate and is formed by lamination on the one metal electrode, One surface of the power supply electrode is exposed on the back surface of the compound semiconductor substrate.

【００１１】[0011]

【発明の実施の形態】以下、図面を用いてこの発明の実
施形態を説明する。Embodiments of the present invention will be described below with reference to the drawings.

【００１２】図１は請求項１，２又は３記載の発明の一
実施形態に係る化合物半導体装置の断面構造を示す図で
ある。FIG. 1 is a view showing a sectional structure of a compound semiconductor device according to an embodiment of the present invention.

【００１３】図１において、この実施形態における化合
物半導体装置のＭＩＭキャパシタは、ＧａＡｓの化合物
半導体基板１上に例えばＴｉ＼Ｐｔ＼Ａｕ＼Ｔｉからな
る下層金属２が蒸着形成され、この下層金属２上に例え
ばＳｉの窒化膜からなる誘電層３がＣＶＤ法により形成
され、この誘電層３上に例えばＴｉ＼Ｐｔ＼Ａｕからな
る上層金属４が蒸着形成されている。さらに、上層金属
４上に例えばＴｉ＼Ａｕからなる緩衝層５が10μmのオ
ーダの厚さで積層形成されている。この緩衝層５は、ボ
ンディング時の衝撃を緩和する機能を有するものであ
り、ボンディング時の圧力により緩衝層５の比較的柔ら
かなＡｕが潰れることにより、ボンディング時の誘電層
３への衝撃は和らげられ、ボンディングにより誘電層５
にクラック等の不具合が発生することは防止される。緩
衝層５は、図２（Ａ）に示すように円筒形状を基本構造
とし、応用構造として例えば同図（Ｂ）に示すようにく
形の凹凸構造や、同図（Ｃ）に示すように柱状の凹凸構
造、もしくは同図（Ｄ）に示すようにリング状の凹凸構
造としても同様の効果を得ることができる。緩衝層５上
には、例えばＴｉ＼Ａｕからなる平坦層６が形成されて
いる。この平坦層６をボンディングパッドとしてこの平
坦層６に接地に接続されたワイヤ７を直接ワイヤボンデ
ィングする。なお、平坦層６を形成せずに、緩衝層５を
ボンディングパッドとして緩衝層５に直接ワイヤボンデ
ィングするようにしてもよい。Referring to FIG. 1, a MIM capacitor of a compound semiconductor device according to this embodiment has a lower metal 2 made of, for example, Ti＼Pt＼Au＼Ti deposited on a GaAs compound semiconductor substrate 1. A dielectric layer 3 made of, for example, a nitride film of Si is formed by a CVD method, and an upper metal layer 4 made of, for example, Ti / Pt / Au is formed on the dielectric layer 3 by vapor deposition. Further, a buffer layer 5 made of, for example, Ti @ Au is formed on the upper metal layer 4 in a thickness of the order of 10 μm. The buffer layer 5 has a function of alleviating the shock at the time of bonding, and the relatively soft Au of the buffer layer 5 is crushed by the pressure at the time of bonding, so that the shock to the dielectric layer 3 at the time of bonding is moderated. And the dielectric layer 5 is formed by bonding.
The occurrence of troubles such as cracks is prevented. The buffer layer 5 has a cylindrical basic structure as shown in FIG. 2A, and as an applied structure, for example, a concave and convex structure as shown in FIG. 2B, or as shown in FIG. The same effect can be obtained by using a pillar-shaped uneven structure or a ring-shaped uneven structure as shown in FIG. On the buffer layer 5, a flat layer 6 made of, for example, Ti＼Au is formed. Using the flat layer 6 as a bonding pad, a wire 7 connected to the ground is directly wire-bonded to the flat layer 6. Note that the buffer layer 5 may be directly bonded to the buffer layer 5 by using the buffer layer 5 as a bonding pad without forming the flat layer 6.

【００１４】このように、ＭＩＭキャパシタが形成され
た領域の鉛直方向上部に設けられた緩衝層５又は平坦層
６に直接ボンディングして、ＭＩＭキャパシタの一方の
金属電極を接地配線することにより、接地のために必要
となる面積を従来に比べて大幅に縮小することが可能と
なる。例えば、150μm×150μmの面積のＭＩＭキャパシ
タに25μmのワイヤ径でボールボンディングする場合
に、図６に示す従来のレイアウトパターンにおいては、
クリアランスを含めて31000μm2程度の面積が必要にな
っていたが、上記実施形態の構造にあっては、ＭＩＭキ
ャパシタの形成面積の22500μm2 程度となり、従来に比
べて8500μm2もチップ面積を縮小化できる。これは、Ｍ
ＩＭキャパシタ１個当たりの縮小面積であり、接地を必
要とするＭＩＭキャパシタの個数が増えるほどチップ面
積の縮小面積も大きくなる。As described above, the first metal electrode of the MIM capacitor is grounded by directly bonding to the buffer layer 5 or the flat layer 6 provided above the region where the MIM capacitor is formed in the vertical direction. The area required for this can be greatly reduced as compared with the related art. For example, when ball bonding is performed on a MIM capacitor having an area of 150 μm × 150 μm with a wire diameter of 25 μm, the conventional layout pattern shown in FIG.
Although 31000Myuemu 2 about an area including the clearance had become necessary, in the structure of the above embodiment, it becomes 22500Myuemu 2 about the formation area of the MIM capacitor, 8500Myuemu 2 also reduce the chip area as compared with the conventional it can. This is M
This is the reduced area per IM capacitor. As the number of MIM capacitors requiring grounding increases, the reduced area of the chip area also increases.

【００１５】図３は請求項５記載の発明の一実施形態に
係る化合物半導体装置の断面構造を示す図である。FIG. 3 is a view showing a sectional structure of a compound semiconductor device according to one embodiment of the invention.

【００１６】図３において、この実施形態における化合
物半導体装置のＭＩＭキャパシタは、ＧａＡｓの化合物
半導体基板１１にＭＩＭキャパシタを埋め込み形成し、
基板１１の裏面からＭＩＭキャパシタに接地給電するよ
うにしたものであり、基板１１の表面に例えばＰｔ＼Ｔ
ｉ＼Ｐｔ＼Ａｕからなる上層金属１２を蒸着形成し、基
板１１の裏面から上層金属１２に向けて上層金属１２で
自己停止するまで基板１１を選択的にエッチング除去し
て溝を形成し、ＳＴＯ膜をスパッタ形成して誘電層１３
を形成し、例えばＡｕ＼Ｔｉ＼Ｐｔからなる下層金属１
４を蒸着形成し、レジストパターン１５をマスクに例え
ばＡｕの給電用電極１６を溝に選択的にメッキ形成し、
レジスタパターン１５、誘電層１３、下層金属１４を所
望の大きさにエッチングし、ＭＩＭキャパシタならびに
給電用電極１６が基板１１に埋め込まれて給電用電極１
６が基板１１の裏面から露出されるように基板１１の裏
面を平坦化して形成される。In FIG. 3, the MIM capacitor of the compound semiconductor device in this embodiment is formed by embedding the MIM capacitor in a GaAs compound semiconductor substrate 11.
Ground power is supplied to the MIM capacitor from the back surface of the substrate 11.
An upper metal layer 12 of i＼Pt＼Au is formed by vapor deposition, and the substrate 11 is selectively etched away from the back surface of the substrate 11 toward the upper metal layer 12 until the upper metal layer 12 is stopped by itself. The film is formed by sputtering to form the dielectric layer 13.
And a lower metal layer 1 made of, for example, AuＡTi＼Pt.
4 is formed by vapor deposition, and a power supply electrode 16 of, for example, Au is selectively formed in a groove by using the resist pattern 15 as a mask.
The register pattern 15, the dielectric layer 13, and the lower metal 14 are etched to a desired size, and the MIM capacitor and the power supply electrode 16 are embedded in the substrate 11 so that the power supply electrode 1 is formed.
6 is formed by flattening the back surface of the substrate 11 so as to be exposed from the back surface of the substrate 11.

【００１７】このような構成においては、チップをマウ
ントした際に給電用電極１６を介して基板１１の裏面か
ら直接接地給電することが可能となり、ＭＩＭキャパシ
タの形成領域の鉛直方向に接地のための接続部を形成す
ることができる。したがって、このような実施形態にお
いても、上記実施形態と同様の効果を得ることができ
る。In such a configuration, when the chip is mounted, it is possible to directly supply the ground power from the back surface of the substrate 11 via the power supply electrode 16, so that the ground for the ground is formed in the vertical direction of the MIM capacitor formation region. Connections can be formed. Therefore, in such an embodiment, the same effect as in the above embodiment can be obtained.

【００１８】図４は請求項４記載の発明の一実施形態に
係る化合物半導体装置の断面構造を示す図である。FIG. 4 is a view showing a sectional structure of a compound semiconductor device according to an embodiment of the present invention.

【００１９】図４において、この実施形態の特徴とする
ところは、図１に示す実施形態に比べて、図１に示す緩
衝層５ならびに平坦層６に代えて、上層金属４上に金ボ
ール１７を選択的にメッキ形成したことにあり、バンプ
方式の実装形態において接地給電するリード端子を金ボ
ール１７に接合することにより、ＭＩＭキャパシタの上
層電極４にＭＩＭキャパシタの鉛直方向から接地給電す
ることが可能となる。このような実施形態においては、
リード端子を金ボール１７に接合する際の衝撃は金ボー
ル１７が潰れることにより緩和され、誘電層３へのダメ
ージは回避され、上記実施形態と同様の効果を得ること
ができる。In FIG. 4, a feature of this embodiment is that, unlike the embodiment shown in FIG. 1, a gold ball 17 is provided on the upper metal 4 in place of the buffer layer 5 and the flat layer 6 shown in FIG. Is selectively formed by plating, and in the mounting method of the bump type, the ground terminal is connected to the gold ball 17 so that the ground electrode is supplied to the upper electrode 4 of the MIM capacitor from the vertical direction of the MIM capacitor. It becomes possible. In such an embodiment,
The impact at the time of joining the lead terminal to the gold ball 17 is mitigated by the crushing of the gold ball 17, damage to the dielectric layer 3 is avoided, and the same effect as in the above embodiment can be obtained.

【００２０】[0020]

【発明の効果】以上説明したように、この発明によれ
ば、ＭＩＭキャパシタの一方の金属電極と接地配線とを
接続する接続部を、基板に対して一方の金属電極の鉛直
方向に設けるようにしたので、接地に必要となる領域の
面積を削減することが可能となり、チップ面積を縮小す
ることができる。As described above, according to the present invention, the connecting portion for connecting one metal electrode of the MIM capacitor and the ground wiring is provided in the direction perpendicular to the one metal electrode with respect to the substrate. Therefore, the area of the region required for grounding can be reduced, and the chip area can be reduced.

【図面の簡単な説明】[Brief description of the drawings]

【図１】請求項１，２又は３記載の発明の一実施形態に
係る化合物半導体装置の構成を示す図である。FIG. 1 is a diagram showing a configuration of a compound semiconductor device according to an embodiment of the present invention.

【図２】図１に示す緩衝層の構成例を示す図である。FIG. 2 is a diagram showing a configuration example of a buffer layer shown in FIG.

【図３】請求項５記載の発明の一実施形態に係る化合物
半導体装置の構成を示す図である。FIG. 3 is a diagram showing a configuration of a compound semiconductor device according to one embodiment of the invention described in claim 5;

【図４】請求項４記載の発明の一実施形態に係る化合物
半導体装置の構成を示す図である。FIG. 4 is a diagram showing a configuration of a compound semiconductor device according to one embodiment of the invention described in claim 4;

【図５】ＭＥＳＦＥＴのソース電極を接地する場合の回
路構成を示す図である。FIG. 5 is a diagram showing a circuit configuration when a source electrode of a MESFET is grounded.

【図６】図５に示す回路のレイアウトパターンを示す図
である。FIG. 6 is a diagram showing a layout pattern of the circuit shown in FIG. 5;

【符号の説明】[Explanation of symbols]

１，１１ 化合物半導体基板 ２，１４ 下層電極 ３，１３ 誘電層 ４，１２ 上層電極 ５ 緩衝層 ６ 平坦層 ７ ボンディングワイヤ １５ レジストパターン １６ 給電用電極 １７ 金ボール Reference Signs List 1,11 Compound semiconductor substrate 2,14 Lower layer electrode 3,13 Dielectric layer 4,12 Upper layer electrode 5 Buffer layer 6 Flat layer 7 Bonding wire 15 Resist pattern 16 Power supply electrode 17 Gold ball

フロントページの続き (72)発明者 浅原 英敏 神奈川県川崎市幸区小向東芝町１番地 株 式会社東芝マイクロエレクトロニクスセン ター内 (72)発明者 越智 雅範 神奈川県川崎市幸区小向東芝町１番地 株 式会社東芝マイクロエレクトロニクスセン ター内 (72)発明者 上野 豊 神奈川県川崎市幸区小向東芝町１番地 株 式会社東芝マイクロエレクトロニクスセン ター内 Ｆターム(参考） 5F038 AC05 AC15 BE07 BE10 CA05 CA07 DF02 EZ02 EZ14 EZ15 EZ20 5F044 EE01 EE17 5F102 FA10 GA16 GB01 GB02 GC01 GD01 GJ05 GR10 GV03 HC11 HC16 HC30 Continuing on the front page (72) Inventor Hidetoshi Asahara 1st address, Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Prefecture Inside the Toshiba Microelectronics Center Co., Ltd. (72) Inventor Masanori Ochi 1 Komukai-Toshiba-cho, Koyuki-ku, Kawasaki-shi, Kanagawa Address: Toshiba Microelectronics Center Co., Ltd. (72) Inventor Yutaka Ueno 1st, Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Prefecture F-term: 5F038 AC05 AC15 BE07 BE10 CA05 CA07 DF02 EZ02 EZ14 EZ15 EZ20 5F044 EE01 EE17 5F102 FA10 GA16 GB01 GB02 GC01 GD01 GJ05 GR10 GV03 HC11 HC16 HC30

Claims (5)

【特許請求の範囲】[Claims] 【請求項１】 化合物半導体基板上に２つの金属電極で
誘電層を挟んで形成されたＭＩＭキャパシタの化合物半
導体装置において、 一方の前記金属電極と接地配線とを接続する接続部が、
前記化合物半導体基板に対して前記一方の金属電極の鉛
直方向に設けられてなることを特徴とする化合物半導体
装置。1. A compound semiconductor device of an MIM capacitor formed on a compound semiconductor substrate by sandwiching a dielectric layer between two metal electrodes, wherein a connecting portion connecting one of the metal electrodes to a ground wiring is provided.
A compound semiconductor device provided in a direction perpendicular to the one metal electrode with respect to the compound semiconductor substrate. 【請求項２】 前記一方の金属電極は、前記２つの金属
電極の内、前記化合物半導体基板からより離れて形成さ
れた金属電極からなり、 前記接続部には、一方の前記金属電極と前記接地配線と
の接続時の衝撃を緩和する緩衝層が設けられてなること
を特徴とする請求項１記載の化合物半導体装置。2. The one metal electrode of the two metal electrodes is formed of a metal electrode formed further away from the compound semiconductor substrate, and the connection portion includes one of the metal electrode and the ground. 2. The compound semiconductor device according to claim 1, wherein a buffer layer is provided to reduce a shock at the time of connection with the wiring. 【請求項３】 前記緩衝層は、断面が凹凸状に形成され
接続時に潰れてなることを特徴とする請求項２記載の化
合物半導体装置。3. The compound semiconductor device according to claim 2, wherein the buffer layer has a cross section formed in an uneven shape and is crushed at the time of connection. 【請求項４】 前記緩衝層は、ボール状に形成され接続
時に潰れてなることを特徴とする請求項２記載の化合物
半導体装置。4. The compound semiconductor device according to claim 2, wherein said buffer layer is formed in a ball shape and crushed at the time of connection. 【請求項５】 前記誘電層ならびに前記一方の金属電極
は前記化合物半導体基板に埋め込まれて形成され、 前記接続部には、給電用電極が前記化合物半導体基板に
埋め込まれて前記一方の金属電極に積層形成され、前記
給電用電極の一方の面は前記化合物半導体基板の裏面に
露出されてなることを特徴とする請求項１記載の化合物
半導体装置。5. The dielectric layer and the one metal electrode are formed by being embedded in the compound semiconductor substrate. In the connection portion, a power supply electrode is embedded in the compound semiconductor substrate, and the power supply electrode is embedded in the compound semiconductor substrate. 2. The compound semiconductor device according to claim 1, wherein one side of said power supply electrode is formed in a laminated manner and is exposed on a back surface of said compound semiconductor substrate.
JP11164177A 1999-06-10 1999-06-10 Compound semiconductor device Pending JP2000353779A (en)

Priority Applications (1)

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JP11164177A JP2000353779A (en) 1999-06-10 1999-06-10 Compound semiconductor device

Applications Claiming Priority (1)

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JP11164177A JP2000353779A (en) 1999-06-10 1999-06-10 Compound semiconductor device

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Publication Number Publication Date
JP2000353779A true JP2000353779A (en) 2000-12-19

Family

ID=15788192

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002299462A (en) * 2001-01-26 2002-10-11 Nokia Mobile Phones Ltd Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002299462A (en) * 2001-01-26 2002-10-11 Nokia Mobile Phones Ltd Semiconductor device

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