JPS6247139A - Forming method for transfer bump substrate - Google Patents
Forming method for transfer bump substrateInfo
- Publication number
- JPS6247139A JPS6247139A JP18691785A JP18691785A JPS6247139A JP S6247139 A JPS6247139 A JP S6247139A JP 18691785 A JP18691785 A JP 18691785A JP 18691785 A JP18691785 A JP 18691785A JP S6247139 A JPS6247139 A JP S6247139A
- Authority
- JP
- Japan
- Prior art keywords
- electrodes
- substrate
- bumps
- bump
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、バンプを介して半導体素子を接合するフィル
ムキャリア方式の半導体組立てに用いる転写バンプ基板
の形成方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for forming a transfer bump substrate used in film carrier type semiconductor assembly in which semiconductor elements are bonded via bumps.
従来の技術
従来の転写バンプ基板上に形成されたバンプをインナリ
ードに転写して、バンプを半導体素子の電極に熱圧着で
接合する方法は次のとおりである。2. Description of the Related Art A conventional method for transferring bumps formed on a transfer bump substrate onto inner leads and bonding the bumps to electrodes of a semiconductor element by thermocompression bonding is as follows.
すなわち、まず第３図に示すように、ガラス基板のよう
な絶縁基板１の上全面にＰｔ、 Ｐｄ、 Ａｕなど −
ｚ−−
の電極膜２全形成したあと、８１０２などの絶縁膜３を
形成して、絶縁膜３に所定のパターン４をエツチング法
等によって形成して転写バンプ基板全行る。次いでパタ
ーン４の部分に第４図ｄに示すような金製のバンプ５金
メツキなどで形成した後、前記転写バンプ基板を第１の
テーブル６上にセツティングして、フィルムキャリアの
インナリード７と金製のバンプ５′ｆｆ：位置合せし、
その後にボンディングツール８でインナリード７と金製
のバンプ５を接合して、金製のバンプ５のみを電極膜２
より分離させる。その後第４図すに示すように第２のテ
ーブル９上に半導体素子１０全セツテイングして、金製
のバンプ５と半導体素子１ｏのＡｄ電極１１とを位置合
せしてボンディングツール８で金製のバンプ６と半導体
素子１ｏのＡＩ電極１１とを接合させて作業が完了する
。That is, as shown in FIG. 3, first, Pt, Pd, Au, etc. are applied to the entire upper surface of an insulating substrate 1 such as a glass substrate.
After the entire electrode film 2 of z-- is formed, an insulating film 3 such as 8102 is formed, and a predetermined pattern 4 is formed on the insulating film 3 by etching or the like to form a transfer bump substrate. Next, gold bumps 5 as shown in FIG. 4d are formed on the pattern 4 by gold plating, and then the transfer bump substrate is set on the first table 6 and the inner leads 7 of the film carrier are formed. and gold bump 5'ff: aligned,
After that, the inner lead 7 and the gold bump 5 are bonded using the bonding tool 8, and only the gold bump 5 is bonded to the electrode film 2.
Separate more. Thereafter, as shown in FIG. 4, the entire semiconductor element 10 is set on the second table 9, the gold bumps 5 and the Ad electrodes 11 of the semiconductor element 1o are aligned, and the gold bumps 5 are aligned with the Ad electrodes 11 of the semiconductor element 1o. The work is completed by joining the bumps 6 and the AI electrodes 11 of the semiconductor element 1o.
発明が解決しようとする問題点
ところが上記方法では、転写バンプ基板の絶縁膜３を５
０００人程度に形成しなければならないため、ピンホー
ルが多く発生することがあった。Problems to be Solved by the Invention However, in the above method, the insulating film 3 of the transfer bump substrate is
000, many pinholes may occur.
３ ・・ 。3...
その結果として第３図ａに示す」：うに、ピンホール部
１２に余分々バンプ１３が形成され、これが転写時にボ
ンディングツール８やインナリー ドアに付着するとい
う問題があった。As a result, an extra bump 13 is formed in the pinhole portion 12 as shown in FIG.
問題点全解決するだめの手段
上記の問題点を解決するだめ、本発明の転写バンプ基板
の形成方法は、基板の一面の所定位置に島状の多数の電
極を互いに船乗した状態で形成すると共に、これら電極
を結ぶ配線を形成し、次いで電極を除いた部分を被覆す
る絶縁膜を形成することを特徴とする。Means to Solve All Problems In order to solve the above problems, the method for forming a transfer bump substrate of the present invention involves forming a large number of island-shaped electrodes at predetermined positions on one surface of the substrate in a state in which they are mounted on top of each other. At the same time, the method is characterized in that wiring is formed to connect these electrodes, and then an insulating film is formed to cover a portion other than the electrodes.
作 用
゛本発明によると、転写バンプ基板の基板−Ｌに形成さ
れた導電部は、島状の電極と配線からなり、必要最小面
積に抑えられているので、基板全面に電極膜が形成され
ている従来例に比較して導電面積は激減する。従って絶
縁膜にピンホールが生じても、その部分にメッキ物が形
成される確率は極端に少なくなる。Effect: According to the present invention, the conductive portion formed on the substrate-L of the transfer bump substrate consists of island-shaped electrodes and wiring, and is suppressed to the minimum required area, so that an electrode film is not formed on the entire surface of the substrate. The conductive area is drastically reduced compared to the conventional example. Therefore, even if a pinhole occurs in the insulating film, the probability that a plated material will be formed in that portion is extremely reduced.
実施例 本発明の実施例を第１図に基づいて説明する。Example An embodiment of the present invention will be described based on FIG.
ガラス基板２ｏの上にＰｔ、 Ｐｄ、 Ａｕなどの島状
電極２１とそれら島状電極２１を結ぶ配線２２を真空蒸
着法等により１００人から２０ｏｏへの厚さに形成した
のち、Ｓ １０２ 、 Ｓ ｘＮ等の無機絶縁膜２３を
ガラス基板の全面に３ｏＯＯ八〜１５０００、への厚さ
に形成した後、各電極２１に対応する位置にパターン孔
２４をエツチングによって形成する。Island electrodes 21 made of Pt, Pd, Au, etc. and wiring 22 connecting the island electrodes 21 are formed on a glass substrate 2o to a thickness of 100 to 200 mm by vacuum evaporation, etc., and then S102, S After forming an inorganic insulating film 23 such as xN on the entire surface of the glass substrate to a thickness of 3000 to 15000, pattern holes 24 are formed at positions corresponding to each electrode 21 by etching.
このようにして形成された転写バンプ基板は次のように
使用される。すなわち第２齢示すように、パターン２４
部の島状電極２１にメッキ法によって金製のバンプ２５
を高さ１０１ｔｍ〜３６μｍに形成したあと、この転写
バンブ基板金弟１のテーブル２６にセツティングしてフ
ィルムキャリアのインナリード２７と金製のバンプ２６
とを位置合せしてボンディングツール２８でインナリー
ド２７と金製のバンプ２５′ｆ：接合してから、金製の
バンプ２５のみを島状電極２１より分離させ、つぎに第
２図すに示すように第２のテーブル２９の６ヘーノ
上に半導体素子３０をセツティングして、金製のバンプ
２５と半導体素子３０のＡＩ電極３１と全位置合せして
ボンディングツール２８で金製のノ（ンブ２５と半導体
素子３ｏのＡＩ電極３１と全接合させる。The thus formed transfer bump substrate is used as follows. That is, as shown in the second instar, pattern 24
Gold bumps 25 are formed by plating on the island-like electrodes 21 of the
After forming the transfer bump board to a height of 101 tm to 36 μm, the transfer bump board is set on the table 26 of the gold plate 1, and the inner leads 27 of the film carrier and the gold bumps 26 are formed.
After aligning and bonding the inner lead 27 and the gold bump 25'f with the bonding tool 28, only the gold bump 25 is separated from the island electrode 21, and then the gold bump 25'f is separated from the island electrode 21 as shown in FIG. Set the semiconductor element 30 on the second table 29 as shown in FIG. 25 and the AI electrode 31 of the semiconductor element 3o are fully connected.
なお、島状電極２１はＰｔ−ＩＴＯのような多層構造に
なっていてもよい。Note that the island electrode 21 may have a multilayer structure such as Pt-ITO.
発明の効果
本発明によれば、転写バンプ基板の絶縁膜にピンホール
が発生しても、その下地に電極膜がある確率が少なくな
るため、ピンホールによる余分なバンプが形成されるこ
とが少なくなり、これがボンディングツールやインナリ
ードに付着する確率が少なくなる。Effects of the Invention According to the present invention, even if a pinhole occurs in the insulating film of the transfer bump substrate, the probability that there is an electrode film underlying it is reduced, so the formation of unnecessary bumps due to the pinhole is reduced. This reduces the probability that this will adhere to the bonding tool or inner lead.
例を示す縦断面図、第３図は従来例を示し、ｂはその平
面図、良はＢ−Ｂ断面図、第４図はａ、ｂ共その使用例
を示す縦断面図である。
６ メ＼−／
２０・・・・・・基板、２１・・・電極、２２・・・・
・配線、２３・・・・・・絶縁膜。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名２θ
−基林
２３−−−Ｈ隷ｎス
第２図
第３図
１５？１−
第４図FIG. 3 shows a conventional example, b is a plan view thereof, good is a BB sectional view, and FIG. 4 is a longitudinal sectional view showing an example of its use. 6 Me\-/ 20... Substrate, 21... Electrode, 22...
・Wiring, 23...Insulating film. Name of agent: Patent attorney Toshio Nakao and one other person 2θ
-Kibayashi 23--H Rei nth Figure 2 Figure 3 15?1- Figure 4
Claims (1)
した状態で形成すると共に、これら電極を結ぶ配線を形
成し、次いで電極を除いた部分を被覆する絶縁膜を形成
することを特徴とする転写バンプ基板の形成方法。It is characterized by forming a large number of island-shaped electrodes at predetermined positions on one surface of the substrate, separated from each other, forming wiring to connect these electrodes, and then forming an insulating film to cover the part other than the electrodes. A method for forming a transfer bump substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18691785A JPH0640559B2 (en) | 1985-08-26 | 1985-08-26 | Method for forming transfer bump substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18691785A JPH0640559B2 (en) | 1985-08-26 | 1985-08-26 | Method for forming transfer bump substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6247139A true JPS6247139A (en) | 1987-02-28 |
| JPH0640559B2 JPH0640559B2 (en) | 1994-05-25 |
Family
ID=16196952
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18691785A Expired - Lifetime JPH0640559B2 (en) | 1985-08-26 | 1985-08-26 | Method for forming transfer bump substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0640559B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS649643A (en) * | 1987-07-02 | 1989-01-12 | Matsushita Electric Ind Co Ltd | Substrate on which transfer bump be formed |
| JPH045325U (en) * | 1990-05-02 | 1992-01-17 | ||
| JPH0639661A (en) * | 1992-07-23 | 1994-02-15 | Komoda Kogyo:Kk | Automatic prefabricated piping machining system and its equipment |
| JPH06182642A (en) * | 1992-12-18 | 1994-07-05 | Fukudagumi:Kk | Mobile rod-like building member finishing machine |
-
1985
- 1985-08-26 JP JP18691785A patent/JPH0640559B2/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS649643A (en) * | 1987-07-02 | 1989-01-12 | Matsushita Electric Ind Co Ltd | Substrate on which transfer bump be formed |
| JPH045325U (en) * | 1990-05-02 | 1992-01-17 | ||
| JPH0639661A (en) * | 1992-07-23 | 1994-02-15 | Komoda Kogyo:Kk | Automatic prefabricated piping machining system and its equipment |
| JPH06182642A (en) * | 1992-12-18 | 1994-07-05 | Fukudagumi:Kk | Mobile rod-like building member finishing machine |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0640559B2 (en) | 1994-05-25 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |