JP2000353769A - Semiconductor element mounting ceramic board - Google Patents

Semiconductor element mounting ceramic board

Info

Publication number
JP2000353769A
JP2000353769A JP11165192A JP16519299A JP2000353769A JP 2000353769 A JP2000353769 A JP 2000353769A JP 11165192 A JP11165192 A JP 11165192A JP 16519299 A JP16519299 A JP 16519299A JP 2000353769 A JP2000353769 A JP 2000353769A
Authority
JP
Japan
Prior art keywords
semiconductor element
ceramic
sheet
resin
outermost
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11165192A
Other languages
Japanese (ja)
Inventor
Yasuto Kudo
康人 工藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Metal Mining Co Ltd
Original Assignee
Sumitomo Metal Mining Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Metal Mining Co Ltd filed Critical Sumitomo Metal Mining Co Ltd
Priority to JP11165192A priority Critical patent/JP2000353769A/en
Publication of JP2000353769A publication Critical patent/JP2000353769A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor element mounting ceramic board, where voids are hardly generated in resin which is poured into a gap between a semiconductor element and an outermost ceramic sheet. SOLUTION: A semiconductor element mounting ceramic board 10 has a structure, where a laminate 14 is composed of ceramic sheets where wiring patterns are provided, semiconductor elements are mounted on a first ceramic green sheet 11 of the laminate 14 in a flip-chip bonding manner, and the semiconductor elements are fixed by resin poured into a gap between the semiconductor elements and the first ceramic green sheet 11. The opening of a via 1, provided to a region of the ceramic sheet 11 that confronts the semiconductor element, is covered with a thin ceramic material film (ceramic coating 20).

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、配線パターンが設
けられた複数セラミックシートの積層体によりその主要
部が構成され、かつ、一方の最外セラミックシート側に
半導体素子がフリップチップ接合される半導体素子搭載
用セラミック基板に係り、特に、半導体素子と最外セラ
ミックシートとの隙間に注入される樹脂中にボイド(voi
d)が発生し難い半導体素子搭載用セラミック基板の改良
に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor in which a main part is constituted by a laminate of a plurality of ceramic sheets provided with a wiring pattern, and a semiconductor element is flip-chip bonded to one of the outermost ceramic sheets. Regarding the ceramic substrate for mounting the element, in particular, the void (voi) in the resin injected into the gap between the semiconductor element and the outermost ceramic sheet
The present invention relates to improvement of a ceramic substrate for mounting a semiconductor element, which is unlikely to cause d).

【０００２】[0002]

【従来の技術】半導体素子(半導体チップ)における微細
な入出力パッドとマザーボード(プリント基板)に形成さ
れた配線との接続を容易にし、かつ、半導体素子とマザ
ーボードとの熱膨張率の差を緩和し、更に半導体素子を
湿度から保護するため、半導体素子は種々の形態にパッ
ケージされて用いられる。中でも、セラミックを用いた
パッケージは、耐湿性、耐熱性、シリコンに近似した熱
膨張率、熱伝導率の各々についてその特性に優れるため
信頼性が高く広く利用されている。2. Description of the Related Art It is easy to connect fine input / output pads of a semiconductor element (semiconductor chip) to wiring formed on a motherboard (printed circuit board) and to reduce the difference in coefficient of thermal expansion between the semiconductor element and the motherboard. In addition, in order to further protect the semiconductor element from humidity, the semiconductor element is used by being packaged in various forms. Above all, packages using ceramics are widely used because of their high reliability because of their excellent properties in moisture resistance, heat resistance, thermal expansion coefficient and thermal conductivity close to those of silicon.

【０００３】そして、近年、電子機器の小型化と共に高
性能化が急激に進展しており、半導体素子とセラミック
基板とをワイヤボンディングしてからセラミック容器に
封入する従来のセラミック容器タイプに変わって、半導
体素子をセラミック基板にフリップチップ接合しかつセ
ラミック基板と半導体素子との隙間に樹脂を注入して半
導体素子を固定するフリップチップタイプが主流となっ
ている。[0003] In recent years, the performance of electronic devices has been rapidly reduced along with their miniaturization, and instead of the conventional ceramic container type in which a semiconductor element and a ceramic substrate are wire-bonded and then sealed in a ceramic container, A flip chip type in which a semiconductor element is flip-chip bonded to a ceramic substrate and a semiconductor element is fixed by injecting a resin into a gap between the ceramic substrate and the semiconductor element has become mainstream.

【０００４】図４は従来のセラミック容器タイプ、図５
はフリップチップタイプをそれぞれ示している。すなわ
ち、従来のセラミック容器タイプは、図４に示すように
配線パターンが設けられたセラミックシートa1、a2、a3
の積層体から成るセラミック基板ａと、このセラミック
基板ａにおける一方の最外セラミックシートa1側に固定
されかつ最外セラミックシートa1の表面配線にその入出
力パッド(電極)がワイヤボンディングされた半導体素子
(半導体チップ)ｂと、半導体素子ｂが配置された側に設
けられ上記半導体素子ｂを保護するセラミック容器ｃと
でその主要部が構成されている。そして、セラミック基
板ａの他方の最外セラミックシートa3側に設けられた電
極ｄと半導体素子ｂの入出力パッド(電極)とはセラミッ
ク基板ａに設けられたヴィアｅや内層配線ｆを通じて結
線される。尚、図４中のｇは、セラミック容器タイプの
半導体素子ｂを図示外のマザーボード(プリント基板)に
接続させるためのはんだを示している。FIG. 4 shows a conventional ceramic container type, and FIG.
Indicates a flip chip type. That is, in the conventional ceramic container type, as shown in FIG. 4, ceramic sheets a1, a2, a3 provided with a wiring pattern are provided.
And a semiconductor element fixed to the outermost ceramic sheet a1 side of the ceramic substrate a and having its input / output pads (electrodes) wire-bonded to the surface wiring of the outermost ceramic sheet a1
(Semiconductor chip) b and a ceramic container c provided on the side where the semiconductor element b is disposed to protect the semiconductor element b constitute a main part thereof. The electrode d provided on the other outermost ceramic sheet a3 side of the ceramic substrate a and the input / output pad (electrode) of the semiconductor element b are connected via a via e provided on the ceramic substrate a and an inner layer wiring f. . Note that g in FIG. 4 indicates solder for connecting the ceramic container type semiconductor element b to a motherboard (printed board) not shown.

【０００５】他方、フリップチップタイプは、図５に示
すように配線パターンが設けられたセラミックシートa
1、a2、a3の積層体から成るセラミック基板ａと、この
セラミック基板ａにおける一方の最外セラミックシート
a1側にフリップチップ接合された半導体素子ｂと、この
半導体素子ｂと最外セラミックシートa1との隙間に注入
されたエポキシ等の樹脂ｈとでその主要部が構成されて
いる。そして、半導体素子ｂの入出力パッド(電極)と最
外セラミックシートa1の表面配線ｉとはバンプｊを介し
て接続されると共に、半導体素子ｂと最外セラミックシ
ートa1間には適度な隙間が形成されエポキシ等の樹脂ｈ
は毛管現象により容易に浸透して隙間を充填するためこ
の樹脂ｈにより半導体素子ｂは固定される。On the other hand, the flip-chip type is a ceramic sheet provided with a wiring pattern as shown in FIG.
A ceramic substrate a comprising a laminate of 1, a2 and a3, and one outermost ceramic sheet on the ceramic substrate a
The main part of the semiconductor element b is flip-chip bonded to the a1 side, and a resin h such as epoxy injected into a gap between the semiconductor element b and the outermost ceramic sheet a1. The input / output pads (electrodes) of the semiconductor element b and the surface wiring i of the outermost ceramic sheet a1 are connected via bumps j, and an appropriate gap is provided between the semiconductor element b and the outermost ceramic sheet a1. Formed resin such as epoxy
The semiconductor element b is fixed by the resin h because the resin h easily penetrates and fills the gap.

【０００６】そして、これ等半導体パッケージにおい
て、フリップチップタイプはセラミック容器タイプと比
較して軽量かつ小型、薄型であり、半導体素子ｂの背面
側が露出しているため熱放散性に優れると共に、半導体
素子ｂの入出力パッド(電極)と最外セラミックシートa1
の表面配線ｉとの接続長さが短いことから電気特性にも
優れている。また、上記最外セラミックシートa1の表面
配線ｉは半導体素子ｂの入出力パッドと同程度に微細で
あるが、この表面配線ｉは最外セラミックシートa3にグ
リッド状に配列された電極ｄ(図６参照)やはんだｇ、ヴ
ィアｅあるいは内部配線ｆを介して上記マザーボード
(プリント基板)に接続されることになる。すなわち、グ
リッド状に配列された電極ｄは、図６に示すように０．
５〜１．２５ｍｍの広い間隔を有するため、上記表面配
線ｉとマザーボード(プリント基板)との接続を容易にさ
せることができる。In these semiconductor packages, the flip chip type is lighter, smaller and thinner than the ceramic container type, and has excellent heat dissipation because the back side of the semiconductor element b is exposed. b input / output pad (electrode) and outermost ceramic sheet a1
Since the connection length with the surface wiring i is short, the electrical characteristics are also excellent. The surface wirings i of the outermost ceramic sheet a1 are as fine as the input / output pads of the semiconductor element b. However, the surface wirings i are arranged on the outermost ceramic sheet a3 in the form of electrodes d (FIG. 6), solder g, via e or internal wiring f.
(Printed circuit board). That is, as shown in FIG.
Because of the wide spacing of 5 to 1.25 mm, the connection between the surface wiring i and the motherboard (printed circuit board) can be facilitated.

【０００７】[0007]

【発明が解決しようとする課題】ところで、上記フリッ
プチップタイプにおいて半導体素子ｂと最外セラミック
シートa1との隙間に注入されたエポキシ等の樹脂ｈは１
５０〜１８０℃程度に加熱されて硬化するが、この加熱
硬化の際に上記半導体素子ｂと対向する領域内に存在す
るヴィアｅに内包されている空気が膨張し、ヴィアｅの
開口部から樹脂ｈ中に入り込んでボイド(void)を生じさ
せてしまう場合があつた。In the flip chip type, the resin h such as epoxy injected into the gap between the semiconductor element b and the outermost ceramic sheet a1 is 1
The resin is cured by being heated to about 50 to 180 ° C. At the time of the heating and curing, the air contained in the via e present in the region opposed to the semiconductor element b expands, and the resin enters through the opening of the via e. There was a case where a void was generated by entering the inside of h.

【０００８】そして、半導体素子ｂが搭載されたセラミ
ック基板ａは２３０〜２８０℃程度で上記はんだｇを熔
かしてマザーボード(プリント基板)に接続されるが、こ
の熱処理の際に樹脂ｈ中のボイド(void)が膨張して上記
樹脂ｈにクラックを生じさせたり半導体素子ｂにダメー
ジを与え易い問題を有していた。The ceramic substrate a on which the semiconductor element b is mounted is connected to a motherboard (printed circuit board) by melting the solder g at about 230 to 280 ° C. There is a problem that the void expands to cause cracks in the resin h or damage to the semiconductor element b.

【０００９】また、最外セラミックシートa1における上
記半導体素子ｂと対向する領域外の表面配線ｉは、図５
に示すように上述した樹脂ｈにより封止されず露出して
いるため、空気中の湿気あるいは結露、導電性の塵等に
より配線間においてショートし易い問題を有していた。The surface wiring i outside the region facing the semiconductor element b in the outermost ceramic sheet a1 is shown in FIG.
As shown in (2), since the wiring is exposed without being sealed by the above-mentioned resin h, there is a problem in that a short circuit easily occurs between wirings due to moisture in the air, dew condensation, conductive dust, or the like.

【００１０】本発明はこのような問題点に着目してなさ
れたもので、その第一の目的とするところは半導体素子
と最外セラミックシートとの隙間に注入される樹脂中に
ボイド(void)が発生し難い半導体素子搭載用セラミック
基板を提供することにあり、また、第二の目的とすると
ころは上記樹脂中にボイド(void)が発生し難いと共に半
導体素子と対向する領域外の表面配線がショートし難い
半導体素子搭載用セラミック基板を提供することにあ
る。The present invention has been made in view of such a problem. A first object of the present invention is to provide a method in which a resin is injected into a gap between a semiconductor element and an outermost ceramic sheet. Another object of the present invention is to provide a ceramic substrate for mounting a semiconductor element, in which voids are unlikely to be generated, and a second object is to prevent a void from being generated in the resin and to provide a surface wiring outside a region facing the semiconductor element. SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor substrate for mounting a semiconductor element, which is not easily short-circuited.

【００１１】[0011]

【課題を解決するための手段】すなわち、請求項１に係
る発明は、配線パターンが設けられた複数セラミックシ
ートの積層体により構成され、この積層体における一方
の最外セラミックシート側に半導体素子がフリップチッ
プ接合されると共に、半導体素子と最外セラミックシー
トとの隙間に注入された樹脂により半導体素子が固定さ
れる半導体素子搭載用セラミック基板を前提とし、上記
最外セラミックシートの半導体素子と対向する領域内に
おけるヴィアの開口部が薄膜のセラミック材で被覆され
ていることを特徴とし、また、請求項２に係る発明は、
請求項１記載の半導体素子搭載用セラミック基板を前提
とし、上記最外セラミックシートの半導体素子と対向す
る領域外の表面配線が薄膜のセラミック材で被覆されて
いることを特徴とし、また、請求項３に係る発明は、請
求項１または２記載の半導体素子搭載用セラミック基板
を前提とし、上記セラミック材の膜厚が３〜１５μｍに
設定されていることを特徴とするものである。That is, the invention according to claim 1 comprises a laminate of a plurality of ceramic sheets provided with a wiring pattern, and a semiconductor element is provided on one of the outermost ceramic sheets in the laminate. It is assumed that the semiconductor element is mounted on the ceramic substrate on which the semiconductor element is fixed by the resin injected into the gap between the semiconductor element and the outermost ceramic sheet while being flip-chip bonded. The opening of the via in the region is covered with a thin-film ceramic material, and the invention according to claim 2 is characterized in that:
The semiconductor substrate for mounting a semiconductor element according to claim 1, wherein a surface wiring of the outermost ceramic sheet outside a region facing the semiconductor element is covered with a thin-film ceramic material. The invention according to a third aspect is based on the ceramic substrate for mounting a semiconductor element according to the first or second aspect, wherein the thickness of the ceramic material is set to 3 to 15 μm.

【００１２】[0012]

【発明の実施の形態】以下、本発明の実施の形態につい
て図面を参照して詳細に説明する。Embodiments of the present invention will be described below in detail with reference to the drawings.

【００１３】図１は、本発明に係る半導体素子搭載用セ
ラミック基板の構成を示す概略断面図である。すなわ
ち、この半導体素子搭載用セラミック基板１０は、図１
に示すようにヴィア１や表面配線２が設けられた第一セ
ラミックグリーンシート(最外セラミックシート)１１、
ヴィア１や内層配線３が設けられた第二セラミックグリ
ーンシート１２、ヴィア１や内層配線、マザーボード側
電極４等が設けられた第三セラミックグリーンシート１
３から成るセラミックシート積層体１４と、これ等ヴィ
ア１内に充填された導体組成物(導体ペースト)１５と、
第一セラミックグリーンシート１１のヴィア１開口部と
表面配線２の一部を被覆するセラミック被膜２０とでそ
の主要部が構成されている。FIG. 1 is a schematic sectional view showing the structure of a ceramic substrate for mounting a semiconductor element according to the present invention. That is, the ceramic substrate 10 for mounting a semiconductor element is the same as that shown in FIG.
The first ceramic green sheet (outermost ceramic sheet) 11 provided with the via 1 and the surface wiring 2 as shown in FIG.
Second ceramic green sheet 12 provided with via 1 and inner layer wiring 3, third ceramic green sheet 1 provided with via 1 and inner layer wiring, motherboard-side electrode 4, and the like
3, a conductor composition (conductor paste) 15 filled in the vias 1;
The principal part of the first ceramic green sheet 11 is formed by the opening of the via 1 and the ceramic coating 20 covering a part of the surface wiring 2.

【００１４】尚、上記セラミック被膜２０は、この基板
１０に搭載される半導体素子の下部に位置する(すなわ
ち、半導体素子と対向する領域内の)ヴィア１開口部
と、半導体素子の周辺に露出する表面配線(すなわち、
半導体素子と対向する領域外の表面配線)２を被覆する
ためのものであるが、半導体素子の下部に位置する表面
配線２を被覆してもよい。但し、半導体素子の下部に位
置する表面配線２の内、半導体素子における入出力パッ
ドと接続される部位の表面配線２については被覆しては
ならない。これは、セラミック被膜の存在により表面配
線と半導体素子との電気的接続ができなくなるからであ
る。The ceramic coating 20 is located below the semiconductor element mounted on the substrate 10 (that is, in a region facing the semiconductor element) and is exposed at the periphery of the semiconductor element. Surface wiring (i.e.,
Although this is for covering the surface wiring 2 outside the region facing the semiconductor element, the surface wiring 2 located below the semiconductor element may be covered. However, among the surface wirings 2 located below the semiconductor element, the surface wiring 2 at a portion connected to the input / output pad in the semiconductor element must not be covered. This is because the presence of the ceramic coating makes it impossible to electrically connect the surface wiring and the semiconductor element.

【００１５】また、図２および図３はこの半導体素子搭
載用セラミック基板１０に半導体素子(半導体チップ)３
０が搭載されたフリップチップタイプの半導体パッケー
ジ１００を示している。尚、図２および図３中、４０は
第一セラミックグリーンシート(最外セラミックシート)
１１と半導体素子３０との隙間に充填されたエポキシ等
の樹脂、５０は第三セラミックグリーンシート１３のマ
ザーボード側電極４に設けられたはんだを示している。FIGS. 2 and 3 show a semiconductor element (semiconductor chip) 3 on this ceramic substrate 10 for mounting a semiconductor element.
0 shows a flip-chip type semiconductor package 100 on which the semiconductor package 100 is mounted. 2 and 3, reference numeral 40 denotes a first ceramic green sheet (outermost ceramic sheet).
A resin such as epoxy filled in a gap between the semiconductor device 11 and the semiconductor element 30, and a solder 50 is provided on the motherboard-side electrode 4 of the third ceramic green sheet 13.

【００１６】そして、本発明に係る半導体素子搭載用セ
ラミック基板１０においては、図２および図３に示すよ
うに上記半導体素子３０の下部に位置する(すなわち、
半導体素子と対向する領域内の)ヴィア１開口部がセラ
ミック被膜２０により被覆されているため、第一セラミ
ックグリーンシート(最外セラミックシート)１１と半導
体素子３０との隙間に充填されたエポキシ等樹脂４０の
加熱硬化の際、上記ヴィア１内に内包されている空気が
膨張してもこの空気がエポキシ等樹脂４０中に入り込む
ことがない。The semiconductor element mounting ceramic substrate 10 according to the present invention is located below the semiconductor element 30 as shown in FIGS.
Since the opening of the via 1 (in the region facing the semiconductor element) is covered with the ceramic coating 20, a resin such as epoxy filled in the gap between the first ceramic green sheet (outermost ceramic sheet) 11 and the semiconductor element 30 At the time of heating and curing of 40, even if the air contained in the via 1 expands, this air does not enter the resin 40 such as epoxy.

【００１７】従って、エポキシ等樹脂４０中におけるボ
イド(void)の発生が阻止されるため、はんだ５０を介し
て半導体素子３０が搭載されたセラミック基板１０をマ
ザーボードに接続する際、２３０〜２８０℃程度の加熱
処理にも拘わらず上記ボイド(void)に起因した樹脂４０
内のクラック発生を防止することが可能となり、かつ、
クラック等に起因した半導体素子３０の損傷をも防止す
ることが可能となる。Therefore, the generation of voids in the resin 40 such as epoxy is prevented, so that when the ceramic substrate 10 on which the semiconductor element 30 is mounted is connected to the motherboard via the solder 50, the temperature is about 230 to 280 ° C. Resin 40 caused by the voids despite the heat treatment of
Cracks in the interior can be prevented, and
It is also possible to prevent the semiconductor element 30 from being damaged due to cracks and the like.

【００１８】また、この半導体素子搭載用セラミック基
板１０においては、図２および図３に示すように半導体
素子の周辺に露出する表面配線(すなわち、半導体素子
と対向する領域外の表面配線)２もセラミック被膜２０
により被覆されていることから空気中の湿気あるいは結
露、導電性塵等の影響を阻止できるため、表面配線２間
におけるショートを確実に防止することも可能となる。Further, in the ceramic substrate 10 for mounting a semiconductor element, as shown in FIGS. 2 and 3, the surface wiring 2 exposed at the periphery of the semiconductor element (that is, the surface wiring outside the region facing the semiconductor element) 2 Ceramic coating 20
Since it is covered by the above, the influence of moisture or dew in the air, conductive dust and the like can be prevented, so that a short circuit between the surface wirings 2 can be surely prevented.

【００１９】ここで、セラミック基板１０を構成する材
料については特に限定されるものではなく、一般的なア
ルミナの他、ガラスセラミック、ムライト、コージェラ
イト等が例示される。Here, the material forming the ceramic substrate 10 is not particularly limited, and examples thereof include glass alumina, mullite, cordierite and the like in addition to general alumina.

【００２０】また、セラミック被膜２０の材質について
は上記セラミック基板１０の材質と同質のものが好まし
いが、特に同質に限定されるものではなく、十分に緻密
な膜に焼成されかつセラミック基板に反りやひずみを生
じさせないものなら任意である。尚、上述したように半
導体素子の下部に位置する表面配線２の内、半導体素子
における入出力パッドと接続される部位の表面配線２に
ついては被覆してはならないことから所定のパターンで
セラミック被膜２０を形成することを要する。The material of the ceramic coating 20 is preferably the same as the material of the ceramic substrate 10, but is not particularly limited to the same material, but is fired into a sufficiently dense film and warps the ceramic substrate. It is arbitrary as long as it does not cause distortion. As described above, among the surface wirings 2 located below the semiconductor element, the surface wiring 2 at a portion connected to the input / output pad in the semiconductor element must not be covered. Need to be formed.

【００２１】また、セラミック被膜の厚さについては基
本的には任意であるが、薄過ぎると上記ボイド(void)の
発生防止や表面配線の保護が不十分となり、反対に厚過
ぎると半導体素子とセラミック基板との隙間が狭くなっ
て樹脂注入の際に均一な浸透が困難となりかつ樹脂を注
入するのにセラミック被膜が邪魔になることがある。す
なわち、セラミック被膜の厚さについては３〜１５μｍ
の範囲に設定することが好ましい。The thickness of the ceramic coating is basically arbitrary. However, if the thickness is too small, the generation of the voids and the protection of the surface wiring will be insufficient. The gap with the ceramic substrate is narrowed, making it difficult to uniformly infiltrate the resin when injecting the resin, and the ceramic coating may hinder the resin injection. That is, the thickness of the ceramic coating is 3 to 15 μm.
Is preferably set in the range.

【００２２】また、セラミック被膜の形成方法について
も基本的に任意であるが、上記パターン形成および膜厚
制限を満たす上でスクリーン印刷の適用が好ましい。Although the method of forming the ceramic coating is basically arbitrary, it is preferable to apply screen printing in order to satisfy the above-mentioned pattern formation and film thickness restrictions.

【００２３】そして、本発明に係るセラミック基板は以
下のようにして製造される。The ceramic substrate according to the present invention is manufactured as follows.

【００２４】すなわち、従来の方法と同様にしてグリー
ンシート(第一セラミックグリーンシート１１)を形成
し、かつ、このグリーンシートに金型を用いてヴィア用
の孔を開設する。ヴィア１内には導体組成物(導体ペー
スト)１５を充填し、その後、スクリーン印刷により導
体ペーストを塗布して表面配線２を形成する。更に、セ
ラミックペーストをスクリーン印刷で塗布して半導体素
子の下部に位置するヴィア１開口部と半導体素子の周辺
に露出する表面配線２を被覆する。That is, a green sheet (first ceramic green sheet 11) is formed in the same manner as in the conventional method, and a hole for a via is formed in the green sheet using a mold. The via 1 is filled with a conductor composition (conductor paste) 15, and then the conductor paste is applied by screen printing to form the surface wiring 2. Further, a ceramic paste is applied by screen printing to cover the opening of the via 1 located below the semiconductor element and the surface wiring 2 exposed around the semiconductor element.

【００２５】次に、ヴィア１や内層配線３が設けられた
第二セラミックグリーンシート１２、ヴィア１や内層配
線、マザーボード側電極４等が設けられた第三セラミッ
クグリーンシート１３を作製し、かつ、第一セラミック
グリーンシート１１、第二セラミックグリーンシート１
２、第三セラミックグリーンシート１３の順で積層する
と共に、熱圧着して一体化し、従来法と同様の条件で焼
成することにより本発明に係る半導体素子搭載用セラミ
ック基板を製造することができ。Next, a second ceramic green sheet 12 provided with the via 1 and the inner layer wiring 3 and a third ceramic green sheet 13 provided with the via 1 and the inner layer wiring, the motherboard-side electrode 4 and the like are produced. First ceramic green sheet 11, Second ceramic green sheet 1
The ceramic substrate for mounting a semiconductor element according to the present invention can be manufactured by laminating in the order of the second and third ceramic green sheets 13, integrating by thermocompression bonding, and firing under the same conditions as in the conventional method.

【００２６】尚、この製造方法では、セラミック積層体
とセラミック被膜を同時に焼成しているが、セラミック
積層体をまず焼成した後、上記セラミック被膜を形成し
て再焼成する方法を採ってもよい。但し、コスト的には
同時焼成の方法が有利である。また、この実施の形態に
おいては、上記セラミック積層体が、第一セラミックグ
リーンシート１１、第二セラミックグリーンシート１２
および第三セラミックグリーンシート１３で構成されて
いるが、セラミック積層体は３層構成に限らず、もっと
多層にあるいはもっと少層にしてもよくその層数は任意
である。In this manufacturing method, the ceramic laminate and the ceramic coating are fired at the same time. However, a method may be employed in which the ceramic laminate is fired first, and then the ceramic coating is formed and fired again. However, the simultaneous firing method is advantageous in terms of cost. Further, in this embodiment, the ceramic laminate is composed of the first ceramic green sheet 11 and the second ceramic green sheet 12.
And the third ceramic green sheet 13. However, the ceramic laminate is not limited to the three-layer structure, but may have more or less layers, and the number of layers is arbitrary.

【００２７】[0027]

【実施例】以下、本発明の実施例について具体的に説明
する。Embodiments of the present invention will be specifically described below.

【００２８】まず、ガラス粉末６０重量％とＡｌ2Ｏ3粉
末４０重量％の混合物をブチラール樹脂が溶解されたア
ルコールとフタル酸ブチル混合溶液内に分散してスラリ
ーを調製し、このスラリーをドクターブレードを用いて
１５０μｍの厚さに形成してグリーンシートを作製し
た。First, a mixture of 60% by weight of glass powder and 40% by weight of Al 2 O 3 powder was dispersed in a mixed solution of alcohol in which butyral resin was dissolved and butyl phthalate to prepare a slurry. Was used to form a green sheet having a thickness of 150 μm.

【００２９】尚、ガラス粉末の構成は、１３重量％Ｃａ
Ｏ−３６重量％ＳｉＯ2−２６重量％ＺｎＯ−１５重量
％Ａｌ2Ｏ3−１０重量％Ｂ2Ｏ3である。The composition of the glass powder is 13% by weight Ca
O-36 wt% SiO 2 -26 wt% ZnO-15 wt% Al 2 O 3 -10 wt% B 2 O 3 .

【００３０】また、セラミック被膜形成用に、上記ガラ
ス粉末とＡｌ2Ｏ3粉末の混合物５０重量％を、５重量％
のエチルセルロースが含まれるターピネオール溶液５０
重量％に分散させたガラスペーストを準備した。For forming a ceramic film, 50% by weight of a mixture of the above glass powder and Al 2 O 3 powder was added to 5% by weight.
Terpineol solution 50 containing ethyl cellulose
A glass paste dispersed in weight% was prepared.

【００３１】次に、上記グリーンシートにヴィアホール
を形成し、かつ、ヴィア内にＡｇペーストを充填した
後、スクリーン印刷によりＡｇペーストを塗布して表面
配線と内層配線を各々の層に形成して第一セラミックグ
リーンシート、第二セラミックグリーンシートおよび第
三セラミックグリーンシートを得た。また、第一セラミ
ックグリーンシートにおいて半導体素子の下部に位置す
るヴィア開口部と半導体素子の周辺に露出する表面配線
には上記ガラスペーストをスクリーン印刷により塗布し
てセラミック被膜を形成した。Next, a via hole is formed in the green sheet, and after filling the via with an Ag paste, an Ag paste is applied by screen printing to form a surface wiring and an inner wiring in each layer. A first ceramic green sheet, a second ceramic green sheet and a third ceramic green sheet were obtained. Further, the glass paste was applied by screen printing to the via openings located below the semiconductor element and the surface wiring exposed around the semiconductor element in the first ceramic green sheet to form a ceramic coating.

【００３２】次に、第一セラミックグリーンシート、第
二セラミックグリーンシート、第三セラミックグリーン
シートの順で金型上に積層し、３００ｋｇ／ｃｍ2、８
０℃、５分の条件で加圧して一体化しセラミック積層体
を得た。次に、このセラミック積層体を空気気流中、５
００℃、２時間の条件で樹脂分を分解除去し、次いで８
５０℃まで毎分２℃の速度で昇温した後、１０分間保持
して焼成し実施例に係る半導体素子搭載用セラミック基
板を得た。尚、このセラミック基板のセラミック被膜
は、Ａｇ表面配線上に４μｍの厚さで形成されていた。[0032] Next, the first ceramic green sheet, the second ceramic green sheet, laminated on the mold in the order of the third ceramic green sheet, 300kg / cm 2, 8
It was integrated under pressure at 0 ° C. for 5 minutes to obtain a ceramic laminate. Next, the ceramic laminate was placed in an air stream for 5 minutes.
The resin content was decomposed and removed under the conditions of 00 ° C. for 2 hours, and then 8 hours.
The temperature was raised to 50 ° C. at a rate of 2 ° C./minute, and then held for 10 minutes and fired to obtain a ceramic substrate for mounting a semiconductor element according to the example. The ceramic coating of this ceramic substrate was formed on the Ag surface wiring with a thickness of 4 μm.

【００３３】次に、得られた実施例に係る半導体素子搭
載用セラミック基板上に半導体素子をフリップチップ実
装し、かつ、半導体素子とセラミック基板との隙間にエ
ポキシ樹脂を６０℃で注入した後、１５０℃、３０分間
で硬化させた。Next, the semiconductor element is flip-chip mounted on the semiconductor element mounting ceramic substrate according to the obtained embodiment, and epoxy resin is injected at 60 ° C. into a gap between the semiconductor element and the ceramic substrate. It was cured at 150 ° C. for 30 minutes.

【００３４】そして、半導体素子が搭載されたセラミッ
ク基板について超音波探傷法によりエポキシ樹脂中のボ
イド(void)の有無を調べたところ全く確認されなかっ
た。Then, when the presence or absence of voids in the epoxy resin was examined by ultrasonic flaw detection on the ceramic substrate on which the semiconductor element was mounted, none was confirmed.

【００３５】また、半導体素子が搭載されたセラミック
基板について、その半導体素子周辺の表面配線上に水を
滴下した後、１０Ｖを通電したところ、ショート等の異
常は確認されなかった。Further, with respect to the ceramic substrate on which the semiconductor element was mounted, water was dropped on the surface wiring around the semiconductor element, and after applying a voltage of 10 V, no abnormality such as a short circuit was confirmed.

【００３６】一方、セラミック被膜を形成しない点を除
き実施例と同様にして製造された比較例に係る半導体素
子搭載用セラミック基板について超音波探傷法によりエ
ポキシ樹脂中のボイド(void)の有無を調べたところ、ヴ
ィア開口部上にボイド(void)が確認された。また、同様
に半導体素子周辺の表面配線上に水を滴下した後、１０
Ｖを通電したところ、比較例に係る半導体素子搭載用セ
ラミック基板においては配線間ショートが確認された。On the other hand, the presence or absence of voids in the epoxy resin was examined by an ultrasonic flaw detection method for a ceramic substrate for mounting a semiconductor element according to a comparative example manufactured in the same manner as in the example except that no ceramic film was formed. As a result, voids were found on the via openings. Similarly, after water is dropped on the surface wiring around the semiconductor element,
When V was applied, a short circuit between wirings was confirmed in the ceramic substrate for mounting a semiconductor element according to the comparative example.

【００３７】[0037]

【発明の効果】請求項１、３記載の発明に係る半導体素
子搭載用セラミック基板によれば、最外セラミックシー
トの半導体素子と対向する領域内におけるヴィアの開口
部が薄膜のセラミック材で被覆されているため、最外セ
ラミックシートと搭載された半導体素子との隙間に充填
された樹脂の加熱硬化の際、上記ヴィア内に内包されて
いる空気が膨張してもこの空気が樹脂中に入り込むこと
がない。According to the ceramic substrate for mounting a semiconductor element according to the first and third aspects of the present invention, the opening of the via in the region of the outermost ceramic sheet facing the semiconductor element is covered with the thin ceramic material. Therefore, when the resin filled in the gap between the outermost ceramic sheet and the mounted semiconductor element is cured by heating, even if the air contained in the via expands, this air may enter the resin. There is no.

【００３８】従って、樹脂中におけるボイド(void)の発
生が阻止されるため、半導体素子が搭載されたセラミッ
ク基板をマザーボードに接続する際の加熱処理にも拘わ
らず上記ボイド(void)に起因した樹脂内のクラック発生
を防止することが可能となり、かつ、クラック等に起因
した半導体素子の損傷をも防止することが可能となる効
果を有する。Therefore, the generation of voids in the resin is prevented, so that the resin caused by the voids despite the heat treatment when the ceramic substrate on which the semiconductor element is mounted is connected to the motherboard. This has the effect that it is possible to prevent the occurrence of cracks in the inside, and also to prevent damage to the semiconductor element due to cracks and the like.

【００３９】また、請求項２、３記載の発明に係る半導
体素子搭載用セラミック基板によれば、最外セラミック
シートの半導体素子と対向する領域外の表面配線が薄膜
のセラミック材で被覆されていることから、空気中の湿
気あるいは結露、導電性塵等の影響を阻止できるため表
面配線間におけるショートを確実に防止できる効果を有
する。According to the ceramic substrate for mounting a semiconductor element according to the second and third aspects of the present invention, the surface wiring of the outermost ceramic sheet outside the region facing the semiconductor element is covered with the thin ceramic material. Therefore, the effects of moisture in the air, dew condensation, conductive dust, and the like can be prevented, so that short-circuiting between the surface wirings can be reliably prevented.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明に係る半導体素子搭載用セラミック基板
の構成を示す概略断面図。FIG. 1 is a schematic sectional view showing a configuration of a ceramic substrate for mounting a semiconductor element according to the present invention.

【図２】本発明に係る半導体素子搭載用セラミック基板
が適用された半導体パッケージの構成を示す概略断面
図。FIG. 2 is a schematic cross-sectional view showing a configuration of a semiconductor package to which the ceramic substrate for mounting a semiconductor element according to the present invention is applied.

【図３】図２に係る半導体パッケージの一部切り欠き概
略斜視図。FIG. 3 is a partially cut-away schematic perspective view of the semiconductor package according to FIG. 2;

【図４】従来例に係るセラミック容器タイプの半導体パ
ッケージの構成を示す概略断面図。FIG. 4 is a schematic sectional view showing a configuration of a ceramic container type semiconductor package according to a conventional example.

【図５】従来例に係るフリップチップタイプの半導体パ
ッケージの構成を示す概略断面図。FIG. 5 is a schematic sectional view showing a configuration of a flip-chip type semiconductor package according to a conventional example.

【図６】図５に係る半導体パッケージの一部切り欠き概
略底面斜視図。FIG. 6 is a partially cutaway schematic bottom perspective view of the semiconductor package according to FIG. 5;

【符号の説明】[Explanation of symbols]

１ ヴィア ２ 表面配線 ３ 内層配線 ４ マザーボード側電極 １０ 半導体素子搭載用セラミック基板 １１ 第一セラミックグリーンシート １２ 第二セラミックグリーンシート １３ 第三セラミックグリーンシート １４ セラミック積層体 １５ 導体組成物(導体ペースト) ２０ セラミック被膜 DESCRIPTION OF SYMBOLS 1 Via 2 Surface wiring 3 Inner layer wiring 4 Motherboard side electrode 10 Ceramic substrate for mounting a semiconductor element 11 First ceramic green sheet 12 Second ceramic green sheet 13 Third ceramic green sheet 14 Ceramic laminate 15 Conductor composition (conductor paste) 20 Ceramic coating

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ テーマコート゛(参考） Ｈ０５Ｋ 3/46 Ｈ０１Ｌ 23/14 Ｃ ──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme coat ゛ (Reference) H05K 3/46 H01L 23/14 C

Claims (3)

【特許請求の範囲】[Claims] 【請求項１】配線パターンが設けられた複数セラミック
シートの積層体により構成され、この積層体における一
方の最外セラミックシート側に半導体素子がフリップチ
ップ接合されると共に、半導体素子と最外セラミックシ
ートとの隙間に注入された樹脂により半導体素子が固定
される半導体素子搭載用セラミック基板において、 上記最外セラミックシートの半導体素子と対向する領域
内におけるヴィアの開口部が薄膜のセラミック材で被覆
されていることを特徴とする半導体素子搭載用セラミッ
ク基板。1. A semiconductor device comprising a laminate of a plurality of ceramic sheets provided with a wiring pattern, a semiconductor element being flip-chip bonded to one of the outermost ceramic sheets in the laminate, and a semiconductor element and an outermost ceramic sheet. In the semiconductor element mounting ceramic substrate in which the semiconductor element is fixed by the resin injected into the gap between the semiconductor element and the semiconductor element, the opening of the via in the region of the outermost ceramic sheet facing the semiconductor element is covered with a thin ceramic material. A ceramic substrate for mounting a semiconductor element. 【請求項２】上記最外セラミックシートの半導体素子と
対向する領域外の表面配線が薄膜のセラミック材で被覆
されていることを特徴とする請求項１記載の半導体素子
搭載用セラミック基板。2. The ceramic substrate for mounting a semiconductor element according to claim 1, wherein a surface wiring of the outermost ceramic sheet outside a region facing the semiconductor element is covered with a thin ceramic material. 【請求項３】上記セラミック材の膜厚が３〜１５μｍに
設定されていることを特徴とする請求項１または２記載
の半導体素子搭載用セラミック基板。3. The ceramic substrate for mounting a semiconductor element according to claim 1, wherein the thickness of said ceramic material is set to 3 to 15 μm.
JP11165192A 1999-06-11 1999-06-11 Semiconductor element mounting ceramic board Pending JP2000353769A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11165192A JP2000353769A (en) 1999-06-11 1999-06-11 Semiconductor element mounting ceramic board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11165192A JP2000353769A (en) 1999-06-11 1999-06-11 Semiconductor element mounting ceramic board

Publications (1)

Publication Number Publication Date
JP2000353769A true JP2000353769A (en) 2000-12-19

Family

ID=15807596

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11165192A Pending JP2000353769A (en) 1999-06-11 1999-06-11 Semiconductor element mounting ceramic board

Country Status (1)

Country Link
JP (1) JP2000353769A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100380649C (en) * 2001-02-01 2008-04-09 埃普科斯股份有限公司 Substrate for electric component and method for production thereof
KR101038891B1 (en) 2009-03-17 2011-06-02 삼성전기주식회사 Ceramic substrate and manufacturing method of the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100380649C (en) * 2001-02-01 2008-04-09 埃普科斯股份有限公司 Substrate for electric component and method for production thereof
KR101038891B1 (en) 2009-03-17 2011-06-02 삼성전기주식회사 Ceramic substrate and manufacturing method of the same

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