JP2000295052A - Amplifier circuit - Google Patents
Amplifier circuitInfo
- Publication number
- JP2000295052A JP2000295052A JP11097838A JP9783899A JP2000295052A JP 2000295052 A JP2000295052 A JP 2000295052A JP 11097838 A JP11097838 A JP 11097838A JP 9783899 A JP9783899 A JP 9783899A JP 2000295052 A JP2000295052 A JP 2000295052A
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- JP
- Japan
- Prior art keywords
- differential
- differential amplifier
- amplifier
- current
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、差動増幅回路、帰
還型増幅回路、インピーダンス変換回路のような増幅回
路に関するものである。[0001] 1. Field of the Invention [0002] The present invention relates to an amplifier circuit such as a differential amplifier circuit, a feedback amplifier circuit, and an impedance conversion circuit.
【０００２】[0002]
【従来の技術】従来、高利得の電圧増幅回路において
は、その電圧利得の安定化のために、抵抗を用いて出力
信号を入力側に負帰還することが一般に行われている。
図６は、抵抗により負帰還を行う反転増幅器の回路例を
示す。この回路では、電圧利得は抵抗の比Ｒ２／Ｒ１で
決定される。2. Description of the Related Art Conventionally, in a high-gain voltage amplifying circuit, in order to stabilize the voltage gain, generally, negative feedback of an output signal to an input side using a resistor is generally performed.
FIG. 6 shows a circuit example of an inverting amplifier that performs negative feedback by a resistor. In this circuit, the voltage gain is determined by the resistance ratio R2 / R1.
【０００３】[0003]
【発明が解決しようとする課題】ところで、増幅器にオ
フセットがあって出力が零点（入力電圧、基準電圧、出
力電圧が等しい）にない場合には、その差分の電圧が帰
還抵抗に印加されるため、帰還抵抗において電力消費が
発生し、増幅器の低消費電力化を妨げる。その消費電力
は、帰還網の抵抗値を増加することにより抑制できる
が、増幅器を集積回路化するような場合には占有面積が
増大し、また抵抗熱雑音の発生などの点から種々の制約
がある。また、差動増幅器や反転増幅器などの一般的な
構成では入力抵抗が低くなる不都合もある。When the amplifier has an offset and the output is not at the zero point (the input voltage, the reference voltage, and the output voltage are equal), the difference voltage is applied to the feedback resistor. In addition, power consumption occurs in the feedback resistor, which hinders reduction in power consumption of the amplifier. The power consumption can be suppressed by increasing the resistance value of the feedback network, but when the amplifier is integrated, the occupied area increases, and various restrictions are imposed due to the occurrence of resistance thermal noise. is there. Further, in a general configuration such as a differential amplifier and an inverting amplifier, there is a disadvantage that input resistance is reduced.
【０００４】そこで、本発明の目的は、上記の点に鑑
み、回路の安定化を損なうことなく消費電力の低減化、
低雑音化が図れる上に、集積回路化の場合には小型化、
低コスト化が図れるようにした増幅回路を提供すること
にある。In view of the above, an object of the present invention is to reduce power consumption without impairing circuit stability.
In addition to lowering noise, miniaturization,
An object of the present invention is to provide an amplifying circuit capable of reducing cost.
【０００５】[0005]
【課題を解決するための手段】上記課題を解決し、本発
明の目的を達成するために、請求項１に記載の発明は、
入力信号を差動増幅する第１差動増幅手段と、この第１
差動増幅手段の出力電流のうちの一部を分岐させ、この
分岐電流に基づいて前記第１差動増幅手段の動作を安定
化させる第２差動増幅手段とを備えたものである。Means for Solving the Problems In order to solve the above problems and achieve the object of the present invention, the invention according to claim 1 is
First differential amplifying means for differentially amplifying an input signal;
And a second differential amplifier for branching a part of the output current of the differential amplifier and stabilizing the operation of the first differential amplifier based on the branched current.
【０００６】このように請求項１に係る発明では、第１
差動増幅手段の出力電流のうちの一部を分岐させ、この
分岐電流に基づいて第１差動増幅手段の動作を安定化さ
せる第２差動増幅手段を備え、これは差動増幅手段のた
めに抵抗を使用せずに実現できる。このため、回路の安
定化を損なうことなく消費電力の低減化、低雑音化が図
れる上に、集積回路化した場合には小型化、低コスト化
できる各種の増幅回路が実現可能となる。Thus, in the invention according to claim 1, the first
A second differential amplifier for branching a part of the output current of the differential amplifier and stabilizing the operation of the first differential amplifier based on the branch current; Therefore, it can be realized without using a resistor. For this reason, power consumption can be reduced and noise can be reduced without impairing the stability of the circuit, and various integrated circuits that can be reduced in size and cost when integrated are realized.
【０００７】請求項２に記載の発明は、入力信号を差動
増幅する第１差動増幅部と、入力信号を差動増幅する第
２差動増幅部と、前記第１差動増幅部と前記第２差動増
幅部とからそれぞれ流れ込む電流の総和の電流を流す負
荷部と、この負荷部に流れる総和の負荷電流を電圧に変
換する電流・電圧変換部とを備えたものである。ここ
で、上記の第１差動増幅部は第１差動増幅器１や第１差
動増幅回路１１が対応し、第２差動増幅部は第２差動増
幅器２や第２差動増幅回路１３が対応し、負荷部はイン
ピーダンス５やトランジスタＭ２４、Ｍ２５が対応し、
電流・電圧変換部はバッファアンプ６などが対応する。According to a second aspect of the present invention, there is provided a first differential amplifying unit for differentially amplifying an input signal, a second differential amplifying unit for differentially amplifying an input signal, and the first differential amplifying unit. And a current-to-voltage converter for converting the total load current flowing through the load into a voltage. Here, the first differential amplifier corresponds to the first differential amplifier 1 or the first differential amplifier 11, and the second differential amplifier corresponds to the second differential amplifier 2 or the second differential amplifier. 13, the load section corresponds to the impedance 5 and the transistors M24 and M25,
The current / voltage converter corresponds to the buffer amplifier 6 and the like.
【０００８】請求項３に記載の発明は、請求項２に記載
の増幅回路において、前記第１差動増幅部と前記第２差
動増幅部とは、少なくともＭＯＳトランジスタの差動対
により構成したものである。請求項４に記載の発明は、
請求項２または請求項３に記載の増幅回路において、前
記第２差動増幅部の負荷トランジスタ対とカレントミラ
ーを構成するトランジスタ対を形成することで、前記第
１差動増幅部に流れる電流と、前記第２差動増幅部に流
れる電流を、共通の負荷回路で加算するようにしたもの
である。According to a third aspect of the present invention, in the amplifier circuit according to the second aspect, the first differential amplifying section and the second differential amplifying section are constituted by at least a differential pair of MOS transistors. Things. The invention described in claim 4 is
4. The amplifier circuit according to claim 2, wherein a current flowing through the first differential amplifier is formed by forming a transistor pair forming a current mirror with a load transistor pair of the second differential amplifier. 5. , The current flowing through the second differential amplifier is added by a common load circuit.
【０００９】請求項５に記載の発明は、請求項２、請求
項３、または請求項４に記載の増幅回路において、前記
電流・電圧変換部の出力を前記第２差動増幅部の負の入
力端子に帰還するとともにその正の入力端子に基準電圧
を印加し、前記第１差動増幅部の入力端子を差動入力と
し、この差動入力と前記電流・電圧変換部の出力との比
が、前記第１差動増幅部の入力トランジスタと前記第２
差動増幅部の入力トランジスタの電流駆動能力比により
設定できる帰還型増幅回路とするものである。According to a fifth aspect of the present invention, in the amplifier circuit according to the second, third, or fourth aspect, the output of the current / voltage converter is connected to the negative of the second differential amplifier. A feedback voltage is applied to the input terminal and a reference voltage is applied to the positive input terminal. The input terminal of the first differential amplifier is used as a differential input. Are connected to the input transistor of the first differential amplifying unit and the second transistor.
This is a feedback amplifier circuit that can be set by the current drive capability ratio of the input transistors of the differential amplifier.
【００１０】請求項６に記載の発明は、請求項５に記載
の増幅回路において、前記第１差動増幅部に対して、さ
らに任意の電流駆動能力を有する入力トランジスタを備
えた複数の入力差動増幅部を並列に有し、前記第１差動
増幅部および前記複数の入力差動増幅部のそれぞれの入
力トランジスタと前記第２差動増幅部の入力トランジス
タとの電流駆動能力比に応じて、複数の入力を加算して
増幅するようにしたものである。According to a sixth aspect of the present invention, in the amplifier circuit according to the fifth aspect, a plurality of input differential circuits further comprising an input transistor having an arbitrary current driving capability with respect to the first differential amplifier. A dynamic amplifying unit in parallel, and according to a current driving capability ratio between an input transistor of each of the first differential amplifying unit and the plurality of input differential amplifying units and an input transistor of the second differential amplifying unit. , A plurality of inputs are added and amplified.
【００１１】請求項７に記載の発明は、請求項５または
請求項６に記載の増幅回路において、前記第２差動増幅
部の正の入力端子に前記基準電圧に加え、さらにオフセ
ット補償電圧を加えるようにしたものである。請求項８
に記載の発明は、請求項２、請求項３、または請求項４
に記載の増幅回路において、前記電流・電圧変換部の出
力を前記第２差動増幅部の負の入力端子に帰還し、前記
第１差動増幅部の正負の２つの入力端子に基準電圧を印
加し、前記第２差動増幅部の正の入力端子に入力信号を
入力することによりインピーダンス変換回路とするもの
である。According to a seventh aspect of the present invention, in the amplifier circuit according to the fifth or sixth aspect, an offset compensation voltage is added to a positive input terminal of the second differential amplifier in addition to the reference voltage. It is intended to be added. Claim 8
The invention described in claim 2 is claim 2, claim 3, or claim 4.
Wherein the output of the current / voltage converter is fed back to a negative input terminal of the second differential amplifier, and a reference voltage is applied to two positive and negative input terminals of the first differential amplifier. And an input signal is input to a positive input terminal of the second differential amplifying section to form an impedance conversion circuit.
【００１２】このように請求項２〜請求項８に係る各発
明では、第１差動増幅部の動作を安定化する手段を第２
差動増幅部などで構成し、これは抵抗を含まずにＭＯＳ
トランジスタなどで実現できる。このため、回路の利得
などの安定化を損なうことなく消費電力の低減化、低雑
音化が図れる上に、集積回路化した場合には小型化、低
コスト化できる増幅回路が実現できる。As described above, in each of the inventions according to claims 2 to 8, means for stabilizing the operation of the first differential amplifying section is provided by the second
It consists of a differential amplifier, etc.
It can be realized by a transistor or the like. For this reason, it is possible to realize an amplifier circuit that can reduce power consumption and reduce noise without impairing stabilization of circuit gain and the like, and can be reduced in size and cost when integrated.
【００１３】[0013]
【発明の実施の形態】以下、本発明の実施の形態につい
て図面を参照して説明する。本発明の実施形態の増幅回
路の構成の概要について、図１のブロック図を参照して
説明する。この増幅回路は、図１に示すように、第１差
動増幅器（トランスコンダクタンスアンプ）１および第
２差動増幅器（トランスコンダクタンスアンプ）２から
なる電圧・電流変換器３と、加算器４と、インピーダン
ス５およびバッファアンプ６からなる電流・電圧変換器
７とから構成されている。Embodiments of the present invention will be described below with reference to the drawings. An outline of the configuration of the amplifier circuit according to the embodiment of the present invention will be described with reference to the block diagram of FIG. As shown in FIG. 1, this amplifying circuit includes a voltage / current converter 3 including a first differential amplifier (transconductance amplifier) 1 and a second differential amplifier (transconductance amplifier) 2, an adder 4, It comprises a current / voltage converter 7 comprising an impedance 5 and a buffer amplifier 6.
【００１４】第１差動増幅器１は、正負の入力端子を有
し入力信号の差動増幅を行うものである。第２差動増幅
器２は、正負の入力端子を有するとともに、加算器４に
供給する正負の電流を生成し、第１差動増幅器１の動作
を安定化させるものである。加算器４は、第１差動増幅
器１からの電流と、第２差動増幅器２からの電流の加算
を行うものである。電流・電圧変換器７は、加算器４か
らの出力電流をインピーダンス５とバッファアンプ６を
用いて電流・電圧変換を行うものである。The first differential amplifier 1 has positive and negative input terminals and performs differential amplification of an input signal. The second differential amplifier 2 has positive and negative input terminals, generates positive and negative currents to be supplied to the adder 4, and stabilizes the operation of the first differential amplifier 1. The adder 4 adds the current from the first differential amplifier 1 and the current from the second differential amplifier 2. The current / voltage converter 7 performs current / voltage conversion of the output current from the adder 4 using the impedance 5 and the buffer amplifier 6.
【００１５】このような構成から図１の増幅回路におい
て、第１差動増幅器１のトランスコンダクタンスをｇｍ
１とし、第２差動増幅器２のトランスコンダクタンスを
ｇｍ２とし、第１差動増幅器１の正負の入力端子の入力
電圧をＶｉｎ+ とＶｉｎ- とし、第２差動増幅器２の正
負の入力端子の入力電圧をＶｆ+ とＶｆ- とし、バッフ
ァアンプ６の出力電圧をＶｏｕｔとし、回路全体の電圧
利得をＡとすると、次の（１）式が成立する。 Ｖｏｕｔ＝Ａ〔ｇｍ１（Ｖｉｎ+ −Ｖｉｎ- ）＋ｇｍ２（Ｖｆ+ −Ｖｆ- ）〕 …（１） 次に、図１の増幅回路において、バッファアンプ６の出
力側と第２差動増幅器２の負の入力端子とを電気的に接
続すると、図２に示すような負帰還増幅回路を構成する
ことになる。With such a configuration, the transconductance of the first differential amplifier 1 in the amplifier circuit of FIG.
1, the transconductance of the second differential amplifier 2 is gm2, the input voltages of the positive and negative input terminals of the first differential amplifier 1 are Vin + and Vin −, and the positive and negative input terminals of the second differential amplifier 2 are the input voltage Vf + and Vf - and, the output voltage of the buffer amplifier 6 as Vout, the voltage gain of the overall circuit and a, the following (1) is established. Vout = A [gm1 (Vin + -Vin -) + gm2 (Vf + -Vf -) ] ... (1) Next, in the amplifier circuit of FIG. 1, the negative output side of the second differential amplifier 2 of the buffer amplifier 6 Is electrically connected to the input terminal of the negative feedback amplifier circuit, a negative feedback amplifier circuit as shown in FIG. 2 is formed.
【００１６】図２の負帰還増幅回路では、Ｖｏｕｔ＝Ｖ
ｆ- になるとともに、Ｖｆ+ ＝Ｖｒｅｆ（基準電圧）と
して使用する。また、回路全体の電圧利得Ａが十分に大
きいとすると、（１）式から次の（２）式が得られる。 Ｖｏｕｔ＝ｇｍ１／ｇｍ２（Ｖｉｎ+ −Ｖｉｎ- ）＋Ｖｒｅｆ…（２） 従って、図２の負帰還増幅回路では、（２）式から第１
差動増幅器の２つの入力に対して、その電圧利得が（ｇ
ｍ１／ｇｍ２）となる。In the negative feedback amplifier circuit of FIG. 2, Vout = V
f - together becomes, Vf + = used as Vref (reference voltage). If the voltage gain A of the entire circuit is sufficiently large, the following equation (2) is obtained from the equation (1). Vout = gm1 / gm2 (Vin + −Vin − ) + Vref (2) Therefore, in the negative feedback amplifier circuit of FIG.
For the two inputs of the differential amplifier, its voltage gain is (g
m1 / gm2).
【００１７】次に、図２の負帰還増幅回路においてＶｉ
ｎ- ＝Ｖｒｅｆとすると、入力Ｖｉｎ+ に対して、その
電圧利得が（ｇｍ１／ｇｍ２）となる非反転増幅器を構
成することになり、Ｖｉｎ+ ＝Ｖｒｅｆとすると入力Ｖ
ｉｎ- に対して、その電圧利得が−（ｇｍ１／ｇｍ２）
となる反転増幅器を構成することになる。次に、図１の
増幅回路において、バッファアンプ６の出力側と第２差
動増幅器２の負の入力端子とを電気的に接続し、第１差
動増幅器１の正負の入力端子に基準電圧Ｖｒｅｆをそれ
ぞれ印加し、第２差動増幅器２の正の入力端子に入力信
号を入力する場合には、図３に示すようなインピーダン
ス変換回路として機能することになる。Next, in the negative feedback amplifier circuit of FIG.
n - = When Vref, the input to the input Vin +, and the voltage gain could be formed into a non-inverting amplifier becomes (gm1 / gm2), Vin + = a Vref V
in - against, is the voltage gain - (gm1 / gm2)
Is formed. Next, in the amplifier circuit of FIG. 1, the output side of the buffer amplifier 6 and the negative input terminal of the second differential amplifier 2 are electrically connected, and the positive and negative input terminals of the first differential amplifier 1 are connected to a reference voltage. When Vref is applied and an input signal is input to the positive input terminal of the second differential amplifier 2, it functions as an impedance conversion circuit as shown in FIG.
【００１８】ここで、図２の回路において、第２差動増
幅器２の正の入力端子に上記の基準電圧に加えて、さら
にオフセット補償電圧を加えると、オフセット補償が行
える点で好ましい。ところで、図２に示す増幅回路は、
第１差動増幅器１が１つの場合であるが、図４に示すよ
うに、複数の第１差動増幅器１ａ、１ｂ、１ｃ…にする
ことができる。この増幅回路は、図４に示すように、複
数の第１差動増幅器１ａ、１ｂ、１ｃ…を備えて複数の
入力とし、その各出力を加算器４に供給するようにした
ものであり、その他の部分の構成は図２と同様であるの
で、その説明は省略する。Here, in the circuit of FIG. 2, it is preferable to add an offset compensation voltage to the positive input terminal of the second differential amplifier 2 in addition to the above-mentioned reference voltage, since offset compensation can be performed. By the way, the amplifier circuit shown in FIG.
Although there is a single first differential amplifier 1, as shown in FIG. 4, a plurality of first differential amplifiers 1a, 1b, 1c... As shown in FIG. 4, the amplifying circuit includes a plurality of first differential amplifiers 1a, 1b, 1c,..., A plurality of inputs, and the respective outputs are supplied to an adder 4. The configuration of the other parts is the same as that of FIG. 2, and the description thereof is omitted.
【００１９】この図４の増幅回路の出力電圧Ｖｏｕｔ
は、第１差動増幅器１ａ、１ｂ、１ｃ…の各トランスコ
ンダクタンスをｇｍ１ａ、ｇｍ１ｂ、ｇｍ１ｃ…とし、
第２差動増幅器２のトランスコンダクタンスをｇｍ２と
し、第１差動増幅器１ａ、１ｂ、１ｃ…の正負の入力端
子の入力電圧をＶｉｎ１ａ+ 、Ｖｉｎ１ｂ+ 、Ｖｉｎ１
ｃ+ …と、Ｖｉｎ１ａ- 、Ｖｉｎ１ｂ- 、Ｖｉｎ１ｃ-
…とすると、次の（４）式が成立する。The output voltage Vout of the amplifier circuit shown in FIG.
, The transconductances of the first differential amplifiers 1a, 1b, 1c... Are gm1a, gm1b, gm1c.
The transconductance of the second differential amplifier 2 is gm2, and the input voltages of the positive and negative input terminals of the first differential amplifiers 1a, 1b, 1c... Are Vin1a + , Vin1b + , Vin1
c + …, Vin1a − , Vin1b − , Vin1c −
Then, the following equation (4) is established.
【００２０】 Ｖｏｕｔ＝ｇｍ１ａ／ｇｍ２（Ｖｉｎ１ａ+ −Ｖｉｎ１ａ- ） ＋ｇｍ１ｂ／ｇｍ２（Ｖｉｎ１ｂ+ −Ｖｉｎ１ｂ- ） ＋ｇｍ１ｃ／ｇｍ２（Ｖｉｎ１ｃ+ −Ｖｉｎ１ｃ- ） ＋… …（４） この（４）式からわかるように、この回路は複数の入力
に重みを持たせることができ、その各入力を加算して出
力できることがわかる。Vout = gm1a / gm2 (Vin1a + −Vin1a − ) + gm1b / gm2 (Vin1b + −Vin1b − ) + gm1c / gm2 (Vin1c + −Vin1c − ) +... (4) As can be seen from equation (4). It can be seen that this circuit can give weight to a plurality of inputs, and can add and output each input.
【００２１】次に、本発明の実施形態の増幅回路を反転
増幅回路に適用した場合の構成の詳細について、図５の
回路図を参照して説明する。この反転増幅回路は、図５
に示すように、入力信号を差動増幅する第１差動増幅回
路１１と、加算回路１２と、この加算回路１２に供給す
る電流を生成し、第１差動増幅回路１１の動作の安定化
を図る電流帰還用の第２差動増幅回路１３と、第１差動
増幅回路１１の出力電流に基づいてＡＢ級の電圧増幅を
行うＡＢ級増幅回路１４と、これら各回路を動作させる
ためのバイアス電流や電圧を供給するバイアス回路とを
少なくとも備えている。Next, details of the configuration when the amplifier circuit of the embodiment of the present invention is applied to an inverting amplifier circuit will be described with reference to the circuit diagram of FIG. This inverting amplifier circuit is shown in FIG.
As shown in (1), a first differential amplifier circuit 11 for differentially amplifying an input signal, an adder circuit 12, and a current supplied to the adder circuit 12 are generated to stabilize the operation of the first differential amplifier circuit 11. And a class AB amplifier 14 for performing class AB voltage amplification based on the output current of the first differential amplifier 11, and a circuit for operating these circuits. A bias circuit for supplying a bias current or a voltage.
【００２２】まずバイアス回路について説明すると、バ
イアス回路は、図５に示すように、それぞれダイオード
接続された４つのＭＯＳトランジスタＭ１、Ｍ２、Ｍ
３、Ｍ１５が、電源の端子間に直列に接続されることに
より構成されている。そして、ＭＯＳトランジスタＭ１
のゲート電圧がＭＯＳトランジスタＭ４、Ｍ７、Ｍ１２
の各ゲートに供給され、第２差動増幅回路１３、第１差
動増幅回路１１、ＡＢ級増幅回路１４に所定のバイアス
電流を供給するようになっている。First, the bias circuit will be described. As shown in FIG. 5, the bias circuit includes four diode-connected MOS transistors M1, M2, M
3, M15 are connected in series between the terminals of the power supply. Then, the MOS transistor M1
Gate voltage of the MOS transistors M4, M7, M12
And a predetermined bias current is supplied to the second differential amplifier circuit 13, the first differential amplifier circuit 11, and the class AB amplifier circuit 14.
【００２３】また、ＭＯＳトランジスタＭ２のゲート電
圧が、第１差動増幅回路１１のカスケードトランジスタ
Ｍ１０、Ｍ１１の各ゲートにバイアス電圧として供給さ
れるようになっている。さらに、ＭＯＳトランジスタ１
５のゲート電圧が、第２差動増幅回路１３のレベルシフ
タを構成するトランジスタＭ１７、Ｍ２３の各ゲートに
バイアス電圧として供給されるようになっている。The gate voltage of the MOS transistor M2 is supplied to each gate of the cascade transistors M10 and M11 of the first differential amplifier circuit 11 as a bias voltage. Further, MOS transistor 1
5 is supplied as a bias voltage to the gates of the transistors M17 and M23 constituting the level shifter of the second differential amplifier circuit 13.
【００２４】第１差動増幅回路１１は、図５に示すよう
に、差動対を構成する２つの入力信号用のＰＭＯＳトラ
ンジスタＭ８、Ｍ９と、このＰＭＯＳトランジスタＭ
８、Ｍ９の差動対に定電流を供給する定電流源用のＰＭ
ＯＳトランジスタＭ７と、ＰＭＯＳトランジスタＭ８、
Ｍ９の出力側に直列に接続され、所定の直流バイアス電
圧がゲートに印加されているＰＭＯＳトランジスタＭ１
０、Ｍ１１と、カレントミラー回路を構成するＮＭＯＳ
トランジスタＭ２４、Ｍ２５とを備えている。また、差
動対を構成するＰＭＯＳトランジスタＭ８とＭ９の各ゲ
ートは、負の入力端子２１と正の入力端子２２にそれぞ
れ接続されている。As shown in FIG. 5, the first differential amplifier circuit 11 includes two input signal PMOS transistors M8 and M9 forming a differential pair, and the PMOS transistors M8 and M9.
8, PM for a constant current source that supplies a constant current to the differential pair of M9
An OS transistor M7, a PMOS transistor M8,
A PMOS transistor M1 connected in series to the output side of M9 and having a predetermined DC bias voltage applied to its gate.
0, M11 and NMOS constituting a current mirror circuit
Transistors M24 and M25. The gates of the PMOS transistors M8 and M9 forming the differential pair are connected to a negative input terminal 21 and a positive input terminal 22, respectively.
【００２５】第２差動増幅回路１３は、図５に示すよう
に、差動対を構成する２つの帰還入力用のＰＭＯＳトラ
ンジスタＭ５、Ｍ６と、このＰＭＯＳトランジスタＭ
５、Ｍ６の差動対に定電流を供給する定電流源用のＰＭ
ＯＳトランジスタＭ４とを少なくとも備えている。ＰＭ
ＯＳトランジスタＭ５のドレインには、その負荷になる
とともに第１差動増幅回路１１のＰＭＯＳトランジスタ
Ｍ８に流れる電流に対して負の加算を行う、ＮＭＯＳト
ランジスタＭ１８とＭ１９とからなる第１カレントミラ
ー回路が接続されている。また、同様に、ＰＭＯＳトラ
ンジスタＭ６のドレインには、その負荷になるとともに
第１差動増幅回路のＰＭＯＳトランジスタＭ９に流れる
電流に対して負の加算を行う、ＮＭＯＳトランジスタＭ
２０とＭ２１とからなる第２カレントミラー回路が接続
されている。このような第１カレントミラー回路と第２
カレントミラー回路とにより、加算回路１２が構成され
ている。As shown in FIG. 5, the second differential amplifier circuit 13 includes two feedback input PMOS transistors M5 and M6 forming a differential pair, and the PMOS transistors M5 and M6.
5, PM for a constant current source that supplies a constant current to the differential pair of M6
At least an OS transistor M4. PM
At the drain of the OS transistor M5, a first current mirror circuit including NMOS transistors M18 and M19, which serves as a load and performs a negative addition to the current flowing through the PMOS transistor M8 of the first differential amplifier circuit 11, is provided. It is connected. Similarly, the drain of the PMOS transistor M6 is connected to the NMOS transistor M that performs a negative addition to the current flowing through the PMOS transistor M9 of the first differential amplifier circuit while being a load.
A second current mirror circuit composed of 20 and M21 is connected. The first current mirror circuit and the second
The addition circuit 12 is configured by the current mirror circuit.
【００２６】差動対を構成する一方のＰＭＯＳトランジ
スタＭ５のゲートには、ＮＭＯＳトランジスタＭ１６、
Ｍ１７で構成されるレベルシフタを介して信号が入力さ
れるようになっている。また、その他方のＰＭＯＳトラ
ンジスタＭ６のゲートには、ＮＭＯＳトランジスタＭ２
２、Ｍ２３で構成されるレベルシフタを介して信号が入
力されるようになっている。そして、ＮＭＯＳトランジ
スタ１６のゲートが正の入力端子２３に接続され、ＮＭ
ＯＳトランジスタＭ２２のゲートが負の入力端子２４に
接続され、これら両入力端子２３、２４が第２差動増幅
回路１３の入力端子を構成している。The gate of one PMOS transistor M5 forming a differential pair is connected to the NMOS transistor M16,
A signal is input via a level shifter including M17. The gate of the other PMOS transistor M6 is connected to the NMOS transistor M2.
2. A signal is input via a level shifter composed of M23. Then, the gate of the NMOS transistor 16 is connected to the positive input terminal 23, and NM
The gate of the OS transistor M22 is connected to the negative input terminal 24, and these two input terminals 23, 24 constitute the input terminals of the second differential amplifier circuit 13.
【００２７】正の入力端子２３には、基準電圧Ｖｒｅｆ
が入力されるが、この基準電圧ＶｒｅｆはＭＯＳトラン
ジスタＭ１６のしきい値分だけ負側にシフトされてＭＯ
ＳトランジスタＭ５のゲートに入力される。また、負の
入力端子２４には、ＡＢ級増幅回路１４の出力端子２５
からの出力電圧Ｖｏｕｔが入力されるが、この出力電圧
Ｖｏｕｔは、ＭＯＳトランジスタＭ２２のしきい値分だ
け負側にシフトされてＭＯＳトランジスタＭ５のゲート
に入力される。The positive input terminal 23 has a reference voltage Vref
However, the reference voltage Vref is shifted to the negative side by the threshold value of the MOS transistor M16, and
Input to the gate of S transistor M5. The negative input terminal 24 is connected to the output terminal 25 of the class AB amplifier circuit 14.
Is output, the output voltage Vout is shifted to the negative side by the threshold value of the MOS transistor M22 and input to the gate of the MOS transistor M5.
【００２８】第２差動増幅回路１３の入力用のＭＯＳト
ランジスタＭ５、Ｍ６の相互コンダクタンスｇｍを相当
に下げた場合には、電流源のＭＯＳトランジスタＭ４の
ドレイン電圧が上がり、非飽和領域に入りやすくなり動
作が不安定になる。そこで、レベルシフタであるＭＯＳ
トランジスタＭ１６、Ｍ２２により、第２差動増幅回路
１３の入力電圧を下げ、電流源のＭＯＳトランジスタＭ
４のドレイン電圧が下げて、非飽和領域で動作すること
を抑制するようにしている。When the transconductance gm of the input MOS transistors M5 and M6 of the second differential amplifier circuit 13 is considerably reduced, the drain voltage of the current source MOS transistor M4 rises and tends to enter an unsaturated region. Operation becomes unstable. Then, MOS which is a level shifter
The input voltage of the second differential amplifier circuit 13 is reduced by the transistors M16 and M22, and the current source MOS transistor M
4, the drain voltage is lowered to suppress the operation in the unsaturated region.
【００２９】ＡＢ級増幅回路１４は、図５に示すよう
に、レベルシフタを構成する２つのＮＭＯＳトランジス
タＭ１２、Ｍ１３と、第１差動増幅回路１１の出力電圧
をＡＢ級増幅するＰＭＯＳトランジスタＭ１４およびＮ
ＭＯＳトランジスタＭ２６とから構成されている。次
に、このような構成からなるこの実施形態にかかる反転
増幅回路の動作について説明する。As shown in FIG. 5, the class AB amplifier circuit 14 comprises two NMOS transistors M12 and M13 forming a level shifter, and PMOS transistors M14 and N which amplify the output voltage of the first differential amplifier circuit 11 in class AB.
And a MOS transistor M26. Next, the operation of the inverting amplifier circuit according to this embodiment having such a configuration will be described.
【００３０】いま、第１差動増幅回路１１の正の入力端
子２２に基準電圧を印加した状態で、その負の入力端子
２１に入力電圧が印加すると、その印加直後は入力用の
ＭＯＳトランジスタＭ８、Ｍ９の出力電流は不平衡にな
る。その不平衡により出力電圧が変動し、それは第２差
動増幅回路１３へ入力される。その結果、加算回路１２
へ第２差動増幅回路１３から流れ込む電流が変化し、不
平衡が打ち消されたところで回路の動作が安定する。When an input voltage is applied to the negative input terminal 21 while a reference voltage is applied to the positive input terminal 22 of the first differential amplifier circuit 11, immediately after the application, the input MOS transistor M8 , M9 become unbalanced. The output voltage fluctuates due to the imbalance, and is input to the second differential amplifier circuit 13. As a result, the addition circuit 12
The current flowing from the second differential amplifier circuit 13 changes, and the operation of the circuit is stabilized when the imbalance is canceled.
【００３１】すなわち、例えば第１差動増幅回路１１の
入力トランジスタＭ８、Ｍ９の電流駆動能力を、第２差
動増幅回路１３の入力トランジスタＭ５、Ｍ６の電流駆
動能力の５０倍とすると、第１差動増幅回路１１の入力
電圧に対して第２差動増幅回路１３に約５０倍の入力電
圧が加わったときに、回路の動作が安定し、回路全体の
電圧利得は約５０倍となる。That is, for example, assuming that the current driving capability of the input transistors M8 and M9 of the first differential amplifier circuit 11 is 50 times the current driving capability of the input transistors M5 and M6 of the second differential amplifier circuit 13, the first When an input voltage that is about 50 times the input voltage of the differential amplifier circuit 11 is applied to the second differential amplifier circuit 13, the operation of the circuit is stabilized, and the voltage gain of the entire circuit becomes about 50 times.
【００３２】第１差動増幅回路１１のカスケードトラン
ジスタＭ１０、Ｍ１１は、各ゲートがバイアス電源によ
り固定されているため、ゲート接地回路として働き、Ｍ
ＯＳトランジスタＭ２４、Ｍ２５を負荷として電圧増幅
する。すなわち、第１差動増幅回路１１の入力トランジ
スタＭ８、Ｍ９の出力電流と、第２差動増幅回路１３の
入力トランジスタＭ５、Ｍ６の出力電流の差分の電流を
電圧に変換する。Each of the cascade transistors M10 and M11 of the first differential amplifier circuit 11 functions as a grounded gate circuit because each gate is fixed by a bias power supply.
The voltage is amplified using the OS transistors M24 and M25 as loads. That is, the difference between the output currents of the input transistors M8 and M9 of the first differential amplifier circuit 11 and the output currents of the input transistors M5 and M6 of the second differential amplifier circuit 13 is converted into a voltage.
【００３３】ここで、加算回路１２を構成するＭＯＳト
ランジスタＭ１７、Ｍ１８と、ＭＯＳトランジスタＭ２
０、Ｍ２１とはそれぞれカレントミラー回路を構成する
ので、第１差動増幅回路１１のＭＯＳトランジスタＭ
８、Ｍ９の各出力電流は、第２差動増幅回路１３のＭＯ
ＳトランジスタＭ５、Ｍ６の各出力電流から負の加算を
したものとなる。Here, the MOS transistors M17 and M18 forming the addition circuit 12 and the MOS transistor M2
0 and M21, respectively, constitute a current mirror circuit, so that the MOS transistors M of the first differential amplifier circuit 11
8 and M9 are output from the MO of the second differential amplifier circuit 13.
This is obtained by adding a negative addition from each output current of the S transistors M5 and M6.
【００３４】換言すれば、この図５の回路では、第１差
動増幅回路１１のＭＯＳトランジスタＭ８、Ｍ９の各出
力電流と、第２差動増幅回路１３のＭＯＳトランジスタ
Ｍ５、Ｍ６の各出力電流との総和の電流が、第１差動増
幅回路１１の負荷であるＭＯＳトランジスタＭ２４、Ｍ
２５に流れることになる。図５の回路は、その外部接続
の変更などにより上記のように反転増幅回路として機能
するが、この反転増幅回路の他に、非反転増幅回路、差
動増幅回路、およびインピーダンス変換回路として機能
させることができるので、これについて以下に説明す
る。In other words, in the circuit of FIG. 5, each output current of the MOS transistors M8 and M9 of the first differential amplifier circuit 11 and each output current of the MOS transistors M5 and M6 of the second differential amplifier circuit 13 And the MOS transistors M24 and M24, which are loads of the first differential amplifier circuit 11,
25. The circuit in FIG. 5 functions as an inverting amplifier circuit as described above due to a change in external connection and the like, but in addition to this inverting amplifier circuit, functions as a non-inverting amplifier circuit, a differential amplifier circuit, and an impedance conversion circuit. This will be described below.
【００３５】まず、非反転増幅回路の場合には、ＡＢ級
増幅回路１４の出力端子と第２差動増幅回路１３の負の
入力端子２４を接続するとともにその正の入力端子２３
に基準電圧を印加し、さらに、第１差動増幅回路１１の
負の入力端子２１に基準電圧を印加するとともにその正
の入力端子２２に入力電圧を印加する。また、差動増幅
回路の場合には、ＡＢ級増幅回路１４の出力端子と第２
差動増幅回路１３の負の入力端子２４を接続するととも
にその正の入力端子２３に基準電圧を印加し、第１差動
増幅回路１１の正負の入力端子２１、２２間に入力信号
を加えることになる。First, in the case of a non-inverting amplifier circuit, the output terminal of the class AB amplifier circuit 14 is connected to the negative input terminal 24 of the second differential amplifier circuit 13 and its positive input terminal 23 is connected.
, A reference voltage is applied to the negative input terminal 21 of the first differential amplifier circuit 11 and an input voltage is applied to the positive input terminal 22 of the first differential amplifier circuit 11. In the case of a differential amplifier circuit, the output terminal of the class AB amplifier circuit 14 is connected to the second terminal.
Connecting the negative input terminal 24 of the differential amplifier circuit 13 and applying a reference voltage to the positive input terminal 23 thereof, and applying an input signal between the positive and negative input terminals 21 and 22 of the first differential amplifier circuit 11. become.
【００３６】さらに、インピーダンス変換回路の場合に
は、第１差動増幅回路１１の正負の入力端子２１、２２
にそれぞれに基準電圧を印加し、第２差動増幅回路１３
のＡＢ級増幅回路１４の出力端子と第２差動増幅回路１
３の負の入力端子２４を接続するとともにその正の入力
端子２３に入力信号を供給することになる。以上説明し
たように、この実施形態にかかる増幅回路では、利得の
安定化のために、抵抗を使用することなくＭＯＳトラン
ジスタからなる第２差動増幅回路１３などを使用するよ
うにし、その利得の決定には第１差動増幅回路１１のＭ
ＯＳトランジスタと第２差動増幅回路１３のＭＯＳトラ
ンジスタの性能比を用いるようにした。このため、増幅
回路としての機能を損なうことなく消費電力の低減化、
低雑音化、小型化などを実現できる。Further, in the case of an impedance conversion circuit, the positive and negative input terminals 21 and 22 of the first differential amplifier circuit 11
, A reference voltage is applied to each of the second differential amplifier circuits 13
Output terminal of the class AB amplifier circuit 14 and the second differential amplifier circuit 1
3 and the input signal is supplied to the positive input terminal 23. As described above, in the amplifier circuit according to this embodiment, the second differential amplifier circuit 13 including a MOS transistor is used without using a resistor to stabilize the gain. The determination of M of the first differential amplifier circuit 11
The performance ratio between the OS transistor and the MOS transistor of the second differential amplifier circuit 13 is used. Therefore, power consumption can be reduced without impairing the function as an amplifier circuit,
Low noise and small size can be realized.
【００３７】また、上記のＭＯＳトランジスタの性能比
は、抵抗素子と同様に相対的な寸法比で決定されるた
め、集積回路化する場合には、従来の集積回路技術を活
用することができる。さらに、この実施形態にかかる増
幅回路では、第２差動増幅回路１３の入力用のＭＯＳト
ランジスタのゲートにＡＢ級増幅回路１４の出力電圧を
帰還するようにしたので、帰還ループの入力インピーダ
ンスがほぼ無限大になる。また、そのＭＯＳトランジス
タの差動対は小電流で動作可能であるので、帰還増幅回
路全体として動作時の消費電力を極力減少できる。Further, since the performance ratio of the MOS transistor is determined by the relative dimensional ratio as in the case of the resistance element, the conventional integrated circuit technology can be used when forming an integrated circuit. Further, in the amplifier circuit according to the present embodiment, the output voltage of the class AB amplifier circuit 14 is fed back to the gate of the input MOS transistor of the second differential amplifier circuit 13, so that the input impedance of the feedback loop is substantially reduced. Becomes infinite. Further, since the differential pair of the MOS transistors can operate with a small current, the power consumption during operation of the entire feedback amplifier circuit can be reduced as much as possible.
【００３８】また、この実施形態では、回路構成を変更
することなく、入力抵抗が無限大の反転増幅回路、非反
転増幅回路、差動増幅回路、およびインピーダンス変換
回路を形成できる。さらに、この実施形態にかかる増幅
回路では、雑音源となる抵抗を含まないため、回路全体
の雑音レベルを低減してＳ／Ｎ比を向上できる。In this embodiment, an inverting amplifier, a non-inverting amplifier, a differential amplifier, and an impedance converter having an infinite input resistance can be formed without changing the circuit configuration. Further, since the amplifier circuit according to this embodiment does not include a resistor serving as a noise source, the noise level of the entire circuit can be reduced and the S / N ratio can be improved.
【００３９】また、この実施形態にかかる増幅回路をモ
ノリシック集積回路で実現する場合には、抵抗で帰還を
実現する場合に比べ、帰還に係る部分の面積占有率を大
幅に減少でき、もって小型化、低コスト化が図れる。Further, when the amplifier circuit according to this embodiment is realized by a monolithic integrated circuit, the area occupancy of the portion related to the feedback can be greatly reduced as compared with the case where the feedback is realized by a resistor. Cost can be reduced.
【００４０】[0040]
【発明の効果】以上述べたように、請求項１に係る発明
では、第１差動増幅手段の出力電流のうちの一部を分岐
させ、この分岐電流に基づいて第１差動増幅手段の動作
を安定化させる第２差動増幅手段を備え、これは差動増
幅手段のために抵抗を使用せずに実現できるので、回路
の安定化を損なうことなく消費電力の低減化、低雑音化
が図れる上に、集積回路化した場合には小型化、低コス
ト化できる増幅回路が実現可能となる。As described above, according to the first aspect of the present invention, a part of the output current of the first differential amplifier is branched, and the output current of the first differential amplifier is divided based on the branch current. A second differential amplifying means for stabilizing the operation is provided, which can be realized without using a resistor for the differential amplifying means, so that the power consumption can be reduced without lowering the stability of the circuit and the noise can be reduced. In addition, when integrated circuits are used, an amplifier circuit that can be reduced in size and cost can be realized.
【００４１】また、請求項２〜請求項８に係る各発明で
は、第１差動増幅部の動作を安定化する手段を第２差動
増幅部などで構成し、これは抵抗を含まずにＭＯＳトラ
ンジスタなどで実現できるので、回路の利得などの安定
化を損なうことなく消費電力の低減化、低雑音化が図れ
る上に、集積回路化した場合には小型化、低コスト化で
きる増幅回路が実現できる。In each of the second to eighth aspects of the present invention, the means for stabilizing the operation of the first differential amplifying unit is constituted by the second differential amplifying unit or the like, which does not include a resistor. Since it can be realized with MOS transistors, it is possible to reduce power consumption and reduce noise without compromising the stability of circuit gain and the like. realizable.
【図１】本発明の実施形態の増幅回路の構成の概略を説
明するブロック図である。FIG. 1 is a block diagram illustrating a schematic configuration of an amplifier circuit according to an embodiment of the present invention.
【図２】負帰還増幅回路とした場合の構成を示すブロッ
ク図である。FIG. 2 is a block diagram showing a configuration in the case of a negative feedback amplifier circuit.
【図３】インピーダンス変換回路とした場合のブロック
図である。FIG. 3 is a block diagram when an impedance conversion circuit is used.
【図４】複数入力とした場合の負帰還増幅回路の構成を
示すブロック図である。FIG. 4 is a block diagram illustrating a configuration of a negative feedback amplifier circuit when a plurality of inputs are provided.
【図５】本発明の実施形態の増幅回路の詳細な構成を示
す回路図である。FIG. 5 is a circuit diagram showing a detailed configuration of an amplifier circuit according to the embodiment of the present invention.
【図６】従来回路の説明図である。FIG. 6 is an explanatory diagram of a conventional circuit.
１ 第１差動増幅器 ２ 第２差動増幅器 ３ 電圧・電流変換回路 ４ 加算器 ５ インピーダンス ６ バッファアンプ ７ 電流・電圧変換回路 １１ 第１差動増幅回路 １２ 加算回路 １３ 第２差動増幅回路 １４ ＡＢ級増幅回路 REFERENCE SIGNS LIST 1 first differential amplifier 2 second differential amplifier 3 voltage-current conversion circuit 4 adder 5 impedance 6 buffer amplifier 7 current-voltage conversion circuit 11 first differential amplification circuit 12 addition circuit 13 second differential amplification circuit 14 AB class amplifier circuit
───────────────────────────────────────────────────── フロントページの続き (72)発明者 福本 博文 静岡県富士市鮫島２番地の１ 旭化成工業 株式会社内 Ｆターム(参考） 5J066 AA01 AA12 CA36 CA41 CA92 FA15 HA10 HA17 HA25 HA29 KA00 KA02 KA03 KA09 KA26 KA27 MA11 ND01 ND14 ND22 ND23 PD02 TA01 5J092 AA01 AA12 CA36 CA41 CA92 FA15 HA10 HA17 HA25 HA29 KA00 KA02 KA03 KA09 KA26 KA27 MA11 TA01 ────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hirofumi Fukumoto 2nd Samejima, Fuji-shi, Shizuoka Prefecture MA11 ND01 ND14 ND22 ND23 PD02 TA01 5J092 AA01 AA12 CA36 CA41 CA92 FA15 HA10 HA17 HA25 HA29 KA00 KA02 KA03 KA09 KA26 KA27 MA11 TA01
Claims (8)
段と、 この第１差動増幅手段の出力電流のうちの一部を分岐さ
せ、この分岐電流に基づいて前記第１差動増幅手段の動
作を安定化させる第２差動増幅手段と、 を備えたことを特徴とする増幅回路。A first differential amplifying means for differentially amplifying an input signal; a part of an output current of the first differential amplifying means being branched; and the first differential amplifying means based on the branched current. And a second differential amplifier for stabilizing the operation of the amplifier.
と、 入力信号を差動増幅する第２差動増幅部と、 前記第１差動増幅部と前記第２差動増幅部とからそれぞ
れ流れ込む電流の総和の電流を流す負荷部と、 この負荷部に流れる総和の負荷電流を電圧に変換する電
流・電圧変換部と、 を備えたことを特徴とする増幅回路。2. A first differential amplifier for differentially amplifying an input signal, a second differential amplifier for differentially amplifying an input signal, the first differential amplifier and the second differential amplifier. An amplifier circuit, comprising: a load section that flows a total current of currents flowing from the first and second sections; and a current / voltage conversion section that converts a total load current flowing in the load section into a voltage.
部とは、少なくともＭＯＳトランジスタの差動対により
構成されていることを特徴とする請求項２に記載の増幅
回路。3. The amplifier circuit according to claim 2, wherein said first differential amplifier and said second differential amplifier are configured by at least a differential pair of MOS transistors.
対とカレントミラーを構成するトランジスタ対を形成す
ることで、前記第１差動増幅部に流れる電流と、前記第
２差動増幅部に流れる電流を、共通の負荷回路で加算す
るようにしたことを特徴とする請求項２または請求項３
に記載の増幅回路。4. A current flowing in the first differential amplifier and a current flowing in the second differential amplifier are formed by forming a transistor pair forming a current mirror with a load transistor pair of the second differential amplifier. The current flowing is added by a common load circuit.
2. The amplifier circuit according to 1.
差動増幅部の負の入力端子に帰還するとともにその正の
入力端子に基準電圧を印加し、 前記第１差動増幅部の入力端子を差動入力とし、 この差動入力と前記電流・電圧変換部の出力との比が、
前記第１差動増幅部の入力トランジスタと前記第２差動
増幅部の入力トランジスタの電流駆動能力比により設定
できる帰還型増幅回路とすること特徴とする請求項２、
請求項３、または請求項４に記載の増幅回路。5. The output of the current / voltage converter is connected to the second
The feedback to the negative input terminal of the differential amplifying unit and the application of a reference voltage to the positive input terminal thereof, the input terminal of the first differential amplifying unit as a differential input, the differential input and the current / voltage The ratio with the output of the converter is
3. A feedback amplifier circuit that can be set by a current driving capability ratio between an input transistor of the first differential amplifier and an input transistor of the second differential amplifier.
The amplifier circuit according to claim 3 or claim 4.
意の電流駆動能力を有する入力トランジスタを備えた複
数の入力差動増幅部を並列に有し、前記第１差動増幅部
および前記複数の入力差動増幅部のそれぞれの入力トラ
ンジスタと前記第２差動増幅部の入力トランジスタとの
電流駆動能力比に応じて、複数の入力を加算して増幅す
ることを特徴とする請求項５に記載の増幅回路。6. A plurality of input differential amplifiers each including an input transistor having an arbitrary current driving capability are provided in parallel with the first differential amplifier, and the first differential amplifier and the first differential amplifier are connected to each other. 2. The method according to claim 1, wherein a plurality of inputs are added and amplified according to a current drive capability ratio between each input transistor of the plurality of input differential amplifiers and an input transistor of the second differential amplifier. 6. The amplifier circuit according to 5.
記基準電圧に加え、さらにオフセット補償電圧を加える
ようにしたことを特徴とする請求項５または請求項６に
記載の増幅回路。7. The amplifier circuit according to claim 5, wherein an offset compensation voltage is further applied to a positive input terminal of the second differential amplifier in addition to the reference voltage. .
差動増幅部の負の入力端子に帰還し、前記第１差動増幅
部の正負の２つの入力端子に基準電圧を印加し、前記第
２差動増幅部の正の入力端子に入力信号を入力すること
によりインピーダンス変換回路とすることを特徴とする
請求項２、請求項３、または請求項４に記載の増幅回
路。8. The output of the current / voltage converter is connected to the second
The signal is fed back to the negative input terminal of the differential amplifier, a reference voltage is applied to two positive and negative input terminals of the first differential amplifier, and an input signal is applied to the positive input terminal of the second differential amplifier. 5. The amplifier circuit according to claim 2, wherein the input circuit forms an impedance conversion circuit by inputting.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP09783899A JP4255564B2 (en) | 1999-04-05 | 1999-04-05 | Amplifier circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP09783899A JP4255564B2 (en) | 1999-04-05 | 1999-04-05 | Amplifier circuit |
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| Publication Number | Publication Date |
|---|---|
| JP2000295052A true JP2000295052A (en) | 2000-10-20 |
| JP4255564B2 JP4255564B2 (en) | 2009-04-15 |
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|---|---|---|---|
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007110460A (en) * | 2005-10-14 | 2007-04-26 | National Institute Of Advanced Industrial & Technology | Cmos amplifier using four-terminal double insulation gate field transistor, multi-input cmos amplifier, high gain multi-input cmos amplifier, high gain highly stable multi-input cmos amplifier, and multi-input cmos differential amplifier |
| KR100748721B1 (en) | 2006-06-15 | 2007-08-13 | 삼성전자주식회사 | Push-pull amplifier and method for low noise amplification |
| JP2008503167A (en) * | 2004-06-15 | 2008-01-31 | アナログ デバイセス インコーポレーテッド | Current mode instrumentation amplifier |
| JP2011071752A (en) * | 2009-09-25 | 2011-04-07 | Seiko Instruments Inc | Operational amplifier |
| JP2013242296A (en) * | 2012-04-27 | 2013-12-05 | Seiko Instruments Inc | Sensor device |
| JP2014023149A (en) * | 2012-07-19 | 2014-02-03 | Honeywell Internatl Inc | Multiple-output-transconductance-amplifier-based instrumentation amplifier |
-
1999
- 1999-04-05 JP JP09783899A patent/JP4255564B2/en not_active Expired - Lifetime
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008503167A (en) * | 2004-06-15 | 2008-01-31 | アナログ デバイセス インコーポレーテッド | Current mode instrumentation amplifier |
| JP2007110460A (en) * | 2005-10-14 | 2007-04-26 | National Institute Of Advanced Industrial & Technology | Cmos amplifier using four-terminal double insulation gate field transistor, multi-input cmos amplifier, high gain multi-input cmos amplifier, high gain highly stable multi-input cmos amplifier, and multi-input cmos differential amplifier |
| KR100748721B1 (en) | 2006-06-15 | 2007-08-13 | 삼성전자주식회사 | Push-pull amplifier and method for low noise amplification |
| JP2011071752A (en) * | 2009-09-25 | 2011-04-07 | Seiko Instruments Inc | Operational amplifier |
| JP2013242296A (en) * | 2012-04-27 | 2013-12-05 | Seiko Instruments Inc | Sensor device |
| JP2014023149A (en) * | 2012-07-19 | 2014-02-03 | Honeywell Internatl Inc | Multiple-output-transconductance-amplifier-based instrumentation amplifier |
Also Published As
| Publication number | Publication date |
|---|---|
| JP4255564B2 (en) | 2009-04-15 |
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