JP2000269162A - Member for integrated circuit and its manufacture - Google Patents
Member for integrated circuit and its manufactureInfo
- Publication number
- JP2000269162A JP2000269162A JP15423299A JP15423299A JP2000269162A JP 2000269162 A JP2000269162 A JP 2000269162A JP 15423299 A JP15423299 A JP 15423299A JP 15423299 A JP15423299 A JP 15423299A JP 2000269162 A JP2000269162 A JP 2000269162A
- Authority
- JP
- Japan
- Prior art keywords
- metal
- alloy
- electrode
- wiring material
- less
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明はエレクトロニクス用
の集積回路、トランジスタおよびＦＥＴに関する．The present invention relates to integrated circuits, transistors and FETs for electronics.
【０００２】[0002]
【従来の技術】従来、コンタクト電極又は配線材には、
アルミニウム（Ａｌ）又はその合金が使われていた．そ
して、ゲート電極にはポリシリコンが使用されていた。
マイクロプロセッサ又はメモリ等の高速化、微細化を可
能にする次世代材料として銅が注目されているが、Ｓｉ
及びＳｉＯ２表面に対する付着力が弱く、均一な膜を形
成するのは困難であった。更に２００℃で以上になる
と、金属がシリコン中に拡散してしまい、電極あるいは
配線材としては使用できない。半導体素子の使用時の内
部温度は通常１７０〜１８０℃に達するのでどんなに低
温プロセスが発達しても２００℃以上での拡散を防止し
なければならない。2. Description of the Related Art Conventionally, a contact electrode or a wiring material includes:
Aluminum (Al) or its alloy was used. Then, polysilicon was used for the gate electrode.
Copper is attracting attention as a next-generation material that enables high-speed and miniaturization of microprocessors or memories.
And the adhesion to the SiO 2 surface was weak, making it difficult to form a uniform film. If the temperature exceeds 200 ° C., the metal diffuses into silicon and cannot be used as an electrode or a wiring material. Since the internal temperature of a semiconductor device during use usually reaches 170 to 180 ° C., diffusion at 200 ° C. or higher must be prevented even if a low-temperature process develops.
【０００３】[0003]
【発明が解決しようとする課題】従って、本発明の目的
は銅に金属を少量添加した銅合金薄膜により、銅のＳｉ
あるいはＳｉＯ２表面への付着力を向上させ、２００℃
以上での拡散を禁止し、更に平滑性を著しく改善するこ
とにより、次世代のオーミック電極、配線材及びゲート
電極、コンデンサー電極及びインダクタを開発すること
である。SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a copper alloy thin film obtained by adding a small amount of metal to copper to form copper Si.
Alternatively, the adhesion to the SiO 2 surface is improved,
The object of the present invention is to develop next-generation ohmic electrodes, wiring materials and gate electrodes, capacitor electrodes, and inductors by inhibiting the above diffusion and further improving the smoothness significantly.
【０００４】[0004]
【発明を解決するための手段】本発明は主成分がＣｕ金
属であって少なくともＮｉ金属を含む合金からなること
を特徴とする、オーミック電極、配線材、ゲート電極、
インダクタ又はコンデンサ電極及びそれらの製造方法に
より達成された。According to the present invention, there is provided an ohmic electrode, a wiring material, a gate electrode, comprising an alloy containing Cu metal as a main component and containing at least Ni metal.
This has been achieved by inductor or capacitor electrodes and their manufacturing method.
【０００５】[0005]
【発明の実施の形態】本発明に使用される合金は主成分
がＣｕ金属であって少なくともＮｉ金属を含む合金から
なる。好ましくは、合金が５０重量％未満のＮｉ金属を
含有し、更に好ましくは、０．１重量％以上４０重量％
以下のＮｉ金属を含有する。最も好ましくは３重量％以
上３５重量％以下Ｎｉ金属を含有する。又、０．１重量
％以上３重量％以下であっても十分作用効果を発生する
ことが可能である．合金の厚みは５μｍ未満である。好
ましくは３ｎｍ以上１μｍ以下であり、更に好ましくは
５ｎｍ以上０．５μｍ以下である。ＳｉＯ２以外の保護
膜（絶縁体）としてはＳｉ３Ｎ４、ＳｉＯｘＮｙ、Ａｌ
Ｎ、ＧａＮ、ＰＳＧ膜、Ａｌ２Ｏ３等をあげることがで
きる．Ｓｉ以外のコンタクト対象（半導体）としてはＩ
ＩＩ−Ｖ族化合物半導体、ＩＩ−ＶＩ族化合物半導体、
ＩＶ−ＶＩ族化合物半導体、酸化物半導体、磁性半導
体、有機物半導体などの化合物半導体（代表例：ＧａＡ
ｓ、ＡｌＧａＡｓ、ＩｎＰ、ＡｌＡｓ、ＩｎＳｂ）、Ｇ
ｅ等をあげることができる。Ｎｉ−Ｃｕ合金に添加する
金属としてはＡｕ、Ａｇ、Ａｌ、Ｚｎ、Ｍｎ、Ｆｅ、Ｃ
ｒ、Ｔｉ、Ｍｏ、Ｚｒ、Ｍｇ、ＳｉまたはＰｔが好まし
い．添加量は５重量％以下、好ましくは０．０１％重量
以上３％重量以下の範囲で添加することが好ましい。BEST MODE FOR CARRYING OUT THE INVENTION The alloy used in the present invention is an alloy whose main component is Cu metal and contains at least Ni metal. Preferably, the alloy contains less than 50 wt% Ni metal, more preferably 0.1 wt% or more and 40 wt%.
Contains the following Ni metal. Most preferably, Ni metal is contained in an amount of 3% by weight or more and 35% by weight or less. Further, even when the content is 0.1% by weight or more and 3% by weight or less, a sufficient effect can be obtained. The thickness of the alloy is less than 5 μm. Preferably it is 3 nm or more and 1 μm or less, more preferably 5 nm or more and 0.5 μm or less. As a protective film (insulator) other than SiO 2 , Si 3 N 4 , SiOxNy, Al
N, GaN, PSG film, Al 2 O 3 and the like can be mentioned. The contact target (semiconductor) other than Si is I
II-V compound semiconductors, II-VI compound semiconductors,
Compound semiconductors such as IV-VI compound semiconductors, oxide semiconductors, magnetic semiconductors, and organic semiconductors (typical examples: GaAs
s, AlGaAs, InP, AlAs, InSb), G
e and the like. Au, Ag, Al, Zn, Mn, Fe, C as metals to be added to the Ni-Cu alloy
r, Ti, Mo, Zr, Mg, Si or Pt are preferred. The amount of addition is preferably 5% by weight or less, more preferably 0.01% to 3% by weight.
【０００６】合金薄膜の展開はＣＶＤ又はスパッタリン
グにより実施するのが好ましい。金属薄膜を使用する場
合、絶縁膜であるＳｉＯ２あるいは基板であるＳｉ表面
に対する付着力が重要である。付着力は一般的に膜構成
原子とのマイクロ的な相互作用によるから、膜の付着形
成法、基板の種類とその前処理法（洗剤処理、化学的洗
浄、有機溶剤洗浄、超音波洗浄、イオン衝撃など）ある
いは後熱処理法によって変化する。薄膜の展開後、熱処
理することも好ましい。そのときの温度は好ましくは３
５０℃以下である。[0006] The development of the alloy thin film is preferably carried out by CVD or sputtering. When a metal thin film is used, its adhesion to SiO 2 as an insulating film or Si surface as a substrate is important. Since the adhesive force is generally based on micro-interactions with the atoms constituting the film, the film formation method, the type of substrate and its pretreatment method (detergent treatment, chemical cleaning, organic solvent cleaning, ultrasonic cleaning, ion cleaning) Impact, etc.) or post heat treatment. After the development of the thin film, it is also preferable to perform a heat treatment. The temperature at that time is preferably 3
50 ° C. or less.
【０００７】付着力は引っかき試験法により測定でき
る。例えば、半径０．０３〜０．０４５ｍｍの剛体球に
種々の荷重をかけてガラス面上の金属膜を引っかくこと
により評価することができる。この場合付着力は引っか
き操作で膜が剥離する時の臨界荷重で表される。[0007] The adhesive force can be measured by a scratch test method. For example, it can be evaluated by applying various loads to a hard sphere having a radius of 0.03 to 0.045 mm and scratching a metal film on a glass surface. In this case, the adhesive force is represented by a critical load when the film is peeled off by a scratching operation.
【０００８】基本的には銅を電極あるいは配線材として
使用するには薄膜の付着力、平滑性及び２００℃での拡
散を改善しなければならないが、銅より付着性の強い金
属を添加することが考えられる。一般的に、Ｓｉ単結晶
上に展開される金属薄膜はランダムに堆積するのではな
くＳｉ結晶の配列の支配を受ける。このため凸凹が生ず
ることは純銅では避けられない。又、熱により拡散する
物質を止めることは出来ない。そのためＳｉ、ＳｉＯ２
中に予め固溶限界以上のＣｕ金属を染み込ませておく
か、他の物質にＣｕ金属を溶かしＣｕ金属を留まらせる
ことが必要である。Basically, in order to use copper as an electrode or wiring material, it is necessary to improve the adhesion, smoothness, and diffusion at 200 ° C. of a thin film. Can be considered. Generally, a metal thin film developed on a Si single crystal is not randomly deposited but is governed by the arrangement of Si crystals. For this reason, the occurrence of irregularities cannot be avoided with pure copper. Also, it is impossible to stop substances that diffuse by heat. Therefore, Si, SiO 2
It is necessary to infiltrate Cu metal in excess of the solid solution limit in advance, or to dissolve Cu metal in other substances to allow the Cu metal to remain.
【０００９】[0009]
【実施例】以下に本発明を具体例をあげ更に詳しく説明
するが、本発明の範囲はこれに限定されるものではな
い。合金薄膜の展開にはＲＦスパッタリング装置ＪＥＣ
−ＳＰ３６０Ｒ（日本電子）を用いた。添加する材料の
小片をターゲットに載せ、その全体での占有面積を変え
て組成比を変化せしめた。次に、合金膜（５重量％のＮ
ｉ金属含有）を展開したウェハを１０−７ｔｏｒｒの真
空中で１時間熱処理した。加熱温度はそれぞれ２００
℃、３００℃、４００℃である。出来あがったサンプル
を走査型電子顕微鏡（日本電子のＪＳＭ−５６００）及
びオージェ分析装置（日本電子のＪＡＭＰ−７８００）
により分析評価した。２００℃、３００℃及び４００℃
でサイクル１０〜サイクル１５の場合についていわゆる
デプスプロファイルを測定した結果、Ｃｕのは下記の通
りであった。EXAMPLES The present invention will be described in more detail with reference to specific examples, but the scope of the present invention is not limited thereto. RF sputtering system JEC for the development of alloy thin films
-SP360R (JEOL) was used. A small piece of the material to be added was placed on a target, and the composition ratio was changed by changing the area occupied by the whole. Next, an alloy film (5% by weight of N
The wafer developed with i metal) was heat-treated for 1 hour in a vacuum of 10 −7 torr. Heating temperature is 200
℃, 300 ℃, 400 ℃. Scanning electron microscope (JEOL JSM-5600) and Auger analyzer (JEOL JAMP-7800)
The analysis was evaluated by 200 ° C, 300 ° C and 400 ° C
As a result of measuring a so-called depth profile in the case of cycle 10 to cycle 15, the content of Cu was as follows.
【００１０】 [0010]
【００１１】上記の結果は意外にも２００℃以上であっ
ても室温と同様合金の基板中への拡散は殆どないことを
示している。ＳｉＯ２の場合も同様の結果が得られた。
一方、Ｃｕの場合、２００℃でも拡散していることが確
認された。The above results show that the alloy hardly diffuses into the substrate even at 200 ° C. or higher, as at room temperature. Similar results were obtained with SiO 2 .
On the other hand, it was confirmed that Cu was diffused even at 200 ° C.
【００１２】次いで、合金のＮｉ添加量を変えて厚みが
０．１μｍの配線材を作製し、付着力、拡散及び平滑性
を測定した。その結果を◎、○、△ 及び×の評価項目
で以下に示す。◎はきわめて良好、○は良好△は可及び
×は不可であることを示す。Next, a wiring material having a thickness of 0.1 μm was prepared by changing the amount of Ni added to the alloy, and the adhesion, diffusion and smoothness were measured. The results are shown below in the evaluation items of ◎, △, Δ and ×. ◎ indicates extremely good, は indicates good, △ indicates acceptable, and × indicates impossible.
【００１３】 [0013]
【００１４】上記の結果より本発明の合金膜の付着力、
拡散及び平滑性、とくに付着力がきわめて良好であるこ
とを示した。その結果、Ｃｕ−Ｎｉ合金によるオーミッ
ク電極はＳｉ（とくにｐ型Ｓｉ）とのコンタクトが良好
であり、ｐ型Ｓｉに対するＳｃｈｏｔｔｋｙバリアの高
さはＡｌの８０％程度で、従来のＡｌ電極よりも優れて
いることが明らかとなった。又、Ｃｕ−Ｎｉ合金配線材
は、Ｃｕ並みの低抵抗であり、許容電流密度がＡｌの１
０倍以上あるため、従来用いられるＡｌ配線材の３分の
１〜５分の１という配線幅を可能にした。また更に、Ｃ
ｕ−Ｎｉ合金ゲート電極は、従来のポリシリコン電極よ
りはるかに低抵抗であり、従来の集積回路の３００倍以
上の高速化が実現された。From the above results, the adhesive force of the alloy film of the present invention,
It showed very good diffusion and smoothness, especially adhesion. As a result, the ohmic electrode made of the Cu—Ni alloy has good contact with Si (particularly p-type Si), and the height of the Schottky barrier to p-type Si is about 80% of Al, which is superior to the conventional Al electrode. It became clear that. Further, the Cu—Ni alloy wiring material has a low resistance equivalent to Cu and an allowable current density of 1
Since it is 0 times or more, a wiring width of 1/3 to 1/5 of the conventionally used Al wiring material is made possible. Furthermore, C
The u-Ni alloy gate electrode has a much lower resistance than the conventional polysilicon electrode, and achieves a speedup of 300 times or more that of the conventional integrated circuit.
【００１５】[0015]
【発明の効果】本発明により、ニッケル等の金属を少量
添加したＣｕ−Ｎｉ合金薄膜により、ＳｉあるいはＳｉ
Ｏ２表面への付着力が向上し、２００℃以上での金属原
子の拡散が防止された。更に平滑性が著しく改善され、
次世代のオーミック電極、配線材、ゲート電極、コンデ
ンサー電極及びインダクタとしての実用化を可能にし
た。According to the present invention, a Cu—Ni alloy thin film to which a small amount of a metal such as nickel is added can form Si or Si.
The adhesion to the O 2 surface was improved, and diffusion of metal atoms at 200 ° C. or higher was prevented. Furthermore, the smoothness is significantly improved,
This has enabled the practical use of next-generation ohmic electrodes, wiring materials, gate electrodes, capacitor electrodes, and inductors.
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ テーマコート゛(参考） Ｈ０１Ｌ 29/78 Ｈ０１Ｌ 27/04 Ｃ // Ｃ２２Ｆ 1/00 ６６１ Ｌ ６９１ 29/78 ３０１Ｇ ──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme coat ゛ (Reference) H01L 29/78 H01L 27/04 C // C22F 1/00 661 L 691 29/78 301G
Claims (10)
ｉ金属を含む合金からなることを特徴とする、オーミッ
ク電極、配線材、ゲート電極、インダクタ又はコンデン
サ電極。1. The method according to claim 1, wherein the main component is Cu metal and at least N
An ohmic electrode, a wiring material, a gate electrode, an inductor or a capacitor electrode, comprising an alloy containing i metal.
有することを特徴とする、請求項１に記載の、オーミッ
ク電極、配線材、ゲート電極、インダクタ又はコンデン
サ電極。2. The ohmic electrode, wiring material, gate electrode, inductor or capacitor electrode according to claim 1, wherein the alloy contains less than 50% by weight of Ni metal.
金属を含有することを特徴とする請求項１又は請求項２
に記載の、オーミック電極、、配線材、ゲート電極、イ
ンダクタ又はコンデンサ電極。3. Ni not less than 0.1% by weight and not more than 40% by weight.
3. The method according to claim 1, further comprising a metal.
4. The ohmic electrode, wiring material, gate electrode, inductor or capacitor electrode according to item 1.
を含有することを特徴とする請求項１〜請求項３に記載
のオーミック電極、配線材、ゲート電極、インダクタ又
はコンデンサ電極。4. The ohmic electrode, a wiring material, a gate electrode, an inductor or a capacitor electrode according to claim 1, further comprising 3% by weight or more and 35% by weight or less of Ni metal.
する請求項１〜請求項４に記載の配線材又はゲート電
極。5. The wiring material or the gate electrode according to claim 1, wherein the insulating film is SiO 2 .
の結晶であることをを特徴とする請求項１〜請求項４に
記載オーミック電極、。6. An n-type or p-type Si contact object.
The ohmic electrode according to claim 1, wherein the ohmic electrode is a crystal.
特徴とする請求項１〜請求項６に記載の、オーミック電
極、配線材、ゲート電極、インダクタ又はコンデンサ電
極。7. The ohmic electrode, wiring material, gate electrode, inductor or capacitor electrode according to claim 1, wherein the thickness of the alloy is less than 5 μm.
とを特徴とする請求項７に記載の、オーミック電極、配
線材、ゲート電極、インダクタ又はコンデンサ電極。8. The ohmic electrode, wiring material, gate electrode, inductor or capacitor electrode according to claim 7, wherein the thickness is 3 nm or more and 1 μm or less.
ることを特徴とする請求項８に記載の、オーミック電
極、配線材、ゲート電極、インダクタ又はコンデンサ電
極。9. The ohmic electrode, wiring material, gate electrode, inductor or capacitor electrode according to claim 8, wherein the thickness is 5 nm or more and 0.5 μm or less.
ングにより実施することを特徴とする、請求項１〜請求
項９に記載のオーミック電極、配線材、ゲート電極、イ
ンダクタ又はコンデンサ電極の製造方法。10. The method for manufacturing an ohmic electrode, a wiring material, a gate electrode, an inductor or a capacitor electrode according to claim 1, wherein the alloy is developed by CVD or sputtering.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15423299A JP2000269162A (en) | 1999-03-13 | 1999-03-13 | Member for integrated circuit and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15423299A JP2000269162A (en) | 1999-03-13 | 1999-03-13 | Member for integrated circuit and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2000269162A true JP2000269162A (en) | 2000-09-29 |
Family
ID=15579747
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15423299A Pending JP2000269162A (en) | 1999-03-13 | 1999-03-13 | Member for integrated circuit and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2000269162A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2003033752A1 (en) * | 2001-10-18 | 2003-04-24 | Canadian Electronic Powders Corporation (Cepc) | Powder for laminated ceramic capacitor internal electrode |
| JP2007012922A (en) * | 2005-06-30 | 2007-01-18 | Toshiba Corp | Semiconductor device and its fabrication process |
| JP2008277685A (en) * | 2007-05-07 | 2008-11-13 | Mitsubishi Materials Corp | Interconnection film and electrode film for flat panel display using thin film transistor (tft) superior in adhesiveness, and sputtering target for forming them |
| CN101984108A (en) * | 2010-12-03 | 2011-03-09 | 中南大学 | CuNiSiAl elastic copper alloy with ultrahigh strength and high stress relaxation resistance |
| JP2013133489A (en) * | 2011-12-26 | 2013-07-08 | Sumitomo Metal Mining Co Ltd | Cu ALLOY SPUTTERING TARGET, METHOD FOR PRODUCING THE SAME, AND METAL THIN FILM |
| CN107201460A (en) * | 2017-04-28 | 2017-09-26 | 杭州前进齿轮箱集团股份有限公司 | A kind of leadless environment-friendly type wet copper-based friction plate and preparation method |
-
1999
- 1999-03-13 JP JP15423299A patent/JP2000269162A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2003033752A1 (en) * | 2001-10-18 | 2003-04-24 | Canadian Electronic Powders Corporation (Cepc) | Powder for laminated ceramic capacitor internal electrode |
| US7277268B2 (en) | 2001-10-18 | 2007-10-02 | Candian Electronic Powers Corporation | Laminated ceramic capacitor |
| US7857886B2 (en) | 2001-10-18 | 2010-12-28 | Canadian Electronic Powders Corporation | Powder for laminated ceramic capacitor internal electrode |
| JP2007012922A (en) * | 2005-06-30 | 2007-01-18 | Toshiba Corp | Semiconductor device and its fabrication process |
| JP2008277685A (en) * | 2007-05-07 | 2008-11-13 | Mitsubishi Materials Corp | Interconnection film and electrode film for flat panel display using thin film transistor (tft) superior in adhesiveness, and sputtering target for forming them |
| CN101984108A (en) * | 2010-12-03 | 2011-03-09 | 中南大学 | CuNiSiAl elastic copper alloy with ultrahigh strength and high stress relaxation resistance |
| JP2013133489A (en) * | 2011-12-26 | 2013-07-08 | Sumitomo Metal Mining Co Ltd | Cu ALLOY SPUTTERING TARGET, METHOD FOR PRODUCING THE SAME, AND METAL THIN FILM |
| CN107201460A (en) * | 2017-04-28 | 2017-09-26 | 杭州前进齿轮箱集团股份有限公司 | A kind of leadless environment-friendly type wet copper-based friction plate and preparation method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Baca et al. | A survey of ohmic contacts to III-V compound semiconductors | |
| Howard et al. | Intermetallic compounds of Al and transitions metals: Effect of electromigration in 1–2‐μm‐wide lines | |
| US9934976B2 (en) | Methods of forming low interface resistance rare earth metal contacts and structures formed thereby | |
| US4300149A (en) | Gold-tantalum-titanium/tungsten alloy contact for semiconductor devices and having a gold/tantalum intermetallic barrier region intermediate the gold and alloy elements | |
| Len et al. | An investigation into the performance of diffusion barrier materials against copper diffusion using metal-oxide-semiconductor (MOS) capacitor structures | |
| JPS59108348A (en) | Integrated semiconductor circuit | |
| US20020105081A1 (en) | Self-assembled near-zero-thickness molecular layers as diffusion barriers for Cu metallization | |
| US4316209A (en) | Metal/silicon contact and methods of fabrication thereof | |
| US5091338A (en) | Process for forming heat resistant ohmic electrode | |
| Lee et al. | Factors affecting passivation of Cu (Mg) alloy films | |
| JP2004506814A5 (en) | ||
| JP2000269162A (en) | Member for integrated circuit and its manufacture | |
| JP5774005B2 (en) | Thin film transistor (TFT) with copper electrode | |
| De Felipe et al. | Capacitance–voltage, current–voltage, and thermal stability of copper alloyed with aluminium or magnesium | |
| Kohn et al. | The role of microstructure in nanocrystalline conformal Co0. 9W0. 02P0. 08 diffusion barriers for copper metallization | |
| US20110147936A1 (en) | Semiconductor device and damascene structure | |
| Chen et al. | Backside copper metallisation of GaAs MESFETs | |
| JP2002083954A (en) | Integrated circuit member and its manufacturing method | |
| Glickman et al. | Electrical resistivity of thin electroless Ag–W films for metallization | |
| Inberg et al. | Electroless and sputtered silver–tungsten thin films for microelectronics applications | |
| Chang et al. | Use of WN/sub X/as the diffusion barrier for interconnect copper metallization of InGaP-GaAs HBTs | |
| US20100176478A1 (en) | Semiconductor device and method for manufacturing the same | |
| JPH0378258A (en) | Metal cover for semiconductor device and its manufacture | |
| KR100327092B1 (en) | Formation Method of Copper Alloy Wiring of Semiconductor Device | |
| Pramanik et al. | Barrier Metals for ULSI; processing and reliability |