JP2000252625A - Multilayer wiring board and its manufacture - Google Patents
Multilayer wiring board and its manufactureInfo
- Publication number
- JP2000252625A JP2000252625A JP4867899A JP4867899A JP2000252625A JP 2000252625 A JP2000252625 A JP 2000252625A JP 4867899 A JP4867899 A JP 4867899A JP 4867899 A JP4867899 A JP 4867899A JP 2000252625 A JP2000252625 A JP 2000252625A
- Authority
- JP
- Japan
- Prior art keywords
- plating layer
- layer
- wiring board
- copper
- copper plating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、ポリイミド樹脂を
絶縁層の材料として採用する多層配線基板及びその製造
方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer wiring board employing a polyimide resin as a material for an insulating layer and a method for manufacturing the same.
【０００２】[0002]
【従来の技術】従来、絶縁層にポリイミド樹脂を採用す
る多層配線基板においては、配線層に一般的には金を採
用する。2. Description of the Related Art Conventionally, in a multilayer wiring board using a polyimide resin for an insulating layer, gold is generally used for a wiring layer.
【０００３】金は、銅と対比してコストが高価であり、
また、電気伝搬速度が劣っている。しかし、銅を配線層
に採用することは、困難である。その理由は、銅がポリ
イミド樹脂中に拡散するから、本来ポリイミド樹脂が有
する絶縁特性が失われるためである。[0003] Gold is expensive compared to copper,
Also, the electric propagation speed is inferior. However, it is difficult to use copper for the wiring layer. The reason is that copper diffuses into the polyimide resin, so that the insulating properties inherent to the polyimide resin are lost.
【０００４】また、銅に対して親和性を有しないベンゾ
シクロブテン樹脂やエポキシ樹脂系の絶縁材料を絶縁層
に採用すれば、銅を配線層に採用することができる。し
かし、これらの絶縁材料を採用した多層配線基板は、ポ
リイミド樹脂を採用した多層配線基板と対比して、積層
枚数の限界が小さい点で劣っている。If a benzocyclobutene resin or epoxy resin-based insulating material having no affinity for copper is used for the insulating layer, copper can be used for the wiring layer. However, a multilayer wiring board employing these insulating materials is inferior to a multilayer wiring board employing a polyimide resin in that the limit of the number of stacked layers is small.
【０００５】[0005]
【発明が解決しようとする課題】そこで、本発明は、前
記従来の多層配線基板の欠点を改良し、絶縁層に採用す
るポリイミド樹脂の特性を失わずに、配線層に銅を採用
して、集積性が高く、コストが低廉で、しかも、高性能
な多層配線基板を提供しようとするものである。SUMMARY OF THE INVENTION Accordingly, the present invention has been made to solve the above-mentioned drawbacks of the conventional multilayer wiring board, and to adopt copper for the wiring layer without losing the characteristics of the polyimide resin used for the insulating layer. It is an object of the present invention to provide a multilayer wiring board having high integration, low cost, and high performance.
【０００６】[0006]
【課題を解決するための手段】本発明は、前記課題を解
決するため、次の手段を採用する。The present invention employs the following means to solve the above-mentioned problems.
【０００７】１．配線基板を次の（１）〜（６）の工程
によって順次製造し、 （１）配線基板上に第１のスパッタ膜を形成した後、第
１のレジストを塗布し、露光装置によって配線ターンを
形成すること。[0007] 1. A wiring substrate is sequentially manufactured by the following steps (1) to (6). (1) After forming a first sputtered film on the wiring substrate, a first resist is applied, and a wiring turn is performed by an exposure device. To form.
【０００８】（２）前記配線パターン上に電解メッキに
よって銅メッキ層を形成した後、前記第１のレジストを
除去すること。(2) After forming a copper plating layer on the wiring pattern by electrolytic plating, the first resist is removed.
【０００９】（３）前記第１のスパッタ膜上に第２のレ
ジストを塗布し、前記銅メッキ層よりも幅の広い寸法で
露光すること。(3) A second resist is applied on the first sputtered film, and is exposed in a dimension wider than the copper plating layer.
【００１０】（４）電解メッキによって前記銅メッキ層
を覆うようにニッケルメッキ層を形成した後、前記第２
のレジストを除去すること。(4) After forming a nickel plating layer so as to cover the copper plating layer by electrolytic plating,
Removing the resist.
【００１１】（５）前記銅メッキ層と前記ニッケルメッ
キ層とがそれぞれ形成された部分以外の前記第１のスパ
ッタ膜をミリングによって除去すること。(5) The first sputter film other than the portions where the copper plating layer and the nickel plating layer are formed is removed by milling.
【００１２】（６）前記ニッケルメッキ層上にポリイミ
ド樹脂層を積層すること。(6) Laminating a polyimide resin layer on the nickel plating layer.
【００１３】前記ポリイミド樹脂層上に第２のスパッタ
膜を形成し、以下繰り返すことによって構成する多層配
線基板の製造方法。[0013] A method of manufacturing a multilayer wiring board, comprising forming a second sputtered film on the polyimide resin layer and repeating the above steps.
【００１４】２．配線基板と、前記配線基板上に形成さ
れたスパッタ膜と、前記スパッタ膜上に形成された銅メ
ッキ層と、前記銅メッキ層を覆うように前記銅メッキ層
上に形成されたニッケルメッキ層と、前記ニッケルメッ
キ層上に積層されたポリイミド樹脂層とから構成される
多層配線基板。2. A wiring substrate, a sputtered film formed on the wiring substrate, a copper plating layer formed on the sputtered film, and a nickel plating layer formed on the copper plating layer so as to cover the copper plating layer. And a polyimide resin layer laminated on the nickel plating layer.
【００１５】[0015]
【発明の実施の形態】本発明の一実施の形態例の多層配
線基板及びその製造方法について図面を参照して説明す
る。図１は、本実施の形態例の多層配線基板の模式的断
面図であり、また、図２は、本実施の形態例の多層配線
基板の製造方法の工程図である。DESCRIPTION OF THE PREFERRED EMBODIMENTS A multilayer wiring board according to an embodiment of the present invention and a method for manufacturing the same will be described with reference to the drawings. FIG. 1 is a schematic cross-sectional view of the multilayer wiring board of the present embodiment, and FIG. 2 is a process chart of a method of manufacturing the multilayer wiring board of the present embodiment.
【００１６】図１（便宜上２層のものを示す。）におい
て、銅メッキ層２とポリイミド樹脂層１とが交互に積層
されている。この際、銅がポリイミド樹脂層１中に拡散
することを防止するために、銅メッキ層２の周囲は、ニ
ッケルメッキ層３によって覆われている。In FIG. 1 (two layers are shown for convenience), a copper plating layer 2 and a polyimide resin layer 1 are alternately laminated. At this time, the periphery of the copper plating layer 2 is covered with a nickel plating layer 3 in order to prevent copper from diffusing into the polyimide resin layer 1.
【００１７】製造方法の工程を図２（１）〜（５）を参
照して順次説明する。The steps of the manufacturing method will be sequentially described with reference to FIGS.
【００１８】１．図２（１）に示すように、配線基板上
にクロムスパッタ膜４を２０００Å形成する。この後、
フォトレジスト５を塗布し、露光装置によって配線パタ
ーンを形成する。1. As shown in FIG. 2A, a chromium sputtered film 4 is formed on the wiring substrate at 2000. After this,
A photoresist 5 is applied, and a wiring pattern is formed by an exposure device.
【００１９】２．図２（２）に示すように、配線パター
ン上に電解メッキによって銅メッキ層２を形成した後、
フォトレジスト５を除去する。2. As shown in FIG. 2 (2), after forming a copper plating layer 2 on the wiring pattern by electrolytic plating,
The photoresist 5 is removed.
【００２０】３．図２（３）に示すように、クロムスパ
ッタ膜４上にフォトレジスト５を塗布し、銅メッキ層２
よりも１μｍ幅の広い寸法で露光する。3. As shown in FIG. 2 (3), a photoresist 5 is applied on the chromium sputtered film 4 and the copper plating layer 2
Exposure is performed with a dimension 1 μm wider than that in FIG.
【００２１】４．図２（４）に示すように、電解メッキ
によって銅メッキ層２を覆うようにニッケルメッキ層３
を形成する。この後、フォトレジスト５を除去する。4. As shown in FIG. 2D, the nickel plating layer 3 is formed so as to cover the copper plating layer 2 by electrolytic plating.
To form Thereafter, the photoresist 5 is removed.
【００２２】５．図２（５）に示すように、銅メッキ層
２とニッケルメッキ層３とがそれぞれ形成された部分以
外のクロムスパッタ膜４をミリングによって除去する。5. As shown in FIG. 2 (5), the chromium sputtered film 4 other than the portions where the copper plating layer 2 and the nickel plating layer 3 are respectively formed is removed by milling.
【００２３】６．ニッケルメッキ層３上にポリイミド樹
脂層１を積層する。6. The polyimide resin layer 1 is laminated on the nickel plating layer 3.
【００２４】更に、このポリイミド樹脂層１上に同一の
方法によって第２の配線層を積層し、更に、第２のポリ
イミド樹脂層１を積層して、図１に示される２層配線基
板を得る。以下同一の方法を繰り返して多層配線基板を
得る。Further, a second wiring layer is laminated on the polyimide resin layer 1 by the same method, and further, a second polyimide resin layer 1 is laminated to obtain the two-layer wiring board shown in FIG. . Hereinafter, the same method is repeated to obtain a multilayer wiring board.
【００２５】なお、クロムスパッタ膜４の材質をパラジ
ウムスパッタ膜等に代えることができる。The material of the chromium sputtered film 4 can be changed to a palladium sputtered film or the like.
【００２６】[0026]
【発明の効果】以上の説明から明らかなように、本発明
によれば、次の効果を奏することができる。As is apparent from the above description, the present invention has the following advantages.
【００２７】１．配線層の材料に銅を採用することによ
って、従来の配線基板に採用されている金と対比してコ
ストが低廉となり、更に、電気伝搬速度が向上するた
め、多層配線基板の性能が向上する。1. By adopting copper as the material of the wiring layer, the cost is lower than that of gold used in the conventional wiring board, and the electric propagation speed is improved, so that the performance of the multilayer wiring board is improved.
【００２８】２．銅がニッケルによって覆われているた
め、絶縁材料にポリイミド樹脂を採用しても、電気的特
性が悪化しない。2. Since copper is covered with nickel, electrical characteristics do not deteriorate even when a polyimide resin is used as the insulating material.
【００２９】３．ポリイミド樹脂を絶縁材料として採用
することによって、配線基板の高積層化が可能になり、
高密度高集積性を有する多層配線基板を得ることができ
る。3. By adopting polyimide resin as the insulating material, high lamination of the wiring board becomes possible,
A multilayer wiring board having high density and high integration can be obtained.
【図１】本発明の一実施の形態例の多層配線基板の模式
的断面図である。FIG. 1 is a schematic cross-sectional view of a multilayer wiring board according to an embodiment of the present invention.
【図２】本発明の一実施の形態例の多層配線基板の製造
方法の工程図であり、順次（１）〜（５）に示す。FIG. 2 is a process chart of a method for manufacturing a multilayer wiring board according to an embodiment of the present invention, which is shown in the order of (1) to (5).
１ ポリイミド樹脂層 ２ 銅メッキ層 ３ ニッケルメッキ層 ４ クロムスパッタ膜 ５ フォトレジスト Reference Signs List 1 polyimide resin layer 2 copper plating layer 3 nickel plating layer 4 chromium sputtered film 5 photoresist
Claims (7)
次製造し、 １．配線基板上に第１のスパッタ膜を形成した後、第１
のレジストを塗布し、露光装置によって配線ターンを形
成すること。 ２．前記配線パターン上に電解メッキによって銅メッキ
層を形成した後、前記第１のレジストを除去すること。 ３．前記第１のスパッタ膜上に第２のレジストを塗布
し、前記銅メッキ層よりも幅の広い寸法で露光するこ
と。 ４．電解メッキによって前記銅メッキ層を覆うようにニ
ッケルメッキ層を形成した後、前記第２のレジストを除
去すること。 ５．前記銅メッキ層と前記ニッケルメッキ層とがそれぞ
れ形成された部分以外の前記第１のスパッタ膜をミリン
グによって除去すること。 ６．前記ニッケルメッキ層上にポリイミド樹脂層を積層
すること。 前記ポリイミド樹脂層上に第２のスパッタ膜を形成し、
以下繰り返すことによって構成することを特徴とする多
層配線基板の製造方法。1. A wiring board is sequentially manufactured by the following steps 1 to 6, After forming the first sputtered film on the wiring substrate,
To form a wiring turn using an exposure device. 2. Removing a first resist after forming a copper plating layer on the wiring pattern by electrolytic plating; 3. Applying a second resist on the first sputtered film and exposing it to a dimension wider than the copper plating layer; 4. Removing the second resist after forming a nickel plating layer so as to cover the copper plating layer by electrolytic plating. 5. Removing the first sputtered film by milling other than the portions where the copper plating layer and the nickel plating layer are respectively formed. 6. Laminating a polyimide resin layer on the nickel plating layer. Forming a second sputtered film on the polyimide resin layer,
A method for manufacturing a multilayer wiring board, characterized in that the method is repeated below.
がクロムであることを特徴とする請求項１記載の多層配
線基板の製造方法。2. The method according to claim 1, wherein the material of the first and second sputtered films is chromium.
がパラジウムであることを特徴とする請求項１記載の多
層配線基板の製造方法。3. The method according to claim 1, wherein the material of the first and second sputtered films is palladium.
ォトレジストであることを特徴とする請求項１記載の多
層配線基板の製造方法。4. The method according to claim 1, wherein the type of the first and second resists is a photoresist.
が２０００Åに形成されることを特徴とする請求項２記
載の多層配線基板の製造方法。5. The method according to claim 2, wherein each of the first and second sputtered films is formed to have a thickness of 2000 °.
りも１μｍ幅の広い寸法で露光することを特徴とする請
求項１記載の多層配線基板の製造方法。6. The method according to claim 1, wherein the second resist is exposed in a dimension 1 μm wider than the copper plating layer.
たスパッタ膜と、前記スパッタ膜上に形成された銅メッ
キ層と、前記銅メッキ層を覆うように前記銅メッキ層上
に形成されたニッケルメッキ層と、前記ニッケルメッキ
層上に積層されたポリイミド樹脂層とから構成されるこ
とを特徴とする多層配線基板。7. A wiring substrate, a sputter film formed on the wiring substrate, a copper plating layer formed on the sputter film, and a copper plating layer formed on the copper plating layer so as to cover the copper plating layer. A multi-layer wiring board, comprising: a nickel plating layer; and a polyimide resin layer laminated on the nickel plating layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4867899A JP2000252625A (en) | 1999-02-25 | 1999-02-25 | Multilayer wiring board and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4867899A JP2000252625A (en) | 1999-02-25 | 1999-02-25 | Multilayer wiring board and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2000252625A true JP2000252625A (en) | 2000-09-14 |
Family
ID=12809990
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4867899A Pending JP2000252625A (en) | 1999-02-25 | 1999-02-25 | Multilayer wiring board and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2000252625A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005317566A (en) * | 2004-04-26 | 2005-11-10 | Kyocera Corp | Wiring board and manufacturing method thereof |
| JP2006120667A (en) * | 2004-10-19 | 2006-05-11 | Fujitsu Ltd | Printed circuit board and manufacturing method thereof |
| US7285229B2 (en) | 2003-11-07 | 2007-10-23 | Mec Company, Ltd. | Etchant and replenishment solution therefor, and etching method and method for producing wiring board using the same |
-
1999
- 1999-02-25 JP JP4867899A patent/JP2000252625A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7285229B2 (en) | 2003-11-07 | 2007-10-23 | Mec Company, Ltd. | Etchant and replenishment solution therefor, and etching method and method for producing wiring board using the same |
| JP2005317566A (en) * | 2004-04-26 | 2005-11-10 | Kyocera Corp | Wiring board and manufacturing method thereof |
| JP4570390B2 (en) * | 2004-04-26 | 2010-10-27 | 京セラ株式会社 | Wiring board and manufacturing method thereof |
| JP2006120667A (en) * | 2004-10-19 | 2006-05-11 | Fujitsu Ltd | Printed circuit board and manufacturing method thereof |
| JP4599132B2 (en) * | 2004-10-19 | 2010-12-15 | 富士通株式会社 | Printed circuit board manufacturing method and printed circuit board |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20000927 |