JP2000188362A - Mounting structure of semiconductor element - Google Patents

Mounting structure of semiconductor element

Info

Publication number
JP2000188362A
JP2000188362A JP10363433A JP36343398A JP2000188362A JP 2000188362 A JP2000188362 A JP 2000188362A JP 10363433 A JP10363433 A JP 10363433A JP 36343398 A JP36343398 A JP 36343398A JP 2000188362 A JP2000188362 A JP 2000188362A
Authority
JP
Japan
Prior art keywords
semiconductor element
wiring board
filler
mounting structure
connection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10363433A
Other languages
Japanese (ja)
Inventor
Tetsuya Kimura
哲也 木村
Masahiko Azuma
昌彦 東
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP10363433A priority Critical patent/JP2000188362A/en
Publication of JP2000188362A publication Critical patent/JP2000188362A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
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    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
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    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/27—Manufacturing methods
    • H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
    • H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
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    • H01L2224/83051—Forming additional members, e.g. dam structures
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    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
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    • H01L2924/01004—Beryllium [Be]
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Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a mounting structure having high mounting reliability, even when the difference in thermal expansions between a semiconductor element and an insulated substrate of a wiring board is large, in a mounting structure where a mounting part between the semiconductor element and a wiring board such as a package, etc., is filled with filler. SOLUTION: On the surface of a wiring board A provided with a connection pad 6 as a metallization wiring layer, a semiconductor element B provided with a connecting electrode is mounted, and the connection pad 6 of the wiring board A and the connecting electrode of the semiconductor element B are connected together through hard soldering. and the connected part is filled with a filler 8 containing thermosetting resin. In the mounting structure of the semiconductor element B constituted in this manner, grooves with depth of 10-100 μm are formed in the surface of the wiring board A situated on a fillet part (spread-foot section) made of the filler 8 which is formed around the semiconductor element B, for preventing the generation and progress of cracks from the periphery of the filler 8.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、半導体素子の実装
構造に関し、特に大型の配線基板上に半導体素子をロウ
付けにより表面実装し、更にその配線基板と半導体素子
の間に熱硬化性樹脂を含む充填剤を注入硬化させてなる
熱履歴特性、使用耐久性、信頼性に優れた半導体素子の
実装構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device mounting structure, and more particularly, to a semiconductor device mounted on a large-sized wiring board by brazing, and a thermosetting resin is further provided between the wiring board and the semiconductor element. The present invention relates to a semiconductor element mounting structure obtained by injecting and curing a filler containing the compound, and having excellent heat history characteristics, durability in use, and reliability.

【０００２】[0002]

【従来技術】従来、配線基板は、絶縁基板の表面あるい
は内部にメタライズ配線層が配設された構造からなり、
この配線基板の代表的な例として、半導体素子、特にＬ
ＳＩ（大規模集積回路素子）等の半導体集積回路素子を
収容するための半導体素子収納用パッケージは、一般に
アルミナセラミックスからなる絶縁基板の表面および内
部には、タングステン、モリブデン等の高融点金属粉末
から成る複数個のメタライズ配線層が配設され、上部に
載置される半導体素子と電気的に接続される。一般に、
半導体素子の集積度が高まるほど、半導体素子に形成さ
れる電極数も増大するが、これに伴い素子と接続される
半導体収納用パッケージ側の端子数も増大すると同時
に、その設置密度を高める必要があるが、従来のワイヤ
ボンディング方式の接続方法では十分な対応が困難にな
り限界に近づきつつある。2. Description of the Related Art Conventionally, a wiring board has a structure in which a metallized wiring layer is provided on the surface or inside of an insulating substrate.
As a typical example of this wiring board, a semiconductor element, in particular, L
A semiconductor element housing package for housing a semiconductor integrated circuit element such as an SI (large-scale integrated circuit element) is generally made of a high melting point metal powder such as tungsten or molybdenum on the surface and inside of an insulating substrate made of alumina ceramics. And a plurality of metallized wiring layers are electrically connected to a semiconductor element mounted thereon. In general,
As the degree of integration of a semiconductor element increases, the number of electrodes formed on the semiconductor element also increases.With this, the number of terminals on the semiconductor storage package connected to the element also increases, and it is necessary to increase the installation density. However, it is difficult to sufficiently cope with the connection method of the conventional wire bonding method, and the connection method is approaching its limit.

【０００３】そこで、最近では、パッケージと半導体素
子との接続は、ワイヤボンディング方式から半導体素子
下面に接続用電極を設け、パッケージの接続端子とを直
接ロウ付けするフリップチップ実装方法に移行しつつあ
る。In recent years, the connection between the package and the semiconductor element has been shifted from a wire bonding method to a flip chip mounting method in which a connection electrode is provided on the lower surface of the semiconductor element and the connection terminal of the package is directly brazed. .

【０００４】また、このフリップチップ実装による接続
では、接続信頼性を高めるために、その接続部に熱硬化
性樹脂を含む、アンダーフィルと呼ばれる充填剤を注
入、硬化させて接続部を機械的に補強することがしばし
ば行われる。In connection by flip-chip mounting, in order to improve connection reliability, a filler called underfill containing a thermosetting resin is injected into the connection portion, and the connection portion is cured to mechanically connect the connection portion. Reinforcement is often performed.

【０００５】一方、パッケージのマザーボードへの実装
にあたっては、パッケージにおける接続端子の実装密度
を高める要求から、従来のリードピンによるピングリッ
ドアレイ（ＰＧＡ）方式に代えて、半田ボールを介し
た、いわゆるボールグリッドアレイ（ＢＧＡ）方式が提
案されている。On the other hand, when mounting a package on a motherboard, a so-called ball grid via a solder ball is used instead of the conventional pin grid array (PGA) system using lead pins in order to increase the mounting density of connection terminals in the package. An array (BGA) method has been proposed.

【０００６】外部電極回路基板は、しばしば、プリント
基板などの樹脂成分を含有する有機質材料乃至有機質材
料と無機質材料との複合材で構成される。The external electrode circuit board is often made of an organic material containing a resin component, such as a printed circuit board, or a composite material of an organic material and an inorganic material.

【０００７】しかしながら、ＢＧＡのような高密度で接
続端子を形成したパッケージにおいて、絶縁基板として
従来より使用されているアルミナ、ムライト等のセラミ
ックスを用いると、ガラス−エポキシ樹脂複合材料など
の有機樹脂を含む絶縁材料からなるマザーボードに表面
実装した場合、半導体素子の作動時に発する熱が絶縁基
板とマザーボードの両方に繰り返し印加され、前記マザ
ーボードと絶縁基板との熱膨張係数差によって熱応力が
発生し、この応力によって、接続用端子が絶縁基板より
剥離したり、接続部にクラックなどが生じ、配線基板を
外部電気回路基板上に長期にわたり安定に維持できない
という問題があった。However, in a package having connection terminals formed at a high density such as BGA, if ceramics such as alumina and mullite conventionally used as an insulating substrate are used, an organic resin such as a glass-epoxy resin composite material is used. When the semiconductor device is surface-mounted on a motherboard made of an insulating material, heat generated during operation of the semiconductor element is repeatedly applied to both the insulating substrate and the motherboard, and a thermal stress is generated due to a difference in thermal expansion coefficient between the motherboard and the insulating substrate. Due to the stress, the connection terminals are peeled off from the insulating substrate, cracks or the like are generated in the connection portions, and there is a problem that the wiring substrate cannot be stably maintained on the external electric circuit board for a long time.

【０００８】そこで、従来のアルミナ、ムライト等のセ
ラミックスに変えて、特開平８−２７９５７４号、特開
平８−３２２０３８号においては、絶縁基板を高熱膨張
特性を有するセラミックスによって形成することによっ
て配線基板とマザーボードとの熱膨張差を小さくするこ
とにより接続信頼性を改善することが提案されている。Therefore, instead of conventional ceramics such as alumina and mullite, JP-A-8-279574 and JP-A-8-322038 disclose that an insulating substrate is formed of a ceramic having a high thermal expansion characteristic, thereby making it possible to form a circuit board and a wiring board. It has been proposed to improve the connection reliability by reducing the thermal expansion difference with the motherboard.

【０００９】[0009]

【発明が解決しようとする課題】しかしながら、このよ
うな高熱膨張セラミックスを絶縁基板として用いた場合
には、配線基板表面に実装されるシリコンよりなる半導
体素子（熱膨張係数: ２乃至３ｐｐｍ／℃）との熱膨張
係数差が大きくなり、その結果、上記高熱膨張のセラミ
ックスの表面に半導体素子をフリップチップ実装した場
合、半導体素子と配線基板との熱膨張係数差により半導
体素子の作動、停止に発生する応力によって半導体素子
と配線基板との間の接着層が剥離するという新たな問題
が発生することが判明した。However, when such a high thermal expansion ceramic is used as an insulating substrate, a semiconductor element made of silicon mounted on the surface of a wiring board (thermal expansion coefficient: 2 to 3 ppm / ° C.) As a result, when the semiconductor element is flip-chip mounted on the surface of the high thermal expansion ceramic, the semiconductor element is activated and stopped due to the difference in thermal expansion coefficient between the semiconductor element and the wiring board. It has been found that a new problem occurs that the adhesive layer between the semiconductor element and the wiring substrate is peeled off by the applied stress.

【００１０】上記高熱膨張セラミックスを絶縁基板とし
て半導体素子を載置、実装した場合、半導体素子の作動
時に発する熱が絶縁基板に繰り返し印加されると、前記
半導体素子と絶縁基板との熱膨張係数差が大きいため
に、熱応力歪みが発生する。この熱応力は、半導体素子
の電極数が３００以下と比較的少ない場合には、発生す
る熱応力も小さいが、接続端子数が３００以上となるよ
うな大型の半導体素子の場合には、発生する応力も増大
する傾向にあり、半導体素子を安定に固定できない致命
的な欠点を有していた。When a semiconductor element is mounted and mounted with the above-mentioned high thermal expansion ceramics as an insulating substrate, when heat generated during operation of the semiconductor element is repeatedly applied to the insulating substrate, a difference in thermal expansion coefficient between the semiconductor element and the insulating substrate is obtained. Is large, thermal stress distortion occurs. This thermal stress is small when the number of electrodes of the semiconductor element is relatively small, such as 300 or less, but is generated when the large semiconductor element has 300 or more connection terminals. The stress also tends to increase, and has a fatal disadvantage that the semiconductor element cannot be fixed stably.

【００１１】また、上記のような熱応力に対しては、半
導体素子との接続部に熱硬化性樹脂を含有する充填剤を
充填することが効果的であるが、充填剤を充填しても、
上記熱応力によって、半導体素子の実装部の周辺に充填
剤によって形成されるフィレット部（裾拡がり部）の充
填剤と配線基板との界面にクラックが発生し、このクラ
ックが半導体素子の電極とパッケージの端子とのロウ材
による接続部まで進展し、前記電極と端子との電気的な
接続状態が損なわれるという問題があった。For the above-mentioned thermal stress, it is effective to fill a filler containing a thermosetting resin into a connection portion with a semiconductor element. ,
Due to the above thermal stress, cracks occur at the interface between the filler in the fillet portion (the flared portion) formed by the filler around the mounting portion of the semiconductor element and the wiring board, and this crack is formed between the electrode of the semiconductor element and the package. There is a problem that the connection between the electrode and the terminal is deteriorated, and the electrical connection between the electrode and the terminal is impaired.

【００１２】従って、本発明は、上記のような半導体素
子とパッケージなどの配線基板との実装部に充填剤を充
填した実装構造において、半導体素子と配線基板の絶縁
基板との熱膨張差が大きい場合においても高い実装信頼
性を有する実装構造を提供することを目的とするもので
ある。Accordingly, the present invention has a large thermal expansion difference between a semiconductor element and an insulating substrate of a wiring board in a mounting structure in which a filler is filled in a mounting portion of the semiconductor element and a wiring board such as a package as described above. It is an object of the present invention to provide a mounting structure having high mounting reliability even in such cases.

【００１３】[0013]

【課題を解決するための手段】本発明者等は、上記した
半導体素子のパッケージなどの配線基板に半導体素子を
フリップチップ実装し、その実装部に熱硬化性樹脂を含
有する充填剤を充填した構造において、前記半導体素子
の周辺部に形成される前記充填剤のフィレット部の下部
に位置する配線基板表面に、溝を形成することにより、
前記した欠点が回避され、強固な、かつ長期にわたり安
定した電気接続を維持できることを見いだしたものであ
る。Means for Solving the Problems The present inventors flip-chip mount a semiconductor element on a wiring board such as a package of the above-described semiconductor element, and filled the mounting portion with a filler containing a thermosetting resin. In the structure, by forming a groove on the surface of the wiring board located under the fillet portion of the filler formed in the peripheral portion of the semiconductor element,
It has been found that the above-mentioned disadvantages can be avoided and a strong and stable electrical connection can be maintained for a long time.

【００１４】即ち、本発明の半導体素子の実装構造は、
メタライズ配線層を備えた配線基板の表面に、接続用電
極を備えた半導体素子を載置し、前記配線基板のメタラ
イズ配線層と前記半導体素子の接続用電極とをロウ付け
接続し、かつその接続部を無機フィラ−を含む熱硬化性
樹脂の充填剤で補強してなる半導体素子の実装構造であ
って、前記半導体素子の周囲に形成された前記充填剤に
よるフィレット部（裾拡がり部）の前記配線基板表面に
溝を形成したことを特徴とするものである。That is, the mounting structure of the semiconductor device of the present invention is as follows.
A semiconductor element provided with a connection electrode is placed on the surface of a wiring board provided with a metallized wiring layer, and the metallized wiring layer of the wiring board is connected to the connection electrode of the semiconductor element by brazing, and the connection is made. A semiconductor element mounting structure in which a portion is reinforced with a filler of a thermosetting resin containing an inorganic filler, wherein a fillet portion (a flared portion) of the filler formed around the semiconductor element is formed by the filler. A groove is formed on the surface of the wiring board.

【００１５】また、かかる実装構造においては、前記溝
の深さが１０〜１００μｍであること、前記熱硬化性樹
脂が、ノボラック型エポキシ樹脂、ビスフェノール型エ
ポキシ樹脂のいずれかであることが望ましい。さらにか
かる構造は、前記半導体素子と前記配線基板における絶
縁基板との５０〜４００℃における熱膨張係数差が５ｐ
ｐｍ／℃以上である場合において特に有効である。In this mounting structure, it is preferable that the depth of the groove is 10 to 100 μm, and the thermosetting resin is one of a novolak epoxy resin and a bisphenol epoxy resin. Further, in this structure, a difference in thermal expansion coefficient between the semiconductor element and the insulating substrate in the wiring board at 50 to 400 ° C. is 5p.
It is particularly effective when the temperature is pm / ° C. or more.

【００１６】[0016]

【作用】半導体素子との接続部の補強を行うために、熱
硬化性樹脂を含有する充填剤を充填した構造において、
前述したような応力の発生によるクラックの発生および
進展は、半導体素子と配線基板との接続部に注入硬化さ
れた充填剤の充填不良によるボイド部から発生する場合
と、半導体素子、絶縁基板などの熱膨張係数差により、
充填剤の外部から発生する場合の２通りがある。In a structure filled with a filler containing a thermosetting resin in order to reinforce a connection portion with a semiconductor element,
The generation and propagation of cracks due to the occurrence of stress as described above occurs when a void is generated due to a defective filling of a filler injected and hardened into a connection portion between a semiconductor element and a wiring board, and when a semiconductor element, an insulating substrate, etc. Due to the difference in thermal expansion coefficient,
There are two cases where it occurs from outside the filler.

【００１７】本発明によれば、このような実装構造にお
いて、半導体素子の周囲に形成される前記充填剤のフィ
レット部（裾拡がり部）の下部に位置する配線基板に、
溝を形成することにより、配線基板に対する充填剤の接
着強度を高めることができるためにクラックの発生を防
ぎ、仮にクラックが発生したとしても、溝によってクラ
ックの進展を防ぐことができる。According to the present invention, in such a mounting structure, a wiring board positioned below a fillet portion (a flared portion) of the filler formed around the semiconductor element is provided.
By forming the groove, the adhesive strength of the filler to the wiring board can be increased, so that the occurrence of cracks can be prevented. Even if the cracks occur, the grooves can prevent the cracks from developing.

【００１８】これにより、半導体素子と配線基板との接
続部における充填剤、さらにはロウ材による接続部への
クラックの発生を防ぎ、かつその外周部から発生するク
ラックの進展を遅延化させることができる結果、半導体
素子と配線基板とを長期にわたり強固に電気的接続する
ことができ、長期使用に対しても高い信頼性が担保され
る。Thus, it is possible to prevent the occurrence of cracks in the connection portion due to the filler and the brazing material at the connection portion between the semiconductor element and the wiring board, and to delay the propagation of cracks generated from the outer peripheral portion. As a result, the semiconductor element and the wiring board can be firmly and electrically connected for a long period of time, and high reliability is ensured even for long-term use.

【００１９】[0019]

【発明の実施の形態】以下に本発明の半導体素子実装基
板を図面に基づき詳細に説明する。図１は、本発明の半
導体素子の実装構造の一例を示す概略断面図であり、図
２は、その半導体素子の実装部の拡大断面図である。図
１によれば、本発明の半導体素子の実装構造は、絶縁基
板の少なくとも表面にメタライズ配線層が配設された、
いわゆる配線基板を基礎構造とするものであるが、この
図１の場合、配線基板として、ボールグリッドアレイ
（ＢＧＡ）型パッケージを用いた場合の実装構造を示し
ている。なお、図１において、ＡはＢＧＡ型パッケージ
を構成する配線基板、Ｂは半導体素子である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a semiconductor element mounting board according to the present invention will be described in detail with reference to the drawings. FIG. 1 is a schematic sectional view showing an example of a mounting structure of a semiconductor device of the present invention, and FIG. 2 is an enlarged sectional view of a mounting portion of the semiconductor device. According to FIG. 1, the mounting structure of the semiconductor device of the present invention has a metallized wiring layer provided on at least a surface of an insulating substrate.
Although a so-called wiring board is used as a basic structure, FIG. 1 shows a mounting structure when a ball grid array (BGA) type package is used as the wiring board. In FIG. 1, A is a wiring board constituting a BGA type package, and B is a semiconductor element.

【００２０】配線基板Ａによれば、絶縁基板１の表面に
は、半導体素子Ｂと接続されるメタライズ配線層とし
て、ランド部２が形成されている。また、絶縁基板１の
底面には、外部回路基板と接続するための接続端子３が
取り付けられており、この接続端子３は、絶縁基板１の
内部に形成されたメタライズ配線層４やビアホ−ル導体
５を介してランド部２と電気的に接続されている。図１
のＢＧＡ型パッケージにおいては、接続端子３は、ボー
ル状の半田ボールにより構成され、絶縁基板１の底面に
形成された接続パッド６に対して半田等により取着され
ている。According to the wiring board A, the land portion 2 is formed on the surface of the insulating substrate 1 as a metallized wiring layer connected to the semiconductor element B. A connection terminal 3 for connecting to an external circuit board is attached to the bottom surface of the insulating substrate 1. The connection terminal 3 is formed by a metallized wiring layer 4 or a via hole formed inside the insulating substrate 1. It is electrically connected to the land 2 via the conductor 5. FIG.
In the BGA type package described above, the connection terminal 3 is formed of a ball-shaped solder ball, and is attached to the connection pad 6 formed on the bottom surface of the insulating substrate 1 by soldering or the like.

【００２１】一方、半導体素子Ｂは、フリップチップ型
からなるもので、Ｓｉ（シリコン）系等からなり、その
下面には半田バンプからなる接続用電極７が形成されて
いる。そして、この半導体素子Ｂは、図２の要部拡大図
に示すように、配線基板Ａの絶縁基板１上面のランド部
２に対して、接続用電極（半田バンプ）７を載置当接さ
せ、しかる後、約２５０乃至４００℃の温度で加熱して
半田バンプを溶接させることにより、半導体素子Ｂの接
続用電極７を配線基板Ａのランド部２に接合、実装され
ている。そして、この半導体素子Ｂの実装部には、実装
部の補強のために熱硬化性樹脂を含有する充填剤８が充
填されている。本発明によれば、上記実装構造におい
て、上記半導体素子Ｂの周囲に形成される充填剤８のフ
ィレット部（裾拡がり部）９の下部に位置する配線基板
Ａの表面に、溝１０を形成する。この溝１０を形成する
ことで、充填剤８が溝１０内まで充填される結果、この
溝１０内に侵入した充填剤８が、アンカー（錨）として
作用することにより充填剤８の配線基板Ａとの接着強度
を高めることができる。On the other hand, the semiconductor element B is of a flip-chip type, made of Si (silicon) or the like, and has a connection electrode 7 made of a solder bump formed on the lower surface thereof. Then, as shown in the main part enlarged view of FIG. 2, the semiconductor element B has a connection electrode (solder bump) 7 placed and brought into contact with the land 2 on the upper surface of the insulating substrate 1 of the wiring board A. Thereafter, the connection electrodes 7 of the semiconductor element B are joined and mounted on the lands 2 of the wiring board A by heating at a temperature of about 250 to 400 ° C. and welding the solder bumps. The mounting portion of the semiconductor element B is filled with a filler 8 containing a thermosetting resin for reinforcing the mounting portion. According to the present invention, in the mounting structure, the groove 10 is formed on the surface of the wiring board A located below the fillet portion (flared portion) 9 of the filler 8 formed around the semiconductor element B. . By forming the groove 10, the filler 8 is filled up to the inside of the groove 10. As a result, the filler 8 that has entered the groove 10 acts as an anchor, so that the wiring board A of the filler 8 is formed. And the adhesive strength with the adhesive can be increased.

【００２２】また、かかる構造においては、配線基板Ａ
と充填剤８との界面形状が複雑化するために、前記界面
付近から発生した微小クラックが、前記ロウ付け接続部
にまで進展するのを溝１０によって抑制することができ
る。In such a structure, the wiring board A
Since the interface shape between the metal and the filler 8 is complicated, the micro-cracks generated from the vicinity of the interface can be suppressed by the groove 10 from extending to the brazing connection portion.

【００２３】この溝１０による上記の効果を発揮させる
ためには、その深さが１０〜１００μｍであることが望
ましく、この深さが１０μｍよりも小さいと、上記効果
が望めず、１００μｍを越えると、プレッシャークッカ
ー試験のような信頼性試験において充填剤の剥離が生じ
やすくなり、また、溝を起点とするクラックが発生しや
すくなるために基板の絶対強度が低下しやすくなるなど
の不具合が発生する虞があるためである。なお、溝１０
の幅は、フィレット部の幅に応じて適宜選択されるが、
特に０．１〜１ｍｍが適当である。In order to exhibit the above-described effect of the groove 10, the depth is desirably 10 to 100 μm. If the depth is smaller than 10 μm, the above effect cannot be expected. In a reliability test such as a pressure cooker test, the filler tends to peel off, and cracks originating from the groove tend to occur, which causes problems such as a decrease in the absolute strength of the substrate. This is because there is a fear. The groove 10
Is appropriately selected according to the width of the fillet portion,
In particular, 0.1 to 1 mm is appropriate.

【００２４】また、この溝１０は、図２に示すように、
半導体素子Ｂの実装部周囲の充填剤８によるフィレット
部９が形成されうる全周囲に、１本あるいは２本以上で
形成することが最も望ましいが、実装部周囲に部分的に
形成してもよいが、その場合には、全周囲の５０％以上
の部分に溝を形成することが望ましい。このような溝の
形成は、絶縁基板を作成する際に、焼成前のシート状成
形体にスルーホールの孔あけに使用されるパンチング、
レーザーあるいは金型プレスを用いて孔あけしたものを
積層し、焼成するか、焼成後の基板表面をレーザー等に
よって加工することにより形成できる。Further, as shown in FIG.
It is most desirable to form one or two or more fillets 9 around the mounting portion of the semiconductor element B around the mounting portion by the filler 8, but it may be formed partially around the mounting portion. However, in that case, it is desirable to form a groove in a portion of 50% or more of the entire circumference. The formation of such a groove is performed by punching, which is used for forming a through hole in a sheet-like molded body before firing when forming an insulating substrate,
It can be formed by laminating holes perforated by using a laser or a mold press and firing, or by processing the substrate surface after firing by laser or the like.

【００２５】本発明における充填剤８中に含まれる熱硬
化性樹脂としては、例えばフェノール樹脂、ユリア樹
脂、メラミン樹脂、エポキシ樹脂、不飽和ポリエステル
樹脂、フタル酸ジアリル樹脂、ポリイミド樹脂、シリコ
ーン樹脂、ポリウレタン樹脂などを挙げることができ
る。これらの中でも、ビスフェノール系エポキシ樹脂、
ノボラック系エポキシ樹脂、ブロム化エポキシ樹脂、脂
環式エポキシ樹脂などのエポキシ樹脂が特に望ましい。The thermosetting resin contained in the filler 8 in the present invention includes, for example, phenol resin, urea resin, melamine resin, epoxy resin, unsaturated polyester resin, diallyl phthalate resin, polyimide resin, silicone resin, polyurethane resin Resins and the like can be mentioned. Among these, bisphenol-based epoxy resins,
Epoxy resins such as novolak epoxy resins, brominated epoxy resins, and alicyclic epoxy resins are particularly desirable.

【００２６】また、この充填剤８中には、熱硬化性樹脂
以外に、無機フィラーを含有することが望ましい。この
無機質フィラーは、充填剤８の熱膨張係数を下げるため
に熱硬化性樹脂に添加されるものであり、無機質フィラ
ーが球状粒子を主体とする場合には、半導体素子Ｂと配
線基板Ａとの実装部の狭い空間に対する充填性を高める
ことができる結果、充填剤中への充填不良によるクラッ
クの発生を防止することができる。The filler 8 preferably contains an inorganic filler in addition to the thermosetting resin. This inorganic filler is added to the thermosetting resin in order to reduce the coefficient of thermal expansion of the filler 8, and when the inorganic filler is mainly composed of spherical particles, the semiconductor filler B and the wiring substrate A As a result, it is possible to enhance the filling property in the narrow space of the mounting portion, so that it is possible to prevent the occurrence of cracks due to poor filling in the filler.

【００２７】この球状粒子は、粒子の表面に角部が実質
的に存在せず、粒子間の摩擦が小さいことから良好な充
填性を示すものと推察される。特にこの球状粒子は、平
均アスペクト比（長径／短径）が１．２以下、特に１．
１以下であり、長径による平均粒径が０．３〜２０μ
ｍ、特に１〜１０μｍが充填性の点から好適である。こ
の平均粒径が０．３μｍよりも小さいと、充填剤の粘性
が低く、充填性が悪化してボイドが発生しやすくなり、
平均粒径が２０μｍを越えると、半導体素子と配線基板
との間にフィラーが充填されにくく、ボイドの発生およ
び充填剤の不均一に伴うクラックが発生しやくなるため
である。用いられる無機フィラーとしては、石英ガラ
ス、アルミナ、マイカ、ジルコニウムシリケート、リチ
ウムシリケートなどの破砕状、もしくは球状の無機物が
望ましい。It is presumed that the spherical particles have good filling properties because there are substantially no corners on the surface of the particles and the friction between the particles is small. In particular, the spherical particles have an average aspect ratio (major axis / minor axis) of 1.2 or less, especially 1.
1 or less, and the average particle diameter according to the long diameter is 0.3 to 20 μm
m, especially 1 to 10 μm, is preferable from the viewpoint of filling properties. When the average particle size is smaller than 0.3 μm, the viscosity of the filler is low, the filling property is deteriorated, and voids are easily generated,
If the average particle size exceeds 20 μm, it is difficult for the filler to be filled between the semiconductor element and the wiring board, and the generation of voids and cracks due to the non-uniformity of the filler tend to occur. As the inorganic filler to be used, a crushed or spherical inorganic substance such as quartz glass, alumina, mica, zirconium silicate, and lithium silicate is desirable.

【００２８】また、本発明の半導体素子の実装構造は、
半導体素子Ｂと配線基板Ａの絶縁基板１との５０〜４０
０℃における熱膨張係数差が５ｐｐｍ／℃以上、特に７
ｐｐｍ／℃以上の場合、熱膨張差によって発生する熱応
力が大きいので、本発明の実装構造は特に有効である。
特に、上記熱膨張係数差が５ｐｐｍ／℃以上となる場合
としては、特に、絶縁基板１の５０〜４００℃における
熱膨張係数が８〜２５ｐｐｍ／℃であり、配線基板を２
次実装するマザーボードなどの有機樹脂を絶縁材料とす
る外部回路基板との熱膨張係数差を小さくする場合であ
る。The mounting structure of the semiconductor device of the present invention is as follows.
50 to 40 between semiconductor element B and insulating substrate 1 of wiring board A
The difference in thermal expansion coefficient at 0 ° C. is 5 ppm / ° C. or more, especially 7
When the temperature is not less than ppm / ° C., the thermal stress generated due to the difference in thermal expansion is large, so the mounting structure of the present invention is particularly effective.
In particular, when the difference in thermal expansion coefficient is 5 ppm / ° C. or more, the thermal expansion coefficient of the insulating substrate 1 at 50 to 400 ° C. is 8 to 25 ppm / ° C.
This is the case where the difference in thermal expansion coefficient between the substrate and an external circuit board using an organic resin as an insulating material, such as a mother board, to be mounted next is reduced.

【００２９】これは、外部回路基板と配線基板Ａとの長
期接続信頼性を得るためであって、絶縁基板１の熱膨張
係数が８ｐｐｍ／℃よりも小さいか、あるいは２５ｐｐ
ｍ／℃よりも大きいと、外部回路基板との熱膨張係数差
が大きくなり、熱膨張係数差に起因する応力によって配
線基板Ａの外部回路基板への接続信頼性が、損なわれる
ためである。This is for obtaining long-term reliability of connection between the external circuit board and the wiring board A. The thermal expansion coefficient of the insulating board 1 is smaller than 8 ppm / ° C. or 25 pp.
If it is larger than m / ° C., the difference in thermal expansion coefficient from the external circuit board increases, and the connection reliability of the wiring board A to the external circuit board is impaired by the stress caused by the difference in thermal expansion coefficient.

【００３０】なお、この配線基板Ａの表面に実装された
半導体素子Ｂは、所望の熱硬化性樹脂によって配線基板
Ａにて樹脂封止されるか、または適当な蓋体を配線基板
Ａの表面に接合することによりその内部に半導体素子Ｂ
を気密に封止される。The semiconductor element B mounted on the surface of the wiring board A is resin-sealed with a desired thermosetting resin in the wiring board A, or an appropriate lid is attached to the surface of the wiring board A. The semiconductor element B inside
The airtightly sealed.

【００３１】[0031]

【実施例】Ａｌ2 Ｏ3 粉末にＳｉＯ2 、ＭｇＯ、ＣａＯ
を合計で３重量％添加混合した組成物（Ａ）、ＳｉＯ2
７８重量％、Ｌｉ2 Ｏ１０重量％、Ａｌ2 Ｏ3 ４重量
％、Ｋ2 Ｏ４重量％、Ｐ2 Ｏ5 ２重量％、Ｎａ2 Ｏ２重
量％の組成からなるガラス粉末５０体積％に対して、フ
ォルステライトを５０体積％添加混合した組成物（Ｂ）
をそれぞれドクターブレード法によってシート状に成形
した後、組成物（Ａ）のシートに対してはタングステン
ペーストを、組成物（Ｂ）のシートに対しては銅ペース
トを用いて、ランド部、メタライズ配線層およびスルー
ホール導体を印刷あるいは充填して形成した後、組成物
（Ａ）に対しては１６００℃、組成物（Ｂ）に対しては
９００℃でそれぞれ焼成してパッケージ用配線基板を作
製し、表面のランド部にはＮｉメッキを施した。その
後、上記ランド部の周囲に、表１〜３にに示すような本
数、幅、深さの溝をレーザー照射によって形成した。[Example] SiO 2 , MgO, CaO were added to Al 2 O 3 powder.
Composition 3 was wt% admixed in a total amount (A), SiO 2
78 wt%, Li 2 O10 wt%, Al 2 O 3 4% by weight, K 2 O4 wt%, P 2 O 5 2% by weight, relative to the glass powder 50% by volume consisting of Na 2 O2 wt% of the composition, Composition (B) containing 50% by volume of forsterite added and mixed
Are formed into a sheet shape by a doctor blade method, and a land portion and a metallized wiring are formed by using a tungsten paste for the sheet of the composition (A) and a copper paste for the sheet of the composition (B). After forming or forming the layer and the through-hole conductor by printing or filling, the composition (A) is fired at 1600 ° C. and the composition (B) is fired at 900 ° C. to produce a package wiring board. The surface land portions were plated with Ni. Thereafter, grooves having the number, width and depth as shown in Tables 1 to 3 were formed by laser irradiation around the lands.

【００３２】そして、この基板の下面の接続端子に直径
が０．５ｍｍの高融点半田（Ｓｎ：Ｐｂ重量比＝１０：
９０）のボールを低融点半田（Ｓｎ：Ｐｂ重量比＝６
３：３７）により取り付けてパッケージＡを作製した。
作製したパッケージの寸法は、縦２２ｍｍ×横１４ｍｍ
×厚み０．９ｍｍである。Then, a high melting point solder having a diameter of 0.5 mm (Sn: Pb weight ratio = 10:
90) with low melting point solder (Sn: Pb weight ratio = 6)
3:37) to prepare a package A.
The dimensions of the fabricated package are 22 mm long x 14 mm wide
X 0.9 mm in thickness.

【００３３】一方、Ｓｉからなり４０〜４００℃におけ
る熱膨張係数が２．６ｐｐｍ／℃であり、縦１２ｍｍ×
横１２ｍｍのサイズからなり、下面に半田バンプからな
る電極パッドが形成されたフリップチップ型半導体素子
を用意し、この半導体素子を配線基板のランド部に搭載
して１５０℃に加熱することにより半田バンプを溶融さ
せて半導体素子を配線基板に実装した。On the other hand, it is made of Si, has a coefficient of thermal expansion at 40 to 400 ° C. of 2.6 ppm / ° C., and is 12 mm long ×
A flip-chip type semiconductor device having a size of 12 mm in width and having an electrode pad made of a solder bump formed on the lower surface is prepared, and this semiconductor device is mounted on a land portion of a wiring board and heated to 150 ° C. Was melted to mount the semiconductor element on the wiring board.

【００３４】その後、この半導体素子と配線基板との間
に、ビスフェノール型エポキシ樹脂５０体積％、平均粒
径が５μｍの球状アルミナ粉末５０体積％からなる充填
剤をディスペンサーにより注入し、配線基板表面の溝内
部にも充填した後、１５０℃の乾燥機に２時間保持して
熱硬化性樹脂を硬化させた。Thereafter, a filler consisting of 50% by volume of bisphenol-type epoxy resin and 50% by volume of spherical alumina powder having an average particle diameter of 5 μm is injected between the semiconductor element and the wiring board by a dispenser, and a filler on the surface of the wiring board is formed. After filling the inside of the groove, the thermosetting resin was cured by holding in a dryer at 150 ° C. for 2 hours.

【００３５】なお、前記（Ａ）（Ｂ）のセラミックスに
対して５０〜４００℃の熱膨張係数を測定した結果を表
１に示した。The results of measuring the thermal expansion coefficients of the ceramics (A) and (B) at 50 to 400 ° C. are shown in Table 1.

【００３６】[0036]

【表１】 [Table 1]

【００３７】また、上記パッケージ用配線基板に対し
て、以下の評価を行った。 （熱サイクル試験）上記配線基板表面に半導体素子を実
装したものを大気雰囲気にて−６５℃と１５０℃の各温
度に制御した高温槽に試験サンプルをそれぞれ３０分つ
づの保持を１サイクルとして最高３０００サイクル繰り
返した。そして、１００サイクル毎に超音波探傷装置及
び顕微鏡による外観検査より界面の剥離の確認を行い、
剥離が発生するまでのサイクル回数を表２、３に示し
た。The following evaluation was performed on the package wiring board. (Thermal cycling test) The above test was carried out in a high-temperature bath in which a semiconductor element was mounted on the surface of the above wiring board at a temperature of −65 ° C. and 150 ° C. in an air atmosphere. 3000 cycles were repeated. Then, every 100 cycles, the peeling of the interface was confirmed from the appearance inspection using an ultrasonic flaw detector and a microscope,
Tables 2 and 3 show the number of cycles until peeling occurred.

【００３８】（プレッシャークッカー試験）また、上記
半導体素子を実装した配線基板について、各試料毎に２
０個のサンプルを作製し、これを１２１℃、２気圧、１
００％湿度に管理されている高温高湿高圧装置に１６８
時間入れた。その後、配線基板の外観検査と超音波探傷
機により、剥離の確認を行い剥離が観察されたサンプル
数を表２、３に示した。(Pressure Cooker Test) Further, with respect to the wiring board on which the above-described semiconductor element is mounted, two
0 samples were prepared, and this was heated to 121 ° C., 2 atm, 1
168 for high-temperature, high-humidity, high-pressure equipment controlled at 00% humidity
I put the time. Thereafter, the peeling was confirmed by the appearance inspection of the wiring board and the ultrasonic flaw detector, and the number of samples in which the peeling was observed is shown in Tables 2 and 3.

【００３９】（基板破壊荷重）上記溝を形成したパッケ
ージ用配線基板の溝形成面を引張面とする３点曲げ強度
をオートグラフを用い、破壊に至った時の荷重を表２、
３に示した。(Substrate Breaking Load) Using an autograph, the three-point bending strength using the groove-formed surface of the package wiring substrate having the above-described groove formed as a tensile surface was calculated.
3 is shown.

【００４０】[0040]

【表２】 [Table 2]

【００４１】[0041]

【表３】 [Table 3]

【００４２】また、表１のようにＳｉ半導体素子との熱
膨張差が５ｐｐｍ／℃以下の場合には、溝を形成しなく
ても熱サイクル試験で２０００回以上の比較的高い耐久
性を有するが、試料Ｎo.２、３に示すように、溝を形成
することにより、熱サイクル試験に対する耐久性がさら
に向上した。When the difference in thermal expansion from the Si semiconductor element is 5 ppm / ° C. or less as shown in Table 1, even if a groove is not formed, it has a relatively high durability of 2000 times or more in a thermal cycle test. However, as shown in Samples Nos. 2 and 3, the formation of the grooves further improved the durability against the heat cycle test.

【００４３】これに対して、表２に示すように、半導体
素子との熱膨張差が５ｐｐｍ／℃を越える場合、溝のな
い試料Ｎo.４では、熱サイクル試験で１２００回で剥離
が発生し、またプレッシャークッカー試験において全て
のサンプルに剥離が観察された。On the other hand, as shown in Table 2, when the difference in thermal expansion from the semiconductor element exceeds 5 ppm / ° C., in the sample No. 4 having no groove, peeling occurred 1200 times in the thermal cycle test. In the pressure cooker test, peeling was observed in all the samples.

【００４４】これに対して、本発明に従い、溝を形成す
ることにより、熱サイクル試験およびプレッシャークッ
カー試験において改善が認められた。On the other hand, by forming the grooves according to the present invention, improvements were recognized in the heat cycle test and the pressure cooker test.

【００４５】また、本発明品の中でも、溝の深さが１０
〜１００μｍ、溝の幅が１００〜３００μｍの範囲の試
料Ｎo.５〜７、１０〜１２、１６〜２１では、いずれも
熱サイクル試験で２２００回以上、プレッシャークッカ
ー試験において剥離したサンプルは全くなく良好な結果
を示した。Further, among the products of the present invention, the groove having a depth of 10
Sample Nos. 5 to 7, 10 to 12, and 16 to 21 having a groove width of 100 to 300 μm and a groove width of 100 to 300 μm were all good at 2200 times or more in the heat cycle test and no samples peeled off in the pressure cooker test. Results were shown.

【００４６】[0046]

【発明の効果】上述した通り、本発明の半導体素子の実
装構造によれば、半導体素子の周囲に形成される充填剤
のフィレット部の下部に位置する配線基板表面に、溝を
形成することにより、充填剤の周囲からのクラックの発
生とともにクラックの進展を防止し、半導体素子と配線
基板の絶縁基板との熱膨張差が大きい場合においても長
期にわたり正確かつ強固な電気的接続を維持し、高い実
装信頼性を有する実装構造を提供できる。As described above, according to the semiconductor device mounting structure of the present invention, the groove is formed on the surface of the wiring board located below the fillet portion of the filler formed around the semiconductor device. Prevents cracks from developing around the filler, and prevents the cracks from developing, and maintains accurate and strong electrical connections for a long time even when the thermal expansion difference between the semiconductor element and the insulating substrate of the wiring board is large, A mounting structure with mounting reliability can be provided.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の半導体素子の実装構造における一例と
して、ＢＧＡ型パッケージにおける実装構造を説明する
ための概略断面図である。FIG. 1 is a schematic cross-sectional view for explaining a mounting structure in a BGA type package as an example of a mounting structure of a semiconductor device of the present invention.

【図２】図１における実装部の要部拡大断面図である。FIG. 2 is an enlarged sectional view of a main part of a mounting unit in FIG.

【符号の説明】[Explanation of symbols]

１ 絶縁基板 ２ ランド部 ３ 接続端子 ４ メタライズ配線層 ５ ビアホール導体 ６ 接続パッド ７ 接続用電極 ８ 充填剤 ９ フィレット部 １０ 溝 Ａ 配線基板（パッケージ） Ｂ 半導体素子 DESCRIPTION OF SYMBOLS 1 Insulating substrate 2 Land part 3 Connection terminal 4 Metallization wiring layer 5 Via hole conductor 6 Connection pad 7 Connection electrode 8 Filler 9 Fillet part 10 Groove A Wiring board (package) B Semiconductor element

Claims (4)

【特許請求の範囲】[Claims] 【請求項１】メタライズ配線層を備えた配線基板の表面
に、接続用電極を備えた半導体素子を載置し、前記配線
基板のメタライズ配線層と前記半導体素子の接続用電極
とをロウ付け接続し、かつその接続部に熱硬化性樹脂を
含む充填剤を充填してなる半導体素子の実装構造であっ
て、前記半導体素子の周囲に形成された前記充填剤によ
るフィレット部（裾拡がり部）に位置する前記配線基板
表面に溝を形成したことを特徴とする半導体素子の実装
構造。1. A semiconductor device provided with a connection electrode is mounted on a surface of a wiring board provided with a metallized wiring layer, and the metallized wiring layer of the wiring board is connected to the connection electrode of the semiconductor element by brazing. And a connection part filled with a filler containing a thermosetting resin, wherein the filler is formed around the semiconductor element and fillet portions (flared portions) formed by the filler are formed around the semiconductor element. A mounting structure for a semiconductor element, wherein a groove is formed on the surface of the wiring board located. 【請求項２】前記溝の深さが１０〜１００μｍである請
求項１記載の半導体素子の実装構造。2. The mounting structure of a semiconductor device according to claim 1, wherein said groove has a depth of 10 to 100 μm. 【請求項３】前記熱硬化性樹脂が、エポキシ樹脂を含む
請求項１記載の半導体素子の実装構造。3. The mounting structure according to claim 1, wherein said thermosetting resin contains an epoxy resin. 【請求項４】前記半導体素子と前記配線基板との５０〜
４００℃における熱膨張係数差が５ｐｐｍ／℃以上であ
る請求項１記載の半導体素子の実装構造。4. A semiconductor device according to claim 1, wherein said semiconductor device and said wiring board are connected to each other by 50 to
2. The semiconductor element mounting structure according to claim 1, wherein a difference in thermal expansion coefficient at 400 ° C. is 5 ppm / ° C. or more.
JP10363433A 1998-12-21 1998-12-21 Mounting structure of semiconductor element Pending JP2000188362A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10363433A JP2000188362A (en) 1998-12-21 1998-12-21 Mounting structure of semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10363433A JP2000188362A (en) 1998-12-21 1998-12-21 Mounting structure of semiconductor element

Publications (1)

Publication Number Publication Date
JP2000188362A true JP2000188362A (en) 2000-07-04

Family

ID=18479298

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10363433A Pending JP2000188362A (en) 1998-12-21 1998-12-21 Mounting structure of semiconductor element

Country Status (1)

Country Link
JP (1) JP2000188362A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007123789A (en) * 2005-10-31 2007-05-17 Mitsumi Electric Co Ltd Electronic component mounting structure of electronic module
JP2010062429A (en) * 2008-09-05 2010-03-18 Fujitsu Microelectronics Ltd Semiconductor device, and method of manufacturing the same
US8110933B2 (en) 2006-12-26 2012-02-07 Panasonic Corporation Semiconductor device mounted structure and semiconductor device mounted method
CN106992157A (en) * 2015-11-27 2017-07-28 富士电机株式会社 Semiconductor device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007123789A (en) * 2005-10-31 2007-05-17 Mitsumi Electric Co Ltd Electronic component mounting structure of electronic module
US8110933B2 (en) 2006-12-26 2012-02-07 Panasonic Corporation Semiconductor device mounted structure and semiconductor device mounted method
JP2010062429A (en) * 2008-09-05 2010-03-18 Fujitsu Microelectronics Ltd Semiconductor device, and method of manufacturing the same
CN106992157A (en) * 2015-11-27 2017-07-28 富士电机株式会社 Semiconductor device
CN106992157B (en) * 2015-11-27 2021-10-26 富士电机株式会社 Semiconductor device with a plurality of semiconductor chips

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