JP2000183150A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JP2000183150A JP2000183150A JP10352716A JP35271698A JP2000183150A JP 2000183150 A JP2000183150 A JP 2000183150A JP 10352716 A JP10352716 A JP 10352716A JP 35271698 A JP35271698 A JP 35271698A JP 2000183150 A JP2000183150 A JP 2000183150A
- Authority
- JP
- Japan
- Prior art keywords
- trench
- film
- silicon oxide
- oxide film
- organic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Element Separation (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体装置の製造方
法に関し、特にLSIの製造プロセスにおいて、トランジ
スター素子分離領域の形成工程に特徴を持つ製造方法に
関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing an LSI, which is characterized by a step of forming a transistor isolation region in an LSI manufacturing process.
【０００２】[0002]
【従来の技術】微細化された半導体集積回路を製造する
際、トランジスター素子をトレンチで分離する技術が行
われている。さらに微細化が進んだ半導体集積回路では
トレンチのアスペクト比が大きくなり、減圧ＣＶＤ法や
常圧ＣＶＤ法ではボイドフリーの埋め込みが困難になっ
てきている。アスペクト比が大きくなったトレンチを、
絶縁物質で埋め込む方法の提案がなされている。2. Description of the Related Art When a miniaturized semiconductor integrated circuit is manufactured, a technique for separating transistor elements by trenches has been used. Further, the aspect ratio of the trench is increased in a miniaturized semiconductor integrated circuit, and it is becoming difficult to perform void-free filling by a low-pressure CVD method or a normal-pressure CVD method. A trench with an increased aspect ratio
A method of embedding with an insulating material has been proposed.
【０００３】図１に『DUMIC 1998ｐ115〜』に示された
方法を説明する。この方法は（Ａ）シリコン基板２にト
レンチ形成後回転塗布法によりＨＳＱ膜（ｈｙｄｏｒｉ
ｄｓｉｌｓｉｌｏｘａｎｅ）６をトレンチ内部に５００
Å堆積し、トレンチのアスペクト比を下げる。（Ｂ）そ
の後減圧ＣＶＤシリコン酸化膜８でトレンチをボイド無
く埋め込む方法である。FIG. 1 illustrates the method described in "DUMIC 1998 p115-". In this method, (A) an HSQ film (hydrori) is formed by spin coating after forming a trench in the silicon substrate 2.
dsilsiloxane) 6 into the trench 500
Å Deposit and lower the aspect ratio of the trench. (B) After that, the trench is filled with the low-pressure CVD silicon oxide film 8 without voids.
【０００４】[0004]
【発明が解決しようとする課題】従来の方法では図２に
示すように、（Ａ）シリコン基板よりも上の部分にＨＳ
Ｑ膜６が堆積したままで、上層に減圧ＣＶＤシリコン酸
化膜８を堆積する。（Ｂ）後工程で化学的機械研磨、洗
浄処理により半導体シリコン基板よりも上のトレンチエ
ッヂ部分で、ウエットエッチレートが大きいＨＳＱ膜
が、選択的にエッチングされる部分１０が発生する。そ
の部分より洗浄液がトレンチ内部に混入し、電気的絶縁
性が劣化する可能性がある。According to the conventional method, as shown in FIG. 2, (A) the HS above the silicon substrate
With the Q film 6 deposited, a low pressure CVD silicon oxide film 8 is deposited on the upper layer. (B) A portion 10 where the HSQ film having a high wet etch rate is selectively etched at a trench edge portion above the semiconductor silicon substrate by a chemical mechanical polishing and a cleaning process in a later step. There is a possibility that the cleaning liquid is mixed into the trench from that portion, and the electrical insulation is deteriorated.
【０００５】そして液体を材料とする回転塗布法では、
堆積選択性が無いのでウエハ全面に連続的に膜が堆積す
る。その結果、薄膜化しても半導体シリコン基板よりも
上のトレンチエッヂ部分にはＨＳＱ膜が堆積し、上記の
不具合が懸念される。In the spin coating method using a liquid material,
Since there is no deposition selectivity, a film is continuously deposited on the entire surface of the wafer. As a result, the HSQ film is deposited on the trench edge portion above the semiconductor silicon substrate even if the film is thinned, and the above-mentioned problem is feared.
【０００６】本発明は第１のシリコン酸化膜によりトレ
ンチのアスペクト比を下げ、次いで第２のシリコン酸化
膜でボイド無くトレンチを埋め込んだ素子分離領域を有
する半導体装置の製造方法を提供することを目的とす
る。SUMMARY OF THE INVENTION It is an object of the present invention to provide a method of manufacturing a semiconductor device having an element isolation region in which a trench is buried without voids by using a first silicon oxide film and then a second silicon oxide film is used to reduce the aspect ratio of the trench. And
【０００７】[0007]
【課題を解決するための手段】上記目的を達成するため
本発明では、まず半導体基板の素子分離領域を形成し、
半導体基板に溝を形成し、前記基板上および前記溝内部
に有機基を有するシリコン酸化膜を形成し、前記基板表
面よりも下でトレンチ底部よりも上の部分まで、前記シ
リコン酸化膜の有機基を除去し、前記有機基を取り去っ
た部分の前記シリコン酸化膜を除去し、高密度プラズマ
ＣＶＤ法により、前記溝に形成された前記シリコン酸化
膜上に、あらたにシリコン酸化膜を形成する。これによ
りボイド無くトレンチを絶縁物質で埋め込み、素子分離
領域を形成することができる。In order to achieve the above object, according to the present invention, first, an element isolation region of a semiconductor substrate is formed,
Forming a groove in a semiconductor substrate, forming a silicon oxide film having an organic group on the substrate and inside the groove, and forming an organic group of the silicon oxide film on a portion below the substrate surface and above a trench bottom; Is removed, and the silicon oxide film at the portion from which the organic groups have been removed is removed, and a silicon oxide film is newly formed on the silicon oxide film formed in the groove by high-density plasma CVD. As a result, the trench can be filled with the insulating material without voids, and an element isolation region can be formed.
【０００８】[0008]
【発明の実施の形態】本発明の一実施例について図３を
用いて説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described with reference to FIG.
【０００９】（Ａ）半導体基板に膜厚１５０ｎｍのシリ
コン窒化膜４をハードマスクとして深さ４５０ｎｍのト
レンチが形成された下地２上に、有機ＳＯＧ膜２０を３
００ｎｍ塗布する。回転塗布法では溝部分への堆積膜厚
は溝幅に依存し、狭い溝ほど堆積膜厚は大きくなる。こ
の場合有機ＳＯＧ膜は非トレンチ領域では３００ｎｍ程
度堆積し、０．５ｕｍ以下の幅のトレンチではシリコン
窒化膜よりも上まで堆積している。(A) An organic SOG film 20 is formed on a base 2 having a trench of 450 nm in depth formed on a semiconductor substrate using a silicon nitride film 4 of 150 nm in thickness as a hard mask.
00 nm is applied. In the spin coating method, the deposited film thickness in the groove portion depends on the groove width, and the smaller the groove, the larger the deposited film thickness. In this case, the organic SOG film is deposited to a thickness of about 300 nm in the non-trench region, and is deposited to a level higher than the silicon nitride film in the trench having a width of 0.5 μm or less.
【００１０】（Ｂ）トレンチ部分に堆積した有機ＳＯＧ
膜２０の一部の有機基を、深さ方向に対して約４００ｎ
ｍ酸素プラズマにより除去する。この工程で前記有機Ｓ
ＯＧ膜中に有機基が残留している部分は、トレンチ内部
の底面から約２００ｎｍだけになる。(B) Organic SOG deposited on trench
Some of the organic groups of the film 20 are reduced to about 400 n in the depth direction.
Removed by oxygen plasma. In this step, the organic S
The portion where the organic group remains in the OG film is only about 200 nm from the bottom inside the trench.
【００１１】（Ｃ）少なくとも一部の有機基が除去され
ている部分２２は、膜に空孔あるいはＳｉ−ＯＨやＨ−
ＯＨの結合が多くなりエッチレートが大きくなる。この
違いを利用して少なくとも一部の有機基が除去された部
分２２のみを選択的にエッチバック除去する。例えばＣ
ＨＦ3、ＣＨ4ガスを１：１程度に混合した、ＲＩＥ（反
応性イオンエッチング）では有機基が除去されたＳＯＧ
は有機ＳＯＧの１．５〜２．０倍ほどエッチレートが大
きい。よってトレンチ内部のみに有機ＳＯＧ膜を残留さ
せることは十分可能である。(C) The portion 22 from which at least a part of the organic group has been removed is a hole or Si-OH or H-
The number of OH bonds increases and the etch rate increases. By utilizing this difference, only the portion 22 from which at least a part of the organic group has been removed is selectively etched back. For example, C
SOG from which organic groups are removed by RIE (Reactive Ion Etching) in which HF 3 and CH 4 gases are mixed at about 1: 1
Has an etch rate about 1.5 to 2.0 times that of organic SOG. Therefore, it is sufficiently possible to leave the organic SOG film only inside the trench.
【００１２】（Ｄ）トレンチのアスペクトを減じた後、
埋め込み性に優れなおかつ熱酸化膜に近い特性を持つＨ
ＤＰ（Ｈｉｇｈ Ｄｅｎｓｉｔｙ Ｐｌａｓｍａ）ＣＶ
Ｄシリコン酸化膜２４を４００ｎｍ程度、堆積する。こ
れによりトレンチをボイド無く絶縁物質で埋め込むこと
ができる。また有機ＳＯＧ膜はトレンチ底部にしか堆積
していないので、後工程で加工されるのはＨＤＰ−ＣＶ
Ｄシリコン酸化膜２４だけであり、洗浄液の浸食の可能
性も無い。(D) After reducing the aspect of the trench,
H with excellent burying properties and characteristics close to thermal oxide films
DP (High Density Plasma) CV
A D silicon oxide film 24 is deposited to a thickness of about 400 nm. Thus, the trench can be filled with the insulating material without voids. Also, since the organic SOG film is deposited only on the bottom of the trench, it is processed in a subsequent step by HDP-CV.
Since only the D silicon oxide film 24 is used, there is no possibility of erosion of the cleaning liquid.
【００１３】（Ｅ）その後、ＣＭＰ（化学的機械研磨
法）で表面を平坦化し、次にＳｉＮを除去する。(E) Thereafter, the surface is flattened by CMP (Chemical Mechanical Polishing), and then SiN is removed.
【００１４】以上のように、本実施形態では、ＨＤＰに
よりシリコン酸化膜を堆積している。ＨＤＰで堆積した
膜は、他の方法、例えば普通のプラズマＴＥＯＳや、常
圧ＣＶＤ法で堆積したＳｉＯ2と比較して埋め込み性が
良く、また膜質が良い（ウエットエッチレートが小さ
い）のが特徴である。ＳＯＧと比べると、埋め込み性は
劣るものの、はるかに膜質が良いのが特徴であり、その
ために（トレンチ内部に堆積した有機膜の）キャップ膜
としての能力が高くなる。As described above, in this embodiment, the silicon oxide film is deposited by HDP. Films deposited by HDP are characterized by a better embedding and better film quality (small wet etch rate) than other methods, such as ordinary plasma TEOS or SiO 2 deposited by atmospheric pressure CVD. It is. Although the embedding property is inferior to that of SOG, it is characterized by much better film quality, and therefore, the ability as a cap film (of the organic film deposited inside the trench) is enhanced.
【００１５】[0015]
【発明の効果】このように本発明では、高アスペクト比
のトレンチをシリコン酸化膜でボイド無く埋め込むこと
により、トランジスター素子分離領域が確実に電気的に
絶縁される。その結果、ＭＯＳＦＥＴ等の半導体装置の
信頼性が向上する。As described above, according to the present invention, the transistor isolation region is reliably electrically insulated by filling the trench having a high aspect ratio with a silicon oxide film without voids. As a result, the reliability of a semiconductor device such as a MOSFET is improved.
【図１】従来の素子分離領域形成方法を示す工程断面図FIG. 1 is a process sectional view showing a conventional method for forming an element isolation region.
【図２】課題を示す工程断面図FIG. 2 is a process sectional view showing a problem.
【図３】本実施形態である素子分離領域形成方法を示す
工程断面図FIG. 3 is a process cross-sectional view showing the element isolation region forming method according to the embodiment;
２ シリコン基板 ４ シリコン窒化膜 ６ ＨＳＱ膜 ８ 減圧ＣＶＤシリコン酸化膜 １０ 洗浄により選択的に除去された部分 ２０ 有機ＳＯＧ膜 ２２ 有機基を除去された有機ＳＯＧ膜 ２４ ＨＤＰ−ＣＶＤシリコン酸化膜 Reference Signs List 2 silicon substrate 4 silicon nitride film 6 HSQ film 8 low-pressure CVD silicon oxide film 10 part selectively removed by cleaning 20 organic SOG film 22 organic SOG film from which organic groups have been removed 24 HDP-CVD silicon oxide film
Claims (1)
シリコン酸化膜を形成する工程と、 前記基板表面よりも下でトレンチ底部よりも上の部分ま
で、前記シリコン酸化膜の有機基を除去する工程と、 前記有機基を取り去った部分の前記シリコン酸化膜を除
去する工程と、 高密度プラズマＣＶＤ法により、前記トレンチに形成さ
れた前記シリコン酸化膜上にあらたにシリコン酸化膜を
形成する工程とを有する、半導体装置の製造方法。A step of forming a trench in a semiconductor substrate; a step of forming a silicon oxide film having an organic group on the substrate and in the trench; and forming a silicon oxide film below the substrate surface and above a trench bottom. Removing the organic group of the silicon oxide film up to the portion; removing the silicon oxide film of the portion from which the organic group has been removed; and forming the silicon oxide film formed in the trench by high-density plasma CVD. Forming a new silicon oxide film on the film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10352716A JP2000183150A (en) | 1998-12-11 | 1998-12-11 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10352716A JP2000183150A (en) | 1998-12-11 | 1998-12-11 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2000183150A true JP2000183150A (en) | 2000-06-30 |
Family
ID=18425952
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10352716A Pending JP2000183150A (en) | 1998-12-11 | 1998-12-11 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2000183150A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001203263A (en) * | 2000-01-20 | 2001-07-27 | Hitachi Ltd | Method for manufacturing semiconductor integrated circuit device and semiconductor integrated circuit device |
| US6566229B2 (en) * | 2001-03-05 | 2003-05-20 | Samsung Electronics Co., Ltd. | Method of forming an insulating layer in a trench isolation type semiconductor device |
| US7052971B2 (en) | 2001-07-13 | 2006-05-30 | Kabushiki Kaisha Toshiba | Method for manufacturing semiconductor device |
| US7105397B2 (en) | 2003-11-28 | 2006-09-12 | Kabushiki Kaisha Toshiba | Semiconductor device and method of fabricating the same |
| KR100816749B1 (en) | 2006-07-12 | 2008-03-27 | 삼성전자주식회사 | Device Isolation Layer, Nonvolatile Memory Device Having The Device Isolation Layer, and Methods Of Forming The Device Isolation Layer and The Semiconductor Device |
| JP2008091368A (en) * | 2006-09-29 | 2008-04-17 | Toshiba Corp | Semiconductor device and manufacturing method thereof |
| KR20100121437A (en) | 2009-05-08 | 2010-11-17 | 르네사스 일렉트로닉스 가부시키가이샤 | Semiconductor device and method of manufacturing the same |
-
1998
- 1998-12-11 JP JP10352716A patent/JP2000183150A/en active Pending
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7060589B2 (en) * | 2000-01-20 | 2006-06-13 | Hitachi, Ltd. | Method for manufacturing a semiconductor integrated circuit device that includes covering the bottom of an isolation trench with spin-on glass and etching back the spin-on glass to a predetermined depth |
| JP2001203263A (en) * | 2000-01-20 | 2001-07-27 | Hitachi Ltd | Method for manufacturing semiconductor integrated circuit device and semiconductor integrated circuit device |
| US6566229B2 (en) * | 2001-03-05 | 2003-05-20 | Samsung Electronics Co., Ltd. | Method of forming an insulating layer in a trench isolation type semiconductor device |
| US7052971B2 (en) | 2001-07-13 | 2006-05-30 | Kabushiki Kaisha Toshiba | Method for manufacturing semiconductor device |
| US7105397B2 (en) | 2003-11-28 | 2006-09-12 | Kabushiki Kaisha Toshiba | Semiconductor device and method of fabricating the same |
| US7416987B2 (en) | 2003-11-28 | 2008-08-26 | Kabushiki Kaisha Toshiba | Semiconductor device and method of fabricating the same |
| US7674685B2 (en) | 2006-07-12 | 2010-03-09 | Samsung Electronics Co, Ltd. | Semiconductor device isolation structures and methods of fabricating such structures |
| KR100816749B1 (en) | 2006-07-12 | 2008-03-27 | 삼성전자주식회사 | Device Isolation Layer, Nonvolatile Memory Device Having The Device Isolation Layer, and Methods Of Forming The Device Isolation Layer and The Semiconductor Device |
| JP2008091368A (en) * | 2006-09-29 | 2008-04-17 | Toshiba Corp | Semiconductor device and manufacturing method thereof |
| KR20100121437A (en) | 2009-05-08 | 2010-11-17 | 르네사스 일렉트로닉스 가부시키가이샤 | Semiconductor device and method of manufacturing the same |
| US8384187B2 (en) | 2009-05-08 | 2013-02-26 | Renesas Electronics Corporation | Semiconductor device with shallow trench isolation |
| US9029237B2 (en) | 2009-05-08 | 2015-05-12 | Renesas Electronics Corporation | Semiconductor device and method of manufacturing the same |
| CN105355540A (en) * | 2009-05-08 | 2016-02-24 | 瑞萨电子株式会社 | Semiconductor device and method of manufacturing the same |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6071805A (en) | Air gap formation for high speed IC processing | |
| US6057226A (en) | Air gap based low dielectric constant interconnect structure and method of making same | |
| US20010006839A1 (en) | Method for manufacturing shallow trench isolation in semiconductor device | |
| US5981402A (en) | Method of fabricating shallow trench isolation | |
| US20080242046A1 (en) | Method on Forming an Isolation Film or a Semiconductor Device | |
| US20040169005A1 (en) | Methods for forming a thin film on an integrated circuit including soft baking a silicon glass film | |
| US6649488B2 (en) | Method of shallow trench isolation | |
| KR19990075821A (en) | Slow trench isolation method | |
| KR19980063317A (en) | Device Separation Method of Semiconductor Device | |
| JP2000183150A (en) | Manufacture of semiconductor device | |
| US20040038493A1 (en) | Method for forming a trench isolation structure | |
| US6838356B2 (en) | Method of forming a trench isolation | |
| US7154159B2 (en) | Trench isolation structure and method of forming the same | |
| JPH10116904A (en) | Manufacture of semiconductor device | |
| KR100500439B1 (en) | method for fabricating semiconductor device with gate spacer of positive slope | |
| KR100688758B1 (en) | Method for forming gap fill of metal line for semiconductor | |
| JPH08330410A (en) | Element isolating method, element isolating structure and semiconductor device | |
| JPH11150179A (en) | Manufacture of trench isolation type semiconductor device | |
| JP2000031489A (en) | Manufacturing semiconductor device | |
| KR100313785B1 (en) | Method for forming interlayer dielectric of semiconductor device | |
| KR100875670B1 (en) | Device Separating Method of Semiconductor Device | |
| KR100568030B1 (en) | Shallow Trench Isolation Method For Semiconductor Devices | |
| KR100245090B1 (en) | Method of forming an element isolation film in a semiconductor device | |
| JPH05235157A (en) | Manufacture of semiconductor device | |
| KR100517351B1 (en) | Method for manufacturing device isolation barrier of semiconductor device |