JP2000091590A - Manufacture of thin-film semiconductor device - Google Patents
Manufacture of thin-film semiconductor deviceInfo
- Publication number
- JP2000091590A JP2000091590A JP10262130A JP26213098A JP2000091590A JP 2000091590 A JP2000091590 A JP 2000091590A JP 10262130 A JP10262130 A JP 10262130A JP 26213098 A JP26213098 A JP 26213098A JP 2000091590 A JP2000091590 A JP 2000091590A
- Authority
- JP
- Japan
- Prior art keywords
- film
- plasma
- semiconductor device
- semiconductor
- gas
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
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- Formation Of Insulating Films (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は薄膜トランジスタ
（ＴＦＴ）等に代表される薄膜半導体装置の製造方法に
関する。更に詳しくは、本願発明は高性能で信頼性に富
む薄膜半導体装置を４５０℃程度以下の比較的低温にて
製造する方法に関する。The present invention relates to a method for manufacturing a thin film semiconductor device represented by a thin film transistor (TFT) and the like. More specifically, the present invention relates to a method for manufacturing a high-performance and highly reliable thin film semiconductor device at a relatively low temperature of about 450 ° C. or less.
【０００２】[0002]
【従来の技術】多結晶硅素薄膜トランジスタ（ｐ−Ｓｉ
ＴＦＴ）に代表される半導体装置を安価な汎用ガラス
基板を使用し得る４５０℃程度以下の低温にて製造する
場合、従来以下の如き製造方法が取られて居た。まずエ
キシマレーザー照射法などで多結晶硅素膜（ｐ−Ｓｉ
膜）形成した後、ゲート絶縁膜と成る酸化硅素膜を化学
気相堆積法（ＣＶＤ法）や物理気相堆積法（ＰＶＤ法）
にて１００ｎｍ程度に形成する。次にタンタル等でゲー
ト電極を作成して、金属（ゲート電極）−酸化膜（ゲー
ト絶縁膜）−半導体（多結晶硅素膜）から成る電界効果
トランジスタ（ＭＯＳ−ＦＥＴ）を構成せしめて居た。2. Description of the Related Art Polycrystalline silicon thin film transistors (p-Si
When a semiconductor device typified by a TFT is manufactured at a low temperature of about 450 ° C. or less at which an inexpensive general-purpose glass substrate can be used, the following manufacturing method has conventionally been adopted. First, a polycrystalline silicon film (p-Si
After the film is formed, a silicon oxide film serving as a gate insulating film is formed by chemical vapor deposition (CVD) or physical vapor deposition (PVD).
To a thickness of about 100 nm. Next, a gate electrode is made of tantalum or the like, and a field effect transistor (MOS-FET) composed of a metal (gate electrode) -oxide film (gate insulating film) -semiconductor (polycrystalline silicon film) has been formed.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら此等従来
の半導体装置の製造方法では半導体膜と酸化硅素膜との
界面が汚れていたり、界面準位が大きい等の多くの問題
を抱えて居り、その界面特質が窮めて貧弱で有るとの課
題を有して居た。斯くした事実に則し、従来の製造方法
にてｐ−Ｓｉ ＴＦＴ等の半導体装置を製造すると、完
成した半導体装置はその電気特性が悪いにのみならず、
使用途上に経時劣化が生ずる等の信頼性にも課題を有し
て居た。However, the conventional method for manufacturing a semiconductor device has many problems such as contamination of the interface between the semiconductor film and the silicon oxide film and a large interface state. There was a problem that the interface characteristics were poor and poor. In accordance with such a fact, when a semiconductor device such as a p-Si TFT is manufactured by a conventional manufacturing method, not only the completed semiconductor device has poor electric characteristics, but also
There is also a problem in reliability such as deterioration over time during use.
【０００４】そこで本発明は上述の諸事情を鑑み、その
目的とする所は４５０℃程度以下との低温工程で清浄な
界面を有する優良な半導体装置を製造する方法を提供す
る事に有る。The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a method of manufacturing an excellent semiconductor device having a clean interface in a low-temperature process of about 450 ° C. or less.
【０００５】[0005]
【課題を解決するための手段】本発明は絶縁性物質上に
形成された半導体膜と、この半導体膜上に形成された酸
化硅素に代表される絶縁膜の二者を構成要件として含ん
で居る半導体装置の製造方法に関し、少なくとも以下の
二工程を以てその特徴と為す。即ち半導体膜を形成する
第一工程と、４５０℃程度以下との比較的低温にて絶縁
膜を半導体膜上に形成する第二工程とで有る。第二工程
では希ガスと酸化性気体との混合気体から成るプラズマ
を第一工程で得られた半導体膜に照射した後に、連続し
てプラズマ化学気相堆積法（ＰＥＣＶＤ法）にて絶縁膜
を堆積する工程を少なくとも含んで居る。The present invention includes, as constituent elements, a semiconductor film formed on an insulating material and an insulating film typified by silicon oxide formed on the semiconductor film. The method for manufacturing a semiconductor device is characterized by at least the following two steps. That is, there are a first step of forming a semiconductor film and a second step of forming an insulating film on the semiconductor film at a relatively low temperature of about 450 ° C. or lower. In the second step, after irradiating the semiconductor film obtained in the first step with plasma composed of a mixed gas of a rare gas and an oxidizing gas, the insulating film is continuously formed by plasma enhanced chemical vapor deposition (PECVD). At least the step of depositing is included.
【０００６】[0006]
【発明の実施の形態】まず本発明は第一工程としてガラ
ス基板や三次元半導体装置の層間絶縁膜等の縁性物質上
に多結晶硅素（ｐ−Ｓｉ）に代表される半導体膜を形成
する。この半導体膜は単結晶状態に有っても、多結晶状
態に有っても、或いは非晶質状態に有っても構わない
が、多結晶状態に有る時に本願発明は殊の外その効果を
示す。此は本願発明が半導体膜と絶縁膜との界面に存在
する捕獲準位（界面準位）を低減せしめると共に、結晶
粒と結晶粒との間に位置する捕獲準位（粒界準位）をも
低減せしめるが故で有る。言う迄もなく界面準位は結晶
状態に拘わらず半導体膜と絶縁膜との接合界面には必ず
存在する。この界面準位を低減させるから、本願発明は
半導体膜の状態の如何に拘わらず有効なので有る。一
方、多結晶膜に対しては此の効果に加え、粒界準位を減
らすとの効果も認められる。半導体膜は硅素（Ｓｉ）や
硅素ゲルマニウム（ＳｉｘＧｅ１−ｘ：０＜ｘ＜１）等
如何なる半導体物質で有っても構わないが、簡便に良好
なＭＯＳ界面を構成するとの視点からは、硅素単体や硅
素をその主構成元素（硅素原子構成比が８０％程度以
上）として居る半導体物質が優れて居る。半導体膜は物
理気相堆積法（ＰＶＤ法）や化学気相堆積法（ＣＶＤ
法）等の気相堆積法等で形成される。ＰＶＤ法にはスパ
ッター法や蒸着法等が考えられる。又ＣＶＤ法には常圧
化学気相堆積法（ＡＰＣＶＤ法）や低圧化学気相堆積法
（ＬＰＣＶＤ法）、プラズマ化学気相堆積法（ＰＥＣＶ
Ｄ法）等が使用され得る。気相堆積法で形成された半導
体膜は、堆積直後には通常多結晶状態か非晶質状態に、
又は此等の混合状態に有る。多結晶状態に有る薄膜は多
結晶膜と称され、非晶質状態や混合状態に有る薄膜は非
晶質膜や混晶質膜と其々称される。半導体装置の能動部
（電界効果型トランジスタのソース・ドレイン領域やチ
ャンネル形成領域、及びバイポーラ型トランジスタのエ
ミッター・ベース・コレクター領域）としては堆積直後
に得られた多結晶膜をその侭使用する事も可能で有る。
此とは対照的に非晶質膜や混晶質膜を結晶化したり、或
いは多結晶膜を再結晶化するなどして、新たな多結晶膜
を得た後に此等を能動部として使用する事も可能で有
る。結晶化や再結晶化を簡単に行うにはレーザー照射や
急速熱処理が用いられる。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In the present invention, a semiconductor film typified by polycrystalline silicon (p-Si) is first formed as a first step on an edge material such as a glass substrate or an interlayer insulating film of a three-dimensional semiconductor device. . This semiconductor film may be in a single-crystal state, a polycrystalline state, or an amorphous state. However, when the semiconductor film is in the polycrystalline state, the present invention has no particular effect. Is shown. This is because the present invention reduces the trap level (interface level) existing at the interface between the semiconductor film and the insulating film, and reduces the trap level (grain boundary level) located between crystal grains. Is also reduced. Needless to say, the interface state always exists at the bonding interface between the semiconductor film and the insulating film regardless of the crystal state. Since this interface state is reduced, the present invention is effective regardless of the state of the semiconductor film. On the other hand, for a polycrystalline film, in addition to this effect, an effect of reducing the grain boundary level is also recognized. Semiconductor film silicon (Si) or silicon germanium (Si x Ge 1-x: 0 <x <1) or the like but may be there in any semiconductor material, from the viewpoint of constituting a simple good MOS interface Semiconductor materials containing silicon alone or silicon as its main constituent element (silicon atomic composition ratio is about 80% or more) are excellent. Semiconductor films can be formed by physical vapor deposition (PVD) or chemical vapor deposition (CVD).
Method) or the like. As the PVD method, a sputtering method, an evaporation method, or the like can be considered. The CVD method includes atmospheric pressure chemical vapor deposition (APCVD), low pressure chemical vapor deposition (LPCVD), and plasma chemical vapor deposition (PECV).
D method) can be used. A semiconductor film formed by a vapor deposition method is usually in a polycrystalline state or an amorphous state immediately after deposition,
Or these are in a mixed state. A thin film in a polycrystalline state is called a polycrystalline film, and a thin film in an amorphous state or a mixed state is called an amorphous film or a mixed crystalline film, respectively. For the active part of the semiconductor device (source / drain region and channel formation region of a field effect transistor, and emitter / base / collector region of a bipolar transistor), a polycrystalline film obtained immediately after deposition may be used as it is. It is possible.
In contrast, a new polycrystalline film is obtained by crystallizing an amorphous film or mixed crystal film, or recrystallizing a polycrystalline film, and then using these as an active part. Things are possible. Laser irradiation or rapid heat treatment is used to easily perform crystallization or recrystallization.
【０００７】次に第二工程として絶縁膜を半導体膜上に
形成する。絶縁膜の形成は高くとも４５０℃程度以下の
温度、通常は４００℃程度以下の温度で行われる。此は
本願が対象として居る半導体装置を非晶質硅素薄膜半導
体装置（ａ−Ｓｉ ＴＦＴ）が製造される汎用ガラス基
板や、プラスチック基板等の耐熱性の乏しい基板上に製
造する事を前提として居るからで有る。此の絶縁膜をＭ
ＯＳ−ＦＥＴのゲート絶縁膜として利用する。絶縁膜は
ヘリウム（Ｈｅ）やネオン（Ｎｅ）、アルゴン（Ａ
ｒ）、クリプトン（Ｋｒ）、キセノン（Ｘｅ）と云った
希ガスと、酸素（Ｏ２）や水（Ｈ２Ｏ）、亜酸化窒素
（Ｎ２Ｏ）と云った酸化性気体との混合気体から成るプ
ラズマを、第一工程で形成された半導体膜に照射して半
導体膜表層部に第一のプラズマ酸化膜を形成した後に、
更に連続してプラズマ化学気相堆積法（ＰＥＣＶＤ法）
にて第二の堆積絶縁膜を堆積する事で形成される。第一
のプラズマ酸化膜は半導体膜表面に４ｎｍ程度から１０
ｎｍ程度の厚みを有して形成される。通常の薄膜半導体
装置ではゲート絶縁膜として３０ｎｍ程度から１５０ｎ
ｍ程度の厚みを必要とするので、第二の堆積絶縁膜は残
りの厚みを受け持ち、その値は２０ｎｍ程度から１４６
ｎｍ程度と成る。第一のプラズマ酸化膜が４ｎｍ程度以
上有れば界面遷移領域全体が清浄と化し、酸化膜捕獲準
位や界面捕獲準位と言った準位が低減されて界面特性が
著しく改善される。此はプラズマ酸化に依り界面が半導
体膜の内部に移動し、元の汚れた界面が界面遷移領域の
外に出る事に由来する。第一工程で形成された半導体膜
が硅素を主体としてたから、此の半導体膜の酸化に依っ
て得られた第一のプラズマ酸化膜の主構成物質は酸化硅
素（ＳｉＯｘ：０＜ｘ≦２）と成る。第二の堆積絶縁膜
としては酸化硅素（ＳｉＯｘ：０＜ｘ≦２）や窒化硅素
（Ｓｉ３Ｎｘ：０＜ｘ≦４）、或いは此等の積層膜が適
して居る。Next, as a second step, an insulating film is formed on the semiconductor film. The formation of the insulating film is performed at a temperature of at most about 450 ° C., usually at a temperature of about 400 ° C. or less. This is based on the premise that the semiconductor device to which the present invention is applied is manufactured on a general-purpose glass substrate on which an amorphous silicon thin film semiconductor device (a-Si TFT) is manufactured, or on a substrate having poor heat resistance such as a plastic substrate. From. This insulation film is M
Used as a gate insulating film of an OS-FET. The insulating film is made of helium (He), neon (Ne), argon (A
r) a mixed gas of a rare gas such as krypton (Kr) or xenon (Xe) and an oxidizing gas such as oxygen (O 2 ), water (H 2 O) or nitrous oxide (N 2 O) After forming the first plasma oxide film on the surface layer of the semiconductor film by irradiating the semiconductor film formed in the first step with plasma comprising
Further continuous plasma enhanced chemical vapor deposition (PECVD)
Is formed by depositing a second deposited insulating film. The first plasma oxide film has a thickness of about 4 nm to 10
It is formed having a thickness of about nm. In a normal thin film semiconductor device, a gate insulating film is formed from about 30 nm to 150 n.
m, the thickness of the second deposited insulating film covers the remaining thickness, and the value ranges from about 20 nm to 146.
nm. If the first plasma oxide film has a thickness of about 4 nm or more, the entire interface transition region is cleaned, and the levels such as the oxide film capture level and the interface capture level are reduced, and the interface characteristics are significantly improved. This is because the interface moves into the semiconductor film due to the plasma oxidation, and the original dirty interface goes out of the interface transition region. Since the semiconductor film formed in the first step was mainly composed of silicon, the main constituent material of the first plasma oxide film obtained by oxidation of this semiconductor film was silicon oxide (SiO x : 0 <x ≦ 2). ). As the second deposited insulating film, silicon oxide (SiO x : 0 <x ≦ 2), silicon nitride (Si 3 N x : 0 <x ≦ 4), or a stacked film of these is suitable.
【０００８】希ガスと酸化性気体との混合気体から成る
プラズマの半導体膜への照射はプラズマ化学気相堆積装
置（ＰＥＣＶＤ装置）等のプラズマ生成装置にて行う。
プラズマ源としてはラジオ波（ｒｆ波：１３．５６ＭＨ
ｚや此の正数倍の周波数で２７．１２ＭＨｚ等）や超高
周波（ＶＨＦ波：１００ＭＨｚ程度から数百ＭＨｚの周
波数を有する電磁波）、或いはマイクロ波（２．４５Ｇ
Ｈｚや８．３ＧＨｚ等のＧＨｚ帯の周波数を有する電磁
波）が使用される。超高周波やマイクロ波を用いればプ
ラズマ密度が上がるので、酸化が迅速に進行する。しか
しながら５５０ｍｍ×６５０ｍｍと云った様な大型基板
に対応する汎用ＰＥＣＶＤ装置を使用出来るとの視点か
らは１３．５６ＭＨｚに代表されるラジオ波の使用が最
適で有る。混合プラズマの照射を行う際には、希ガスと
酸化性気体との混合気体中に占める酸化性気体の割合を
１％程度以上１０％程度以下とする。特にラジオ波をプ
ラズマ源としているＰＥＣＶＤ装置を使用する場合には
プラズマ密度の低下に応じて、酸化性気体の割合を１％
程度以上６％程度未満とせねばならない。これは本願発
明が希ガスの励起状態を多量に生成し、此の励起状態か
らのエネルギー遷移を以て酸化性気体の原子状活性種
（酸素原子活性種Ｏ＊や水酸基活性種ＯＨ＊、一酸化窒
素活性種ＮＯ＊、窒素原子活性種Ｎ＊）を生成し、半導
体膜表面の酸化乃至は窒化やニトロ化を促進するとの原
理に基づいて居るからで有る。従来のプラズマ酸化で
は、例えば純酸素のプラズマを用いて多結晶硅素膜表面
の酸化を行って居た。此の場合、プラズマ中に発生する
活性種の殆ど総てが酸素分子の活性種（Ｏ２ ＊）で有
る。本願の様に硅素等の半導体物質表面や多結晶性半導
体膜の粒界部を４５０℃程度未満の低温で酸化させる場
合、酸素原子が半導体構成原子間に効果的に入り込まね
ばならない。酸素分子の活性種では分子が原子に解離す
る必要が有り、此の解離エネルギーの多くは半導体膜か
ら熱的に供給されて居る。それ故、基板温度が４５０℃
程度未満との低温では酸化の進行が著しく抑制されて仕
舞うので有る。此に対して本願ではプラズマ中に希ガス
の活性種を多量に生成する。希ガスの活性種は励起エネ
ルギーが２０ｅＶ程度と高い。一方、例えば酸素分子が
二つの酸素原子に解離し、その内の一つの酸素原子が第
一励起状態に迄達する総エネルギーは凡そ１８ｅＶで有
る。従って酸素分子が希ガスの励起種からエネルギーを
受け取れば、容易に酸素原子の第一励起種、即ち酸素原
子活性種が生成される。斯うして生成された酸素原子活
性種は化学的に窮めて活性で、４５０℃乃至は４００℃
程度未満との低温で有っても半導体原子の格子間に容易
に入り込んだり、或いは粒界部に於ける不対結合対を終
端する事が出来、斯くして半導体膜の低温での酸化が進
行する訳で有る。此の場合、酸化性気体の割合が１％程
度未満ではプラズマ中の酸化性気体原子活性種の数が少
なく、逆に１０％程度以上だと希ガスの活性種の数が減
少して酸化気体分子活性種が増えて仕舞う為、矢張り酸
化性原子活性種の数は減って仕舞う。取り分けプラズマ
密度の低いラジオ波を用いたプラズマでは酸化性気体原
子活性種の数を多くする必要が有り、混合気体中に於け
る酸化性気体の割合を１％程度以上６％程度未満とせね
ばならない。斯うすればｒｆプラズマで有っても界面準
位が低い良質な酸化膜を、比較的速い成膜速度で形成出
来る訳で有る。本願発明の半導体装置の製造工程中でプ
ラズマ酸化工程を除いた最高温度は半導体膜堆積時で凡
そ４２５℃程度と成って居る。此の半導体装置製造工程
中での最高温度以下、或いは半導体膜堆積時の温度以
下、即ち４２５℃程度以下の低温で第二工程を行うに
は、低温化に伴う酸化反応速度の低下を補償する為に酸
化性気体原子活性種の数を最大とせねば成らず、故に混
合気体中に於ける酸化性気体の割合を１．５％程度以上
４．５％程度未満とする必要が有る。更に結晶粒界が存
在する多結晶性半導体膜に於いては、粒界での乱れた結
合を解き放して此等に酸素を新たに結合させる必要が有
る為、優良な半導体装置を得るには混合気体中に於ける
酸化性気体の割合を２％程度以上４％程度未満とするの
が好ましい。尚、低温でのプラズマ酸化を促進するには
プラズマ酸化の直前に基板を希釈沸酸水溶液等に浸し
て、半導体膜表面や粒界部を水素で終端化しておく。斯
うすると半導体膜表面等は秩序有る状態と成っており、
乱れた結合を解く必要がないので酸化が容易に進行す
る。Irradiation of the semiconductor film with plasma composed of a mixed gas of a rare gas and an oxidizing gas is performed by a plasma generation apparatus such as a plasma chemical vapor deposition apparatus (PECVD apparatus).
As a plasma source, radio waves (rf waves: 13.56 MH)
z or a positive multiple of this frequency, such as 27.12 MHz), a very high frequency (VHF wave: an electromagnetic wave having a frequency of about 100 MHz to several hundred MHz), or a microwave (2.45 G).
Hz or an electromagnetic wave having a frequency in the GHz band such as 8.3 GHz). If an ultra-high frequency or microwave is used, the plasma density increases, so that oxidation proceeds rapidly. However, from the viewpoint that a general-purpose PECVD apparatus corresponding to a large substrate of 550 mm × 650 mm can be used, the use of radio waves represented by 13.56 MHz is optimal. When performing the irradiation of the mixed plasma, the ratio of the oxidizing gas in the mixed gas of the rare gas and the oxidizing gas is set to about 1% or more and about 10% or less. In particular, when a PECVD apparatus using a radio wave as a plasma source is used, the ratio of the oxidizing gas is reduced to 1% according to the decrease in the plasma density.
It should be at least about 6% and less than about 6%. This is because the present invention generates a large amount of the excited state of the rare gas, and the energy transition from this excited state causes the atomic active species (oxygen active species O * , hydroxyl active species OH * , nitric oxide) of the oxidizing gas. This is because it is based on the principle that active species NO * and nitrogen atom active species N * ) are generated and oxidation or nitridation or nitration of the semiconductor film surface is promoted. In the conventional plasma oxidation, the surface of the polycrystalline silicon film is oxidized using, for example, plasma of pure oxygen. In this case, almost all of the active species generated in the plasma are active species of oxygen molecules (O 2 * ). When a surface of a semiconductor material such as silicon or a grain boundary of a polycrystalline semiconductor film is oxidized at a low temperature of less than about 450 ° C. as in the present application, oxygen atoms must effectively enter between semiconductor constituent atoms. Active species of oxygen molecules need to be dissociated into atoms, and much of this dissociation energy is thermally supplied from the semiconductor film. Therefore, the substrate temperature is 450 ° C
At a low temperature of less than the extent, the progress of oxidation is significantly suppressed and the operation is performed. On the other hand, in the present application, a large amount of a rare gas active species is generated in the plasma. The active energy of the rare gas has a high excitation energy of about 20 eV. On the other hand, for example, an oxygen molecule dissociates into two oxygen atoms, and the total energy of one of the oxygen atoms reaching the first excited state is about 18 eV. Therefore, when the oxygen molecule receives energy from the excited species of the rare gas, the first excited species of oxygen atoms, that is, oxygen atom active species is easily generated. The oxygen atom active species thus produced is chemically distressingly active, 450 ° C. to 400 ° C.
Even at a low temperature of less than the order, it is possible to easily penetrate into the lattices of the semiconductor atoms, or terminate unpaired bonding pairs at the grain boundary, thus oxidizing the semiconductor film at a low temperature. It is going to progress. In this case, if the ratio of the oxidizing gas is less than about 1%, the number of the oxidizing gas atomic active species in the plasma is small, and if it is about 10% or more, the number of the rare gas active species decreases and the oxidizing gas decreases. Since the number of molecular active species increases, the number of oxidizing atomically active species decreases and the number of molecular active species decreases. In particular, in a plasma using a radio wave having a low plasma density, it is necessary to increase the number of oxidizing gas atomic active species, and the ratio of the oxidizing gas in the mixed gas must be about 1% or more and less than about 6%. . In this case, a high-quality oxide film having a low interface state can be formed at a relatively high film formation rate even with rf plasma. The maximum temperature excluding the plasma oxidation step in the manufacturing process of the semiconductor device of the present invention is about 425 ° C. when the semiconductor film is deposited. In order to perform the second step at a low temperature of not more than the maximum temperature in the semiconductor device manufacturing process or the temperature at the time of depositing the semiconductor film, that is, about 425 ° C. or less, a reduction in the oxidation reaction rate accompanying the low temperature is compensated. Therefore, the number of oxidizing gas atomic active species must be maximized. Therefore, the ratio of the oxidizing gas in the mixed gas must be about 1.5% or more and less than about 4.5%. Further, in a polycrystalline semiconductor film having a crystal grain boundary, it is necessary to release the disordered bond at the grain boundary and newly bond oxygen to the polycrystalline semiconductor film. It is preferable that the ratio of the oxidizing gas in the gas be about 2% or more and less than about 4%. In order to promote low-temperature plasma oxidation, the substrate is immersed in a dilute aqueous hydrofluoric acid solution or the like immediately before the plasma oxidation to terminate the semiconductor film surface or the grain boundary with hydrogen. In this case, the semiconductor film surface and the like are in an ordered state,
Oxidation proceeds easily because there is no need to break the disordered bonds.
【０００９】希ガスと酸化性気体との混合気体から成る
プラズマを半導体膜に照射する時の基板温度は高ければ
高い程、形成される酸化膜の品質が向上し、酸化速度も
速く成る。比較的良質な酸化膜を得るには基板温度は低
くとも１００℃程度以上で有る事が望ましい。先にも述
べた様に４５０℃程度以下ならば大型汎用ガラス基板の
使用が可能と成り、半導体装置製造工程中での最高温度
程度以下、即ち４２５℃程度以下の低温で有れば、先の
大型ガラス基板でその厚みが０．７ｍｍ程度以下と云っ
た、非晶質硅素薄膜半導体装置の製造に使用されて居る
総ての汎用ガラス基板を自由に使用出来る様に成る。The higher the substrate temperature when irradiating the semiconductor film with a plasma comprising a mixed gas of a rare gas and an oxidizing gas, the higher the quality of the formed oxide film and the faster the oxidation rate. In order to obtain a relatively high quality oxide film, it is desirable that the substrate temperature be at least about 100 ° C. or more. As described above, a large general-purpose glass substrate can be used if the temperature is about 450 ° C. or less, and if the temperature is as low as about the maximum temperature in the semiconductor device manufacturing process, that is, about 425 ° C. or less, It is possible to freely use all general-purpose glass substrates used for manufacturing an amorphous silicon thin film semiconductor device having a large glass substrate thickness of about 0.7 mm or less.
【００１０】半導体膜表層部に第一のプラズマ酸化膜を
形成した後、真空を破る事無く連続して第二の堆積絶縁
膜を堆積する。ゲート絶縁膜内での不用意な準位形成や
ゲート絶縁膜への不純物混入等の不具合を避ける為に
も、プラズマ酸化が終了した後直ちに、長くとも５分程
度以内に第二の堆積絶縁膜の堆積を開始する。プラズマ
酸化終了から絶縁膜堆積開始迄の間、プラズマ処理室は
プラズマを立てる事を除いて絶縁膜堆積時と同一条件と
しておく。斯様な工程を実行するには、プラズマ酸化に
於ける基板温度と絶縁膜堆積に於ける基板温度とが略同
等でなければ成らない。即ち、両者の温度差は大きくと
も３０℃程度未満とする。斯うする事で先の短時間内で
有っても基板温度は平衡に達し、均質な絶縁膜を安定的
に堆積する事が可能と成る。After forming the first plasma oxide film on the surface of the semiconductor film, a second deposited insulating film is continuously deposited without breaking vacuum. Immediately after the plasma oxidation is completed, the second deposited insulating film should be formed within 5 minutes at most after the plasma oxidation in order to avoid problems such as inadvertent formation of levels in the gate insulating film and contamination of the gate insulating film with impurities. Start the deposition of. During the period from the end of the plasma oxidation to the start of the deposition of the insulating film, the plasma processing chamber is kept under the same conditions as the deposition of the insulating film except that a plasma is formed. To perform such a process, the substrate temperature in plasma oxidation and the substrate temperature in insulating film deposition must be substantially equal. That is, the temperature difference between the two is at most less than about 30 ° C. By doing so, the substrate temperature reaches an equilibrium even within the short time, and a uniform insulating film can be stably deposited.
【００１１】堆積絶縁膜として酸化硅素を利用する時に
は原料気体としてモノシラン（ＳｉＨ４）やジシラン
（Ｓｉ２Ｈ６）、ジクロールシラン（Ｓｉ２Ｈ２Ｃ
ｌ２）等のシラン気体、乃至はＴＥＯＳ（Ｓｉ（０Ｃ２
Ｈ５）４）等の硅素含有化合物と、酸素（Ｏ２）や亜酸
化窒素（Ｎ２Ｏ）等の酸化性気体とを用いる。窒化硅素
を利用する時には上述のシラン気体と、アンモニア（Ｎ
Ｈ３）や窒素（Ｎ２）等の窒化性気体とを用いる。When silicon oxide is used as the deposited insulating film, monosilane (SiH 4 ), disilane (Si 2 H 6 ), and dichlorosilane (Si 2 H 2 C) are used as source gases.
l 2 ) or TEOS (Si (0C 2
A silicon-containing compound such as H 5 ) 4 ) and an oxidizing gas such as oxygen (O 2 ) or nitrous oxide (N 2 O) are used. When using silicon nitride, the above-mentioned silane gas and ammonia (N
H 3) and nitrogen (N 2) using a nitriding gas such as.
【００１２】斯様にして半導体膜と、その表層部にプラ
ズマ酸化法にて得られた第一のプラズマ酸化膜とＰＥＣ
ＶＤ法にて得られた第二の堆積絶縁膜を形成し、ＭＯＳ
−ＦＥＴの半導体膜とゲート絶縁膜とを構成する。本願
発明では酸化性気体の原子状活性種を多量に生成して、
多結晶性半導体膜の粒界部や半導体膜の表面を効率的に
酸化させるので、斯うした部位に於ける不対結合対の数
が著しく減少する。取り分け、多結晶性半導体膜の粒界
部酸化は半導体膜の禁制帯中での捕獲準位数を低減し、
以て薄膜半導体装置のサブスレーシュホールド特性や閾
値電圧を小さくし、同時に粒界部に於ける荷電単体の非
弾性散乱数を減らす事で移動度の向上をもたらす。又、
酸化膜質が高い為に動作信頼性が高く、寿命の長い薄膜
半導体装置が得られる。しかも第一のプラズマ酸化膜が
４ｎｍ程度以上と従来よりも可成り厚く成るので、界面
遷移領域（半導体膜と絶縁膜との界面から絶縁膜側に４
ｎｍ程度の領域）全体が清浄と化して居る。此に対して
従来は酸素濃度１００％のプラズマ照射を３０秒程度行
われており、此の場合は酸化が非効率的で界面に多量の
不対結合対を残して居るにのみならず、（即ち多量の界
面捕獲準位を有して居るにのみならず、）プラズマ酸化
膜厚も２．５ｎｍ程度未満と薄く成っていた。従って従
来は界面遷移領域の６割程度未満しか清浄な領域はな
く、半導体特性に最も重要な影響を及ぼす界面遷移領域
内にフォトレジスト等が乗った元の汚れた表面が来てい
た。本願発明では元の汚れた表面は界面遷移領域外に出
ており、界面遷移領域全体が清浄と化して居る。此に加
えて酸化効率も高く不対結合対数も少なく、それ故半導
体特性が向上するので有る。In this manner, the semiconductor film, the first plasma oxide film obtained by the plasma oxidation method on the surface portion thereof, and PEC
A second deposited insulating film obtained by the VD method is formed, and a MOS
Forming a semiconductor film and a gate insulating film of the FET; In the present invention, a large amount of oxidizing gas atomic active species is generated,
Since the grain boundaries of the polycrystalline semiconductor film and the surface of the semiconductor film are efficiently oxidized, the number of unpaired pairs at such sites is significantly reduced. In particular, the grain boundary oxidation of the polycrystalline semiconductor film reduces the trap level in the forbidden band of the semiconductor film,
As a result, the mobility is improved by reducing the sub-threshold hold characteristic and the threshold voltage of the thin film semiconductor device, and at the same time, reducing the number of inelastic scattering of the charged single substance in the grain boundary portion. or,
Since the quality of the oxide film is high, a thin-film semiconductor device having high operation reliability and a long life can be obtained. In addition, since the first plasma oxide film is about 4 nm or more, which is considerably thicker than in the past, the interface transition region (4 nm from the interface between the semiconductor film and the insulating film to the insulating film side).
The whole area (about nm) is clean. On the other hand, conventionally, plasma irradiation with an oxygen concentration of 100% is performed for about 30 seconds, and in this case, oxidation is inefficient and not only a large amount of unpaired couples remain at the interface, but also ( That is, not only has a large number of interface trap levels, but also) the plasma oxide film thickness is as thin as less than about 2.5 nm. Therefore, conventionally, there is a clean area which is less than about 60% of the interfacial transition area, and the original dirty surface on which a photoresist or the like rides is present in the interfacial transition area which has the most important effect on semiconductor characteristics. In the present invention, the original dirty surface is out of the interface transition region, and the entire interface transition region is clean. In addition to this, the oxidation efficiency is high and the number of unpaired bonds is small, so that the semiconductor characteristics are improved.
【００１３】（実施例１）本願発明のプラズマ酸化法で
効率良くプラズマ酸化膜が形成される事を本実施例１に
て示す。プラズマ酸化速度はＮ型３Ω・ｃｍ （１０
０）の単結晶硅素基板を用いて調べられた。まず硅素基
板を次の手順で洗浄した。Example 1 Example 1 shows that a plasma oxide film is efficiently formed by the plasma oxidation method of the present invention. The plasma oxidation rate is N-type 3Ω · cm (10
This was examined using the single crystal silicon substrate of 0). First, the silicon substrate was cleaned by the following procedure.
【００１４】（１）超音波照射に依るイソプロピルアル
コール洗浄（２７℃、５分間） （２）窒素バブリングされた純水洗浄（２７℃、５分
間） （３）アンモニア過水洗浄（８０℃、５分間） （４）窒素バブリングされた純水洗浄（２７℃、５分
間） （５）硫酸過水洗浄（９７℃、５分間） （６）窒素バブリングされた純水洗浄（２７℃、５分
間） （７）希釈弗酸水溶液（弗酸濃度１．６７％）洗浄（２
７℃、２０秒間） （８）窒素バブリングされた純水洗浄（２７℃、５分
間） 上記７番目の希釈弗酸水溶液洗浄により、硅素基板表面
に存在する自然酸化膜が除去され、硅素表面は水素に依
り終端化されて居る。斯うして洗浄された基板表面にプ
ラズマ酸化膜をＰＥＣＶＤ装置にて成長させた。上記８
番目の純水洗浄が終了してから基板がＰＥＣＶＤ装置の
プラズマ処理室に設置される迄の時間は約１５分間で有
った。(1) Cleaning with isopropyl alcohol by ultrasonic irradiation (27 ° C., 5 minutes) (2) Cleaning with pure water subjected to nitrogen bubbling (27 ° C., 5 minutes) (3) Cleaning with ammonia and peroxide (80 ° C., 5 minutes) (4) Cleaning with pure water with nitrogen bubbling (27 ° C., 5 minutes) (5) Cleaning with sulfuric acid and peroxide (97 ° C., 5 minutes) (6) Cleaning with nitrogen bubbling and pure water (27 ° C., 5 minutes) (7) Washing with diluted hydrofluoric acid aqueous solution (hydrofluoric acid concentration 1.67%)
(7 ° C, 20 seconds) (8) Cleaning with pure water with nitrogen bubbling (27 ° C, 5 minutes) The above-mentioned seventh diluted hydrofluoric acid aqueous solution removes the natural oxide film present on the silicon substrate surface, leaving the silicon surface It is terminated by hydrogen. A plasma oxide film was grown on the surface of the substrate thus cleaned using a PECVD apparatus. 8 above
The time from the completion of the second pure water cleaning to the installation of the substrate in the plasma processing chamber of the PECVD apparatus was about 15 minutes.
【００１５】ＰＥＣＶＤ装置は枚葉式容量結合型でプラ
ズマは工業用周波数（１３．５６ＭＨｚ）のラジオ高周
波電源を用いて平行平板電極間に発生させる。プラズマ
処理室は反応容器に依り外気から隔絶され、プラズマ処
理中で凡０．１ｔｏｒｒから１０ｔｏｒｒ程度の減圧状
態とされる。反応容器内には下部平板電極と上部平板電
極が互いに平行に設置されて居り、これら二枚の電極が
平行平板電極を形成する。この平行平板電極間がプラズ
マ処理室となる。本願発明で用いたＰＥＣＶＤ装置は４
７０ｍｍ×５６０ｍｍの平行平板電極を備え、此等平行
平板電極間距離は下部平板電極の位置を上下させる事に
依り、１８．０ｍｍから３７．０ｍｍの間で自由に設定
し得る。此に応じてプラズマ処理室の容積は４７３８ｃ
ｍ３から９７３８ｃｍ３と変化する。又電極間距離を所
定の値に設定した場合、４７０ｍｍ×５６０ｍｍの平板
電極面内での電極間距離の偏差は僅か０．５ｍｍで有
る。従って電極間に生ずる電界強度の偏差は平板電極面
内で２％程度以下となり窮めて均質なプラズマがプラズ
マ処理室に発生する。下部平板電極上に酸化膜を形成す
べき硅素基板を置く。下部平板電極内部にはヒーターが
設けられて居り、下部平板電極の温度を２５０℃から４
００℃の間で任意に調整し得る。周辺２ｍｍを除いた下
部平板電極内の温度分布は設定温度に対して±５℃以内
で有り、基板として３６０ｍｍ×４６５ｍｍとの大きな
物を使用しても基板内温度偏差を±２℃以内に保つ事が
出来る。希ガスと酸化性気体から成る混合気体は配管を
通じて上部平板電極内に導入され、更に上部平板電極内
に設けられたガス拡散板の間を擦り抜けて上部平板電極
全面より略均一な圧力でプラズマ処理室に流れ出る。処
理中で有れば混合気体の一部は上部平板電極から出た所
で電離し、平行平板電極間にプラズマを発生させる。混
合気体の一部乃至全部は酸化膜の成長に関与し、成長に
関与しなかった残留混合気体及び酸化膜形成の化学反応
の結果として生じた生成ガスは排気ガスと成って反応容
器周辺上部に設けられた排気穴を介して排気される。排
気穴のコンダクタンスは平行平板電極間のコンダクタン
スに比べて十分に大きく、その値は平行平板電極間のコ
ンダクタンスの１００倍以上が好ましい。更に平行平板
電極間のコンダクタンスはガス拡散板のコンダクタンス
よりも十分に大きく、やはりその値はガス拡散板のコン
ダクタンスの１００倍以上が好ましい。こうした構成に
依り４７０ｍｍ×５６０ｍｍとの大型上部平板電極全面
より略均一な圧力で反応ガスがプラズマ処理室に導入さ
れ、同時に排気ガスがプラズマ処理室から総ての方向に
均等な流量で排気されるので有る。各種反応ガスの流量
は配管に導入される前にマス・フロー・コントローラー
に依り所定の値に調整される。又プラズマ処理室内の圧
力は排気穴出口に設けられたコンダクタンス・バルブに
依り所望の値に調整される。コンダクタンス・バルブの
排気側にはターボ分子ポンプ等の真空排気装置が設けら
れて居る。本願発明ではオイル・フリーのドライ・ポン
プが真空排気装置の一部として用いられ、プラズマ処理
室等の反応容器内の背景真空度を１０ー５ｔｏｒｒ台と
して居る。反応容器及び下部平板電極は接地電位に有
り、これらと上部平板電極は絶縁リングに依り電気的に
絶縁状態が保たれる。プラズマ発生時には高周波発振源
から出力された１３．５６ＭＨｚのラジオ高周波がイン
ピーダンス・マッチング回路を介して上部平板電極に印
加される。The PECVD apparatus is a single-wafer type capacitively-coupled type, and plasma is generated between parallel plate electrodes using a radio frequency power source of an industrial frequency (13.56 MHz). The plasma processing chamber is isolated from the outside air by the reaction vessel, and is kept under a reduced pressure of about 0.1 to 10 torr during the plasma processing. In the reaction vessel, a lower plate electrode and an upper plate electrode are provided in parallel with each other, and these two electrodes form a parallel plate electrode. The space between the parallel plate electrodes is a plasma processing chamber. The PECVD apparatus used in the present invention is 4
A parallel plate electrode of 70 mm × 560 mm is provided, and the distance between the parallel plate electrodes can be freely set between 18.0 mm and 37.0 mm by raising and lowering the position of the lower plate electrode. Accordingly, the volume of the plasma processing chamber is 4738c.
It changes from m 3 to 9738 cm 3 . When the distance between the electrodes is set to a predetermined value, the deviation of the distance between the electrodes in the plane of the 470 mm × 560 mm plate electrode is only 0.5 mm. Therefore, the deviation of the electric field intensity generated between the electrodes becomes about 2% or less in the plane of the plate electrode, and a uniform plasma is generated in the plasma processing chamber. A silicon substrate on which an oxide film is to be formed is placed on the lower plate electrode. A heater is provided inside the lower plate electrode, and the temperature of the lower plate electrode is increased from 250 ° C. to 4 ° C.
It can be arbitrarily adjusted between 00 ° C. The temperature distribution in the lower plate electrode excluding the peripheral 2 mm is within ± 5 ° C. with respect to the set temperature, and the temperature deviation in the substrate is kept within ± 2 ° C. even if a large substrate of 360 mm × 465 mm is used as the substrate. I can do things. A mixed gas composed of a rare gas and an oxidizing gas is introduced into the upper plate electrode through a pipe, and further passes through a gas diffusion plate provided in the upper plate electrode. Run out to. During the treatment, a part of the mixed gas is ionized at the place exiting from the upper plate electrode, and generates plasma between the parallel plate electrodes. A part or all of the mixed gas is involved in the growth of the oxide film, and the residual mixed gas not involved in the growth and the product gas generated as a result of the chemical reaction of the oxide film formation are exhausted and formed in the upper part of the periphery of the reaction vessel. Air is exhausted through the exhaust holes provided. The conductance of the exhaust hole is sufficiently larger than the conductance between the parallel plate electrodes, and its value is preferably at least 100 times the conductance between the parallel plate electrodes. Further, the conductance between the parallel plate electrodes is sufficiently larger than the conductance of the gas diffusion plate, and the value is preferably 100 times or more the conductance of the gas diffusion plate. According to such a configuration, the reaction gas is introduced into the plasma processing chamber at substantially uniform pressure from the entire surface of the large upper plate electrode of 470 mm × 560 mm, and the exhaust gas is simultaneously exhausted from the plasma processing chamber at a uniform flow rate in all directions. There is. The flow rates of the various reaction gases are adjusted to predetermined values by a mass flow controller before being introduced into the piping. The pressure in the plasma processing chamber is adjusted to a desired value by a conductance valve provided at the outlet of the exhaust hole. A vacuum exhaust device such as a turbo molecular pump is provided on the exhaust side of the conductance valve. In the present invention the dry pump of the oil-free is used as part of the vacuum exhaust system, there background vacuum degree in the reaction vessel of a plasma processing chamber such as 10 @ 5 torr stand. The reaction vessel and the lower plate electrode are at the ground potential, and these and the upper plate electrode are kept electrically insulated by the insulating ring. At the time of plasma generation, a radio frequency of 13.56 MHz output from a high frequency oscillation source is applied to the upper plate electrode via an impedance matching circuit.
【００１６】本発明に用いたＰＥＣＶＤ装置は上述の如
く窮めて精巧たる電極間制御と均質なガス流を実現した
事に依り３６０ｍｍ×４６５ｍｍとの大型基板に対応可
能な薄膜形成装置となった。しかしながらこれらの基礎
概念さえ踏襲すれば、更なる基板の大型化には寧ろ容易
に対応出来、実際５５０ｍｍ×６５０ｍｍとのより大型
な基板に対応し得る装置も実現可能で有る。又本願発明
では最も汎用性の高い周波数１３．５６ＭＨｚの高周波
を用いているが、この他にこの高周波の整数倍の高周波
を利用しても良い。例えば２倍の２７．１２ＭＨｚや３
倍の４０．６８ＭＨｚ、４倍の５４．２４ＭＨｚ等も有
効で有る。更には１００ＭＨｚ〜１ＧＨｚ程度のＶＨＦ
波を利用しても良い。周波数が１０ＭＨｚ程度のｒｆ波
から数百ＭＨｚ程度のＶＨＦ波で有れば平行平板電極間
にプラズマを発生させる事が可能で有る。従って本願発
明に用いたＰＥＣＶＤ装置の高周波発振源とインピーダ
ンス・マッチング回路を交換する事に依り容易に所望の
周波数の高周波を用いてプラズマを発生出来る。The PECVD apparatus used in the present invention has become a thin film forming apparatus capable of coping with a large substrate of 360 mm.times.465 mm due to the above-mentioned intricately sophisticated inter-electrode control and uniform gas flow. . However, if these basic concepts are followed, it is possible to easily cope with a further increase in the size of the substrate, and it is also possible to realize an apparatus that can actually cope with a larger substrate of 550 mm × 650 mm. In the present invention, a high frequency of 13.56 MHz, which has the highest versatility, is used. Alternatively, a high frequency which is an integral multiple of this high frequency may be used. For example, 2 times 27.12 MHz or 3
A frequency of 40.68 MHz, a frequency of 54.24 MHz, and the like are also effective. Furthermore, VHF of about 100 MHz to 1 GHz
Waves may be used. If the frequency is an rf wave of about 10 MHz to a VHF wave of about several hundred MHz, it is possible to generate plasma between the parallel plate electrodes. Therefore, by exchanging the high frequency oscillation source and the impedance matching circuit of the PECVD apparatus used in the present invention, it is possible to easily generate plasma using a high frequency having a desired frequency.
【００１７】本実施例１では、基板は下部平板電極の温
度が３７５℃に保たれているプラズマ処理室に設置され
る。プラズマを立てる事を除いてプラズマ処理室内の条
件を酸化過程と同一とする。例えば酸素を１００ＳＣＣ
Ｍとヘリウムを４９００ＳＣＣＭ流し、プラズマ処理室
内の圧力を１．５Ｔｏｒｒに保つ。平行平板電極間距離
は２１．６ｍｍで有る。設置基板がこうした系と平衡状
態となった後の硅素基板表面温度は３５０℃で有る。設
置された基板と処理室とが平衡状態に達した後、上部平
板電極に高周波を印加してプラズマを発生させ、半導体
膜表面の酸化を行う。高周波出力は５００Ｗで有る。プ
ラズマ酸化条件の一例は以下の通りとなる。In the first embodiment, the substrate is set in a plasma processing chamber where the temperature of the lower plate electrode is maintained at 375 ° C. The conditions in the plasma processing chamber are the same as in the oxidation process except that a plasma is established. For example, 100 SCC of oxygen
M and helium are flowed at 4900 SCCM, and the pressure in the plasma processing chamber is maintained at 1.5 Torr. The distance between the parallel plate electrodes is 21.6 mm. The silicon substrate surface temperature is 350 ° C. after the installation substrate is in equilibrium with such a system. After the placed substrate and the processing chamber reach an equilibrium state, a high frequency is applied to the upper plate electrode to generate plasma and oxidize the surface of the semiconductor film. The high frequency output is 500W. An example of the plasma oxidation conditions is as follows.
【００１８】酸素流量：Ｏ２＝１００ＳＣＣＭ ヘリウム流量：Ｈｅ＝４９００ＳＣＣＭ （酸素濃度
２．０％） ラジオ高周波出力：ＲＦ＝５００Ｗ（０．１９Ｗ／ｃｍ
２） 圧力：Ｐ＝１．５Ｔｏｒｒ 電極間距離：Ｓ＝２１．６ｍｍ 下部平板電極温度：Ｔｓｕｓ＝３７５℃ 硅素基板表面温度：Ｔｓｕｂ＝３５０℃ プラズマ処理時間：ｔ＝５００秒 此の条件下で硅素表面には５．３ｎｍの酸化膜が成長す
る。以下、酸化速度を調べる為にプラズマ処理時間を５
０秒と２００秒、３００秒としてプラズマ酸化を行っ
た。又、上例で希ガスをヘリウムからアルゴンに変えて
同じプラズマ処理を単結晶硅素基板に施した。斯うして
得られた結果を図１に示す。図１中でヘリウム希釈酸素
２％と記して有るのが希ガスとしてヘリウムを用いた実
施例に相当し、アルゴン希釈酸素２％と記して有るのが
希ガスとしてアルゴンを用いた実施例に相当する。更に
図１には比較の為に従来技術に当たる酸素１００％での
プラズマ酸化の結果（図１中に純酸素１００％と記す）
をも記す。此の場合、プラズマ処理室に導入する気体が
混合気体の５０００ＳＣＣＭから純酸素気体の５０００
ＳＣＣＭに変わった他は、比較の為にすべて同じ処理条
件とした。図１から分かる様に本願発明に依り従来より
も酸化速度が５０％以上も大きくする事が可能と化し
た。Oxygen flow rate: O 2 = 100 SCCM Helium flow rate: He = 4900 SCCM (oxygen concentration 2.0%) Radio high frequency output: RF = 500 W (0.19 W / cm)
2 ) Pressure: P = 1.5 Torr Distance between electrodes: S = 21.6 mm Lower plate electrode temperature: Tsus = 375 ° C. Silicon substrate surface temperature: Tsub = 350 ° C. Plasma processing time: t = 500 seconds Silicon under these conditions An oxide film of 5.3 nm grows on the surface. Hereinafter, the plasma processing time was set to 5
Plasma oxidation was performed at 0, 200, and 300 seconds. In the above example, the same plasma treatment was performed on the single crystal silicon substrate by changing the rare gas from helium to argon. The result obtained in this way is shown in FIG. In FIG. 1, 2% of helium diluted oxygen corresponds to the example using helium as a rare gas, and 2% of argon diluted oxygen corresponds to the example using argon as a rare gas. I do. Further, FIG. 1 shows the result of plasma oxidation with 100% oxygen according to the prior art for comparison (shown as 100% pure oxygen in FIG. 1).
Is also noted. In this case, the gas introduced into the plasma processing chamber is changed from 5000 SCCM of the mixed gas to 5000 SCCM of the pure oxygen gas.
Except for changing to SCCM, all processing conditions were the same for comparison. As can be seen from FIG. 1, according to the present invention, the oxidation rate can be increased by 50% or more as compared with the conventional case.
【００１９】（実施例２）図２（ａ）〜（ｄ）はＭＯＳ
型電界効果トランジスタを形成する薄膜半導体装置の製
造工程を断面で示した図で有る。本実施例２では基板１
０１として歪点が６５０℃程度の汎用無アルカリガラス
を用いた。まず基板１０１上にＥＣＲ−ＰＥＣＶＤ法で
酸化硅素膜を２００ｎｍ程度堆積し、下地保護膜１０２
とした。酸化硅素膜のＥＣＲ−ＰＥＣＶＤ法での堆積条
件は以下の通りで有る。(Embodiment 2) FIGS. 2A to 2D show MOS transistors.
FIG. 4 is a cross-sectional view showing a manufacturing process of a thin-film semiconductor device for forming a field-effect transistor. In the second embodiment, the substrate 1
As 01, general-purpose alkali-free glass having a strain point of about 650 ° C. was used. First, a silicon oxide film is deposited to a thickness of about 200 nm on the substrate 101 by the ECR-PECVD method.
And The conditions for depositing the silicon oxide film by the ECR-PECVD method are as follows.
【００２０】 モノシラン（ＳｉＨ４）流量・・・６０ｓｃｃｍ 酸素（Ｏ２）流量・・・１００ｓｃｃｍ 圧力・・・２．４０ｍＴｏｒｒ マイクロ波（２．４５ＧＨｚ）出力・・・２２５０Ｗ 印可磁場・・・８７５Ｇａｕｓｓ 基板温度・・・１００℃ 成膜時間・・・４０秒 此の下地保護膜上に半導体膜として真性非晶質硅素膜を
ＬＰＣＶＤ法にて６５ｎｍ程度の膜厚に堆積した。ＬＰ
ＣＶＤ装置はホット・ウォール型で容積が１８４．５ｌ
で、基板挿入後の反応総面積は約４４０００ｃｍ２で有
る。堆積温度は４２５℃で原料ガスとして純度９９．９
９％以上のジシラン（Ｓｉ２Ｈ６）を用い、２００ｓｃ
ｃｍ反応炉に供給した。堆積圧力は凡そ１．１Ｔｏｒｒ
で有り、此の条件下で硅素膜の堆積速度は０．７７ｎｍ
／ｍｉｎで有った。斯様にして得られた非晶質半導体膜
にキセノン塩素（ＸｅＣｌ）エキシマレーザーを照射し
て半導体膜の結晶化を進めた。照射レーザーエネルギー
密度は４２５ｍＪ・ｃｍ−２で、半導体膜が膜厚方向全
体に渡り完全溶融して微結晶化が生ずるエネルギー密度
よりも１０ｍＪ・ｃｍ−２低いエネルギー密度で有っ
た。レーザー結晶化終了後の多結晶硅素薄膜の厚みは６
１．８ｎｍで有った。こうして結晶性半導体膜（多結晶
硅素膜）を形成した（第一工程）後、この結晶性半導体
膜を島状に加工して、後に半導体装置の能動層と成る半
導体膜の島１０３を形成した。（図２−ａ） 次にパターニング加工された半導体膜の島１０３を被う
様に酸化硅素膜１０４をＰＥＣＶＤ装置にてプラズマ酸
化法と堆積法にて形成（第二工程）した。此の酸化硅素
膜は半導体装置のゲート絶縁膜として機能する。ゲート
絶縁膜形成に先立ち基板を次の手順で洗浄した。Monosilane (SiH4) flow rate: 60 sccm Oxygen (O2) flow rate: 100 sccm Pressure: 2.40 mTorr Microwave (2.45 GHz) output: 2250 W Applied magnetic field: 875 Gauss Substrate temperature 100 ° C. Film formation time: 40 seconds An intrinsic amorphous silicon film was deposited as a semiconductor film on the underlayer protective film to a thickness of about 65 nm by LPCVD. LP
The CVD equipment is a hot wall type with a volume of 184.5 l
The total reaction area after inserting the substrate is about 44000 cm 2 . The deposition temperature is 425 ° C. and the purity is 99.9 as a source gas.
200 sc using disilane (Si 2 H 6 ) of 9% or more
cm reactor. Deposition pressure is about 1.1 Torr
Under these conditions, the deposition rate of the silicon film is 0.77 nm.
/ Min. The thus obtained amorphous semiconductor film was irradiated with a xenon chlorine (XeCl) excimer laser to promote crystallization of the semiconductor film. In the irradiation laser energy density is 425mJ · cm -2, the semiconductor film is there at 10 mJ · cm -2 lower energy density than the energy density micro-crystallization occurs completely melted throughout the thickness direction. The thickness of polycrystalline silicon thin film after laser crystallization is 6
It was 1.8 nm. After forming the crystalline semiconductor film (polycrystalline silicon film) in this manner (first step), the crystalline semiconductor film was processed into an island shape, and an island 103 of the semiconductor film which later became an active layer of the semiconductor device was formed. . (FIG. 2-a) Next, a silicon oxide film 104 was formed by a plasma oxidation method and a deposition method using a PECVD apparatus so as to cover the island 103 of the semiconductor film subjected to the patterning process (second step). This silicon oxide film functions as a gate insulating film of the semiconductor device. Prior to forming the gate insulating film, the substrate was cleaned in the following procedure.
【００２１】（１）超音波照射に依るイソプロピルアル
コール洗浄（２７℃、５分間） （２）窒素バブリングされた純水洗浄（２７℃、５分
間） （３）アンモニア過水洗浄（８０℃、５分間） （４）窒素バブリングされた純水洗浄（２７℃、５分
間） （５）硫酸過水洗浄（９７℃、５分間） （６）窒素バブリングされた純水洗浄（２７℃、５分
間） （７）希釈弗酸水溶液（弗酸濃度１．６７％）洗浄（２
７℃、２０秒間） （８）窒素バブリングされた純水洗浄（２７℃、５分
間） 上記８番目の純水洗浄が終了してから基板がＰＥＣＶＤ
装置のプラズマ処理室に設置される迄の時間は約１５分
間で有った。プラズマ処理装置は実施例１に記した物と
同一で有り、第一のプラズマ酸化条件は以下の通りで有
る。(1) Isopropyl alcohol cleaning by ultrasonic irradiation (27 ° C., 5 minutes) (2) Nitrogen bubbling pure water cleaning (27 ° C., 5 minutes) (3) Ammonia / hydrogen peroxide cleaning (80 ° C., 5 minutes) (4) Cleaning with pure water with nitrogen bubbling (27 ° C., 5 minutes) (5) Cleaning with sulfuric acid and peroxide (97 ° C., 5 minutes) (6) Cleaning with nitrogen bubbling and pure water (27 ° C., 5 minutes) (7) Washing with diluted hydrofluoric acid aqueous solution (hydrofluoric acid concentration 1.67%)
(7 ° C., 20 seconds) (8) Pure water cleaning with nitrogen bubbling (27 ° C., 5 minutes) After the eighth pure water cleaning is completed, the substrate is PECVD
The time required for installation in the plasma processing chamber of the apparatus was about 15 minutes. The plasma processing apparatus is the same as that described in Example 1, and the first plasma oxidation conditions are as follows.
【００２２】酸素流量：Ｏ２＝１００ＳＣＣＭ ヘリウム流量：Ｈｅ＝４９００ＳＣＣＭ （酸素濃度
２．０％） ラジオ高周波出力：ＲＦ＝５００Ｗ（０．１９Ｗ／ｃｍ
２） 圧力：Ｐ＝１．５Ｔｏｒｒ 電極間距離：Ｓ＝２１．６ｍｍ 下部平板電極温度：Ｔｓｕｓ＝３７５℃ ガラス基板表面温度：Ｔｓｕｂ＝３５０℃ プラズマ処理時間：ｔ＝３００秒 此の条件下で硅素表面には５ｎｍ程度の酸化膜が成長し
て居る。プラズマ酸化が終了した後、引き続いて酸化硅
素膜の堆積を行う。原料気体の流量を安定させる為にプ
ラズマ酸化後プラズマ処理室を次の状態とした。Oxygen flow rate: O 2 = 100 SCCM Helium flow rate: He = 4900 SCCM (oxygen concentration 2.0%) Radio high frequency output: RF = 500 W (0.19 W / cm)
2 ) Pressure: P = 1.5 Torr Distance between electrodes: S = 21.6 mm Lower plate electrode temperature: Tsus = 375 ° C. Glass substrate surface temperature: Tsub = 350 ° C. Plasma processing time: t = 300 seconds Silicon under these conditions An oxide film of about 5 nm grows on the surface. After the plasma oxidation is completed, a silicon oxide film is deposited subsequently. In order to stabilize the flow rate of the source gas, the plasma processing chamber was placed in the following state after the plasma oxidation.
【００２３】酸素流量：Ｏ２＝１２００ＳＣＣＭ アルゴン流量：Ａｒ＝４７００ＳＣＣＭ ＴＥＯＳ流量：ＴＥＯＳ＝１００ＳＣＣＭ ラジオ高周波出力：ＲＦ＝０Ｗ（プラズマは立てない） 圧力：Ｐ＝１．５Ｔｏｒｒ 電極間距離：Ｓ＝２０．９ｍｍ 下部平板電極温度：Ｔｓｕｓ＝３７５℃ ガラス基板表面温度：Ｔｓｕｂ＝３５０℃ 安定化時間：ｔ＝２０秒 此の状態に連続して、以下の条件で第二の堆積絶縁膜で
有る酸化硅素膜を堆積した。Oxygen flow rate: O 2 = 1200 SCCM Argon flow rate: Ar = 4700 SCCM TEOS flow rate: TEOS = 100 SCCM Radio high frequency output: RF = 0 W (no plasma is set up) Pressure: P = 1.5 Torr Distance between electrodes: S = 20. 9 mm Lower plate electrode temperature: Tsus = 375 ° C. Glass substrate surface temperature: Tsub = 350 ° C. Stabilization time: t = 20 seconds Continuously in this state, the silicon oxide film as the second deposited insulating film under the following conditions Was deposited.
【００２４】酸素流量：Ｏ２＝１２００ＳＣＣＭ アルゴン流量：Ａｒ＝４７００ＳＣＣＭ ＴＥＯＳ流量：ＴＥＯＳ＝１００ＳＣＣＭ ラジオ高周波出力：ＲＦ＝１０００Ｗ（０．３８Ｗ／ｃ
ｍ２） 圧力：Ｐ＝１．５Ｔｏｒｒ 電極間距離：Ｓ＝２０．９ｍｍ 下部平板電極温度：Ｔｓｕｓ＝３７５℃ ガラス基板表面温度：Ｔｓｕｂ＝３５０℃ 堆積時間：ｔ＝３３秒 斯様にして第二工程で酸化硅素膜を形成した後、第三工
程として基板を酸化性雰囲気下にて第一熱処理を行っ
た。濃度１６％の塩化水素酸水溶液を空気中に露点で９
６℃含む塩酸水蒸気空気下にて熱処理は施こされた。処
理温度は３４５℃で処理時間は２時間、処理室内圧力は
１気圧で有った。この塩酸に依る熱処理が終了した後、
引き続いて酸化膜中のハロゲン元素を抜く目的で１時間
の熱処理を継続した。この熱処理雰囲気は露点９６℃の
水蒸気含有空気中で行われ、雰囲気に塩酸は含まれて居
ない。熱処理温度は矢張り３４５℃で圧力は１気圧で有
る。Oxygen flow rate: O 2 = 1200 SCCM Argon flow rate: Ar = 4700 SCCM TEOS flow rate: TEOS = 100 SCCM Radio high frequency output: RF = 1000 W (0.38 W / c)
m 2 ) Pressure: P = 1.5 Torr Distance between electrodes: S = 20.9 mm Lower flat plate electrode temperature: Tsus = 375 ° C. Glass substrate surface temperature: Tsub = 350 ° C. Deposition time: t = 33 seconds After the silicon oxide film was formed in the step, the substrate was subjected to a first heat treatment in an oxidizing atmosphere as a third step. An aqueous solution of hydrochloric acid having a concentration of 16% was dew point 9
The heat treatment was performed under hydrochloric acid steam air containing 6 ° C. The processing temperature was 345 ° C., the processing time was 2 hours, and the processing chamber pressure was 1 atm. After the heat treatment with hydrochloric acid is completed,
Subsequently, the heat treatment was continued for one hour in order to remove the halogen element in the oxide film. This heat treatment atmosphere is performed in steam-containing air having a dew point of 96 ° C., and the atmosphere does not contain hydrochloric acid. The heat treatment temperature is 345 ° C. and the pressure is 1 atm.
【００２５】斯うして第三工程が終了した後に第四工程
の第二熱処理を行い、酸化膜を乾燥さた。第二熱処理は
アルゴン中に水素を３％含む非酸化性雰囲気下にて１気
圧、３５０℃で２時間施された。After the completion of the third step, the second heat treatment of the fourth step was performed to dry the oxide film. The second heat treatment was performed at 350 ° C. for 2 hours at 1 atm under a non-oxidizing atmosphere containing 3% of hydrogen in argon.
【００２６】第四工程終了後、直ちに基板は先に記述し
た平行平板容量結合型ＰＥＣＶＤ装置に導入され、半導
体膜と酸化膜に対して水素プラズマ照射が施された。水
素プラズマ条件は以下の通りで有る。Immediately after the fourth step, the substrate was introduced into the above-mentioned parallel plate capacitively coupled PECVD apparatus, and the semiconductor film and the oxide film were irradiated with hydrogen plasma. The hydrogen plasma conditions are as follows.
【００２７】水素流量：Ｈ２＝１０００ＳＣＣＭ ラジオ高周波出力：ＲＦ＝１００Ｗ（０．０３８Ｗ／ｃ
ｍ２） 圧力：Ｐ＝０．５Ｔｏｒｒ 電極間距離：Ｓ＝２５ｍｍ 下部平板電極温度：Ｔｓｕｓ＝３５０℃ ガラス基板表面温度：Ｔｓｕｂ＝３２５℃ プラズマ処理時間：ｔ＝９０秒 此の工程が終了した後に第一のプラズマ酸化膜と第二の
堆積絶縁膜を合わせた酸化膜の厚みを測定したところ、
その値は９３．５ｎｍで有った。斯うしてゲート絶縁膜
形成と、酸化膜及び界面の改質が完了した。（図２−
ｂ） 引き続いて金属薄膜に依りゲート電極１０５をスパッタ
ー法にて形成する。スパッター時の基板温度は１５０℃
で有った。本実施例２では７５０ｎｍの膜厚を有するタ
ンタル（Ｔａ）にてゲート電極を作成し、このゲート電
極のシート抵抗は２．５４Ω／□で有った。次にゲート
電極をマスクとして、ドナー又はアクセプターとなる不
純物イオン１０６を打ち込み、ソース・ドレイン領域１
０７とチャンネル形成領域１０８をゲート電極に対して
自己整合的に作成する。本実施例２ではＣＭＯＳ半導体
装置を作製した。ＮＭＯＳトランジスタを作製する際に
はＰＭＯＳトランジスタ部をアルミニウム（Ａｌ）薄膜
で覆った上で、不純物元素として水素中に５％の濃度で
希釈されたフォスヒィン（ＰＨ３）を選び、加速電圧７
０ｋＶにて水素を含んだ総イオンを５×１０１５ｃｍ
−２の濃度でＮＭＯＳトランジスタのソース・ドレイン
領域に打ち込んだ。反対にＰＭＯＳトランジスタを作製
する際にはＮＭＯＳトランジスタ部をアルミニウム（Ａ
ｌ）薄膜で覆った上で、不純物元素として水素中に５％
の濃度で希釈されたジボラン（Ｂ２Ｈ６）を選び、加速
電圧７０ｋＶにて水素を含んだ総イオンを４×１０１５
ｃｍー２の濃度でＰＭＯＳトランジスタのソース・ドレ
イン領域に打ち込んだ。（図１−ｃ）イオン打ち込み時
の基板温度は３００℃で有る。Hydrogen flow rate: H 2 = 1000 SCCM Radio high frequency output: RF = 100 W (0.038 W / c)
m 2 ) Pressure: P = 0.5 Torr Distance between electrodes: S = 25 mm Lower flat plate electrode temperature: Tsus = 350 ° C. Glass substrate surface temperature: Tsub = 325 ° C. Plasma processing time: t = 90 seconds After this step is completed When the thickness of the oxide film combining the first plasma oxide film and the second deposited insulating film was measured,
Its value was 93.5 nm. Thus, the formation of the gate insulating film and the modification of the oxide film and the interface were completed. (Figure 2-
b) Subsequently, a gate electrode 105 is formed by a sputtering method using a metal thin film. The substrate temperature during sputter is 150 ° C
It was. In Example 2, a gate electrode was formed from tantalum (Ta) having a thickness of 750 nm, and the sheet resistance of the gate electrode was 2.54 Ω / □. Next, using the gate electrode as a mask, an impurity ion 106 serving as a donor or an acceptor is implanted into the source / drain region 1.
07 and the channel forming region 108 are formed in a self-aligned manner with respect to the gate electrode. In Example 2, a CMOS semiconductor device was manufactured. When fabricating an NMOS transistor, the PMOS transistor portion is covered with an aluminum (Al) thin film, and phosphine (PH 3 ) diluted with hydrogen at a concentration of 5% is selected as an impurity element.
At 0 kV, 5 × 10 15 cm of total ions containing hydrogen
Implanted into the source / drain region of the NMOS transistor at a concentration of -2 . Conversely, when fabricating a PMOS transistor, the NMOS transistor portion is formed of aluminum (A
l) After covering with a thin film, 5%
Diborane (B 2 H 6 ) diluted at a concentration of 4 × 10 15 was selected at an accelerating voltage of 70 kV.
It was implanted at a concentration of cm -2 into the source / drain regions of the PMOS transistor. (FIG. 1-c) The substrate temperature at the time of ion implantation is 300 ° C.
【００２８】次にＰＥＣＶＤ法でＴＥＯＳ（Ｓｉ−（Ｏ
ＣＨ２ＣＨ３）４）と酸素を原料気体として、基板温度
３００℃で層間絶縁膜１０９を堆積した。層間絶縁膜は
二酸化硅素膜から成り、その膜厚は凡そ５００ｎｍで有
った。層間絶縁膜堆積後、層間絶縁膜の焼き締めとソー
ス・ドレイン領域に添加された不純物元素の活性化を兼
ねて、窒素雰囲気下３５０℃にて２時間の熱処理を施し
た。最後にコンタクト・ホールを開穴し、スパッター法
で基板温度を１８０℃としてアルミニウムを堆積し、配
線１１０を作成して薄膜半導体装置が完成した。（図１
−ｄ） この様にして作成した薄膜半導体装置の伝達特性を測定
した。測定した半導体装置のチャンネル形成領域の長さ
は１０μｍで幅は１０μｍで有った。伝達特性の測定は
室温にて行われた。ＮＭＯＳトランジスタのＶｄｓ＝８
Ｖに於ける飽和領域より求めた移動度は１２９±７ｃｍ
２・Ｖー１・ｓ−１で有り、閾値電圧は３．００１±
０．１７６Ｖ、サブスレーシュホールド・スイングは
０．３６５±０．０６７Ｖで有った。又、ＰＭＯＳトラ
ンジスタのＶｄｓ＝−８Ｖに於ける飽和領域より求めた
移動度は８４±２ｃｍ２・Ｖー１・ｓ−１で有り、閾値
電圧は−２．０５４±０．１６８Ｖ、サブスレーシュホ
ールド・スイングは０．４４６±０．０４８Ｖで有っ
た。此に対してプラズマ酸化を酸素１００％で３０秒間
行った比較例（従来技術に相当、此の時プラズマ酸化膜
は２ｎｍ程度）ではＮＭＯＳの移動度は７３±６ｃｍ２
・Ｖー１・ｓ−１で有り、閾値電圧は３．７９１±０．
３０８Ｖ、サブスレーシュホールド・スイングは０．５
５６±０．１２４Ｖで有った。又、比較例のＰＭＯＳの
移動度は７５±２ｃｍ２・Ｖー１・ｓ−１で有り、閾値
電圧は−３．２８７±０．４３９Ｖ、サブスレーシュホ
ールド・スイングは０．９７９±０．３２５Ｖで有っ
た。此の例が示す様に本願発明に依りＮ型とＰ型の両半
導体装置共に大きな移動度を有し、急峻なサブスレーシ
ュホールド特性を示す優良な薄膜半導体装置をばらつき
無く安定的に製造出来る様に成った。然も界面遷移領域
の酸化膜質が高い為に酸化膜の信頼性が良く、超寿命の
薄膜半導体装置を汎用ガラス基板を使用し得る低温工程
にて、簡便且つ容易に作成し出来る様に成った。Next, TEOS (Si- (O
Using CH 2 CH 3 ) 4 ) and oxygen as source gases, an interlayer insulating film 109 was deposited at a substrate temperature of 300 ° C. The interlayer insulating film was made of a silicon dioxide film, and its thickness was about 500 nm. After the deposition of the interlayer insulating film, a heat treatment was performed at 350 ° C. for 2 hours in a nitrogen atmosphere to bake the interlayer insulating film and activate the impurity element added to the source / drain regions. Finally, a contact hole was opened, aluminum was deposited at a substrate temperature of 180 ° C. by a sputtering method, and a wiring 110 was formed to complete a thin film semiconductor device. (Figure 1
-D) The transfer characteristics of the thin film semiconductor device thus prepared were measured. The length of the channel formation region of the semiconductor device measured was 10 μm and the width was 10 μm. The transfer characteristics were measured at room temperature. Vds of NMOS transistor = 8
The mobility determined from the saturation region at V is 129 ± 7 cm
2 · V −1 · s −1 , and the threshold voltage is 3.001 ±
0.176V, the sub-shake hold swing was 0.365 ± 0.067V. The mobility of the PMOS transistor determined from the saturation region at Vds = −8 V is 84 ± 2 cm 2 · V −1 · s −1 , the threshold voltage is −2.054 ± 0.168 V, and the sub-latch is The hold swing was 0.446 ± 0.048V. On the other hand, in a comparative example in which plasma oxidation was performed with 100% oxygen for 30 seconds (corresponding to the prior art, the plasma oxide film was about 2 nm at this time), the mobility of the NMOS was 73 ± 6 cm 2.
V −1 · s− 1 , and the threshold voltage is 3.791 ± 0.
308V, Sub-leash hold swing is 0.5
It was 56 ± 0.124V. The mobility of the PMOS of the comparative example is 75 ± 2 cm 2 · V −1 · s −1 , the threshold voltage is −3.287 ± 0.439 V, and the sub-threshold hold swing is 0.979 ± 0. It was 325V. As shown in this example, according to the present invention, both the N-type and P-type semiconductor devices have large mobilities, and excellent thin-film semiconductor devices exhibiting steep sub-slash hold characteristics can be stably manufactured without variation. It became like. Of course, the oxide film quality in the interface transition region is high, so the oxide film has high reliability, and a long-life thin-film semiconductor device can be easily and easily formed in a low-temperature process that can use a general-purpose glass substrate. .
【００２９】[0029]
【発明の効果】以上詳述してきた様に、従来低品質で有
った界面遷移領域の高品質化が本願発明に依り可能と化
し、薄膜半導体装置の高性能化を簡便に実現した。これ
に依り薄膜トランジスタに代表される半導体装置の高速
動作や省エネ化を促進し、同時に半導体装置の動作安定
性をも高めるとの効果が認められる。As described in detail above, the present invention makes it possible to improve the quality of the interface transition region, which has conventionally been of low quality, and easily achieves high performance of the thin film semiconductor device. This has the effect of promoting high-speed operation and energy saving of a semiconductor device represented by a thin film transistor, and at the same time, improving the operation stability of the semiconductor device.
【図１】 本願発明の効果を確認した図。FIG. 1 is a diagram confirming the effect of the present invention.
【図２】 本願発明の製造工程を説明した図。FIG. 2 is a diagram illustrating a manufacturing process of the present invention.
１０１・・・基板 １０２・・・下地保護膜 １０３・・・半導体膜の島 １０４・・・酸化硅素膜 １０５・・・ゲート電極 １０６・・・不純物イオン １０７・・・ソース・ドレイン領域 １０８・・・チャネル形成領域 １０９・・・層間絶縁膜 １１０・・・配線 DESCRIPTION OF SYMBOLS 101 ... Substrate 102 ... Underlying protective film 103 ... Semiconductor film island 104 ... Silicon oxide film 105 ... Gate electrode 106 ... Impurity ions 107 ... Source / drain region 108 ...・ Channel forming region 109 ・ ・ ・ Interlayer insulating film 110 ・ ・ ・ Wiring
───────────────────────────────────────────────────── フロントページの続き Ｆターム(参考） 5F045 AA06 AB03 AC01 AD08 AE21 AF07 BB16 BB18 CA15 DC51 HA15 5F058 BA20 BB04 BB07 BC11 BD01 BD04 BD10 BD15 BF07 BF23 BF24 BF25 BF29 BF30 BF32 BH01 BH16 BH20 BJ01 BJ02 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference)
Claims (16)
該半導体膜上に形成された絶縁膜とを少なくとも構成要
件として有する半導体装置の製造方法に於いて、 半導体膜を形成する第一工程と絶縁膜を形成する第二工
程とを含み、 該第二工程は希ガスと酸化性気体との混合気体から成る
プラズマを該半導体膜に照射した後に、連続してプラズ
マ化学気相堆積法（ＰＥＣＶＤ法）にて絶縁膜を堆積す
る工程を少なくとも含む事を特徴とする薄膜半導体装置
の製造方法。A semiconductor film formed on an insulating material;
A method of manufacturing a semiconductor device having at least a dielectric film formed on the semiconductor film as a constituent feature, comprising: a first step of forming a semiconductor film and a second step of forming an insulating film; The step includes at least a step of irradiating the semiconductor film with a plasma composed of a mixed gas of a rare gas and an oxidizing gas, and then continuously depositing an insulating film by a plasma enhanced chemical vapor deposition (PECVD) method. A method for manufacturing a thin film semiconductor device.
とする請求項１記載の薄膜半導体装置の製造方法。2. The method according to claim 1, wherein the semiconductor film is a polycrystalline film.
して居る事を特徴とする請求項１または２記載の薄膜半
導体装置の製造方法。3. The method according to claim 1, wherein the semiconductor film is mainly composed of silicon (Si).
ｘ≦２）を主体と成して居る事を特徴とする請求項１乃
至３のいずれかに記載の薄膜半導体装置の製造方法。4. The method according to claim 1, wherein the insulating film is made of silicon oxide (SiO x = 0 <).
4. The method for manufacturing a thin film semiconductor device according to claim 1, wherein x ≦ 2 is mainly used.
（ｒｆ波）で有る事を特徴とする請求項１乃至４のいず
れかに記載の薄膜半導体装置の製造方法。5. The method for manufacturing a thin film semiconductor device according to claim 1, wherein the plasma source of the plasma is a radio wave (rf wave).
（ＶＨＦ波）で有る事を特徴とする請求項１乃至４のい
ずれかに記載の薄膜半導体装置の製造方法。6. The method for manufacturing a thin film semiconductor device according to claim 1, wherein the plasma source of the plasma is a very high frequency (VHF wave).
で有る事を特徴とする請求項１乃至４のいずれかに記載
の薄膜半導体装置の製造方法。7. The method according to claim 1, wherein a plasma source of the plasma is a microwave.
度以下で有る事を特徴とする請求項１乃至７のいずれか
に記載の薄膜半導体装置の製造方法。8. The method according to claim 1, wherein the substrate temperature during the second step is about 450 ° C. or less.
度以下で有る事を特徴とする請求項１乃至７のいずれか
に記載の薄膜半導体装置の製造方法。9. The method for manufacturing a thin film semiconductor device according to claim 1, wherein the substrate temperature during said second step is about 425 ° C. or less.
割合が１％程度以上１０％程度以下で有る事を特徴とす
る請求項１乃至９のいずれかに記載の薄膜半導体装置の
製造方法。10. The method of manufacturing a thin film semiconductor device according to claim 1, wherein the ratio of the oxidizing gas in the mixed gas is about 1% or more and about 10% or less.
割合が１％程度以上６％程度以下で有る事を特徴とする
請求項１乃至９のいずれかに記載の薄膜半導体装置の製
造方法。11. The method according to claim 1, wherein the proportion of the oxidizing gas in the mixed gas is about 1% or more and about 6% or less.
割合が１.5％程度以上4.5％程度以下で有る事を特徴と
する請求項１乃至９のいずれかに記載の薄膜半導体装置
の製造方法。12. The method according to claim 1, wherein an oxidizing gas accounts for about 1.5% to about 4.5% of the mixed gas. Method.
割合が２％程度以上4％程度以下で有る事を特徴とする
請求項１乃至９のいずれかに記載の薄膜半導体装置の製
造方法。13. The method for manufacturing a thin film semiconductor device according to claim 1, wherein the ratio of the oxidizing gas in the mixed gas is about 2% or more and about 4% or less.
（ｒｆ波）で有り、且つ前記混合気体中に占める酸化性
気体の割合が１％程度以上６％程度以下で有る事を特徴
とする請求項１乃至４のいずれかに記載の薄膜半導体装
置の製造方法。14. The plasma source of the plasma is a radio wave (rf wave), and the ratio of the oxidizing gas in the mixed gas is about 1% or more and about 6% or less. 5. The method for manufacturing a thin film semiconductor device according to any one of 1 to 4.
程度以下で、且つ前記混合気体中に占める酸化性気体の
割合が１．５％程度以上４．５％程度以下で有る事を特
徴とする請求項１乃至７のいずれかに記載の薄膜半導体
装置の製造方法。15. The substrate temperature during the second step is 425 ° C.
8. The thin-film semiconductor device according to claim 1, wherein the ratio of the oxidizing gas in the mixed gas is about 1.5% or more and about 4.5% or less. Manufacturing method.
記第二工程中の基板温度が４２５℃程度以下で有り、前
記プラズマのプラズマ源がラジオ波（ｒｆ波）で有り、
更に前記混合気体中に占める酸化性気体の割合が２％程
度以上４％程度以下で有る事を特徴とする請求項１、
３、および４のいずれかに記載の薄膜半導体装置の製造
方法。16. The semiconductor film is polycrystalline, the substrate temperature during the second step is about 425 ° C. or less, and the plasma source of the plasma is a radio wave (rf wave);
Further, the ratio of the oxidizing gas in the mixed gas is about 2% or more and about 4% or less.
5. The method for manufacturing a thin film semiconductor device according to any one of items 3 and 4.
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| JP2006203038A (en) * | 2005-01-21 | 2006-08-03 | Fujitsu Ltd | Method for forming nitride film, method for manufacturing semiconductor device and capacitor, and device for forming nitride film |
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| WO2011077966A1 (en) * | 2009-12-25 | 2011-06-30 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
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| US7180095B2 (en) | 2003-02-19 | 2007-02-20 | Hitachi Displays, Ltd. | Display device and manufacturing method thereof |
| JP2006203038A (en) * | 2005-01-21 | 2006-08-03 | Fujitsu Ltd | Method for forming nitride film, method for manufacturing semiconductor device and capacitor, and device for forming nitride film |
| US7696107B2 (en) | 2005-01-21 | 2010-04-13 | Fujitsu Microelectronics Limited | Nitride film forming method, semiconductor device fabrication method, capacitor fabrication method and nitride film forming apparatus |
| JP4554378B2 (en) * | 2005-01-21 | 2010-09-29 | 富士通セミコンダクター株式会社 | Nitride film forming method, semiconductor device manufacturing method, and capacitor manufacturing method |
| US7951727B2 (en) | 2005-01-21 | 2011-05-31 | Fujitsu Semiconductor Limited | Capacitor fabrication method |
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| JP2008028252A (en) * | 2006-07-24 | 2008-02-07 | Toshiba Matsushita Display Technology Co Ltd | Processing method and processing device of semiconductor layer, and manufacturing method and manufacturing equipment of thin film transistor |
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