JP2000091260A - Manufacture of semiconductor - Google Patents
Manufacture of semiconductorInfo
- Publication number
- JP2000091260A JP2000091260A JP10262091A JP26209198A JP2000091260A JP 2000091260 A JP2000091260 A JP 2000091260A JP 10262091 A JP10262091 A JP 10262091A JP 26209198 A JP26209198 A JP 26209198A JP 2000091260 A JP2000091260 A JP 2000091260A
- Authority
- JP
- Japan
- Prior art keywords
- temperature
- wafer
- semiconductor
- impurities
- diffusion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体製造方法に関
する。より詳しくは、不純物の増速拡散防止のための急
速昇温工程を施す半導体製造方法に関するものである。[0001] The present invention relates to a semiconductor manufacturing method. More specifically, the present invention relates to a semiconductor manufacturing method for performing a rapid temperature raising step for preventing accelerated diffusion of impurities.
【０００２】[0002]
【従来の技術】Ｓｉ半導体の場合、Ｐ（リン）やＢ（ボ
ロン）といった不純物をイオン化し、これを電界により
加速して、半導体基板中に導入し、ｐ型半導体やｎ型半
導体を形成している。この方法で不純物密度が１ｅ１９
／ｃｍ3 以上になるまでイオンを注入すると、半導体製
造プロセスにおける熱処理工程中に、通常よりもはるか
に大きな熱拡散係数で不純物が熱拡散する増速拡散（照
射促進拡散）が生じる。特に、近年は半導体素子の微細
化のため、イオン注入を半導体基板の浅いところに行う
ので、増速拡散の影響は半導体素子の電気特性に顕著に
表れ、浅い拡散層ができにくく、トランジスタ特性を悪
化させるようになり、半導体回路の製造上問題となって
いた。このような増速拡散現象は、７５０℃前後で行わ
れるＬＰのＣＶＤを用いる絶縁膜形成工程やその他の熱
処理を施す薄膜形成工程において最も顕著に生じてい
た。2. Description of the Related Art In the case of a Si semiconductor, impurities such as P (phosphorus) and B (boron) are ionized, accelerated by an electric field, and introduced into a semiconductor substrate to form a p-type semiconductor or an n-type semiconductor. ing. With this method, the impurity density is 1e19.
When ions are implanted to at least / cm 3, accelerated diffusion (irradiation-enhanced diffusion) occurs in which impurities are thermally diffused with a much larger thermal diffusion coefficient than usual during a heat treatment step in a semiconductor manufacturing process. In particular, in recent years, ion implantation is performed in a shallow place of a semiconductor substrate in order to miniaturize a semiconductor element. Therefore, the effect of the accelerated diffusion is remarkably exhibited in an electric characteristic of the semiconductor element, a shallow diffusion layer is hardly formed, and a transistor characteristic is reduced. It has become a problem in the manufacture of semiconductor circuits. Such an accelerated diffusion phenomenon has occurred most remarkably in an insulating film forming step using LP CVD performed at about 750 ° C. and other thin film forming steps in which heat treatment is performed.
【０００３】このような増速拡散を抑制するため、近年
になり、薄膜形成や、拡散処理などの熱処理工程の前に
数１０℃／秒以上の昇温率で９００℃以上まで短時間で
急速に高温まで昇温するＲＴＡ（Rapid Thermal Annea
l）工程が行われている。図４は従来のＲＴＡ工程の時
間と温度の関係図である。図示したように、時間Ｏから
Ｐの間に数十℃／秒若しくは数百度／秒の昇温率で昇温
したい温度まで昇温し、ある程度保持して時間Ｑから降
温工程を行い、Ｒの時点で完了する。このようなＲＴＡ
を行うことで、前記増速拡散は抑制され、トランジスタ
特性等も大きく改善されることとなった。In recent years, in order to suppress such accelerated diffusion, a rapid temperature rise to 900 ° C. or more at a temperature rise rate of several tens ° C./sec or more before heat treatment steps such as thin film formation and diffusion processing is performed in a short time. RTA (Rapid Thermal Annea)
l) The process is being performed. FIG. 4 is a diagram showing the relationship between time and temperature in a conventional RTA process. As shown in the figure, the temperature is raised from the time O to the temperature P at a heating rate of several tens of degrees Celsius / second or several hundred degrees / second, the temperature is maintained to some extent, and the temperature is reduced from the time Q to the temperature R. Complete at that point. RTA like this
As a result, the enhanced diffusion is suppressed, and the transistor characteristics and the like are greatly improved.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら、上記従
来のＲＴＡは、非常に高い昇温率で温度を上げるため、
拡散炉内部の温度均一性に影響を与える。また、電子素
子を形成するウェーハは年々大口径化しており、これに
起因してウェーハ面内の温度差が大きくなる傾向があ
る。さらに、不純物の熱拡散はＲＴＡの温度、時間、昇
温率に大きく依存するため、半導体素子特性はこれらの
条件によって敏感に変化する。よって、ＲＴＡの急速昇
温の際にウェーハ面内の温度などのバラツキが生じやす
く、これにより、ウェーハ面内の半導体素子特性が不均
一になって製品の歩留まりを悪化させる。However, the above-mentioned conventional RTA raises the temperature at a very high rate,
Affects temperature uniformity inside the diffusion furnace. Further, the diameter of a wafer on which an electronic element is formed is increasing year by year, and as a result, the temperature difference within the wafer surface tends to increase. Further, since the thermal diffusion of the impurities greatly depends on the temperature, time, and rate of temperature rise of the RTA, the characteristics of the semiconductor device are sensitively changed depending on these conditions. Therefore, when the RTA rapidly rises in temperature, variations in the temperature within the wafer surface and the like are likely to occur, thereby causing the semiconductor device characteristics within the wafer surface to become non-uniform, thereby deteriorating the product yield.
【０００５】一方、近年の実験から、イオン注入法によ
りＳｉ基板中に導入した不純物は１０秒以内であれば、
７００度以下の温度で不純物は増速拡散しないことが分
かっている。さらに、７５０度以上の熱処理を行うとき
は、高い昇温率で拡散炉の温度を上昇させ、短時間でＲ
ＴＡを行うことにより増速拡散が抑制されることも分か
っている。On the other hand, according to recent experiments, impurities introduced into a Si substrate by an ion implantation
It has been found that the impurity does not diffuse at a temperature of 700 ° C. or less. Further, when performing a heat treatment at 750 ° C. or higher, the temperature of the diffusion furnace is increased at a high rate of temperature increase, and R
It has also been found that enhanced diffusion is suppressed by performing TA.
【０００６】また、ＲＴＡの工程において、最高温度に
達する前に一度昇温を止め、一定温度の状態を保持し
（Pre Stable工程）、その後再び最高温度まで昇温を行
うことにより、ＲＴＡ時の炉内温度やウェーハ面内温度
のバラツキが安定化することが実験により確認されてい
る。さらにＭＯＳＦＥＴについて、５００℃から７００
℃の間で１０秒間のPre Stable工程を行った後、１００
０℃まで昇温するＲＴＡを施した試料でシート抵抗（電
気抵抗）の測定を行う実験により、シート抵抗のウェー
ハ面内バラツキが減り、特性が安定化することが確認さ
れている。Further, in the RTA process, once the temperature is raised before reaching the maximum temperature, a state of a constant temperature is maintained (Pre Stable process), and then the temperature is raised again to the maximum temperature, whereby the RTA during the RTA is performed. Experiments have confirmed that variations in the furnace temperature and the wafer in-plane temperature are stabilized. In addition, for MOSFETs,
After performing a Pre Stable process for 10 seconds between
From an experiment in which sheet resistance (electrical resistance) is measured on a sample subjected to RTA that is heated to 0 ° C., it has been confirmed that variations in sheet resistance in a wafer surface are reduced and characteristics are stabilized.
【０００７】一方、先行技術として、特開平８-１０７
０６７号公報にＲＴＡ等の多段階のアニールを利用した
半導体の薄膜形成方法が掲載されている。しかしなが
ら、この公報は結晶粒成長のための熱処理プロセスを開
示するものであり、不純物の増速拡散抑制に関しては考
慮しておらず、昇温率や、昇温を止めて保持する時間に
ついては何の規定もない。よってこの公報内容からは増
速拡散抑制やウェーハ面内の温度のバラツキを防ぐ技術
は得られない。On the other hand, Japanese Patent Application Laid-Open No. 8-107
No. 067 discloses a method for forming a thin film of a semiconductor utilizing multi-step annealing such as RTA. However, this publication discloses a heat treatment process for crystal grain growth, and does not consider the suppression of the accelerated diffusion of impurities. There is no provision. Therefore, the technique disclosed in this publication does not provide a technique for suppressing the accelerated diffusion and preventing the temperature variation in the wafer surface.
【０００８】本発明は、上記従来技術を考慮したもので
あり、半導体製造プロセスでの不純物の増速拡散を抑制
し、ウェーハ面内温度や半導体素子特性のバラツキを生
じないＲＴＡ工程を含む半導体製造方法の提供を目的と
する。The present invention has been made in consideration of the above-mentioned prior art, and suppresses the accelerated diffusion of impurities in a semiconductor manufacturing process and includes an RTA process including a wafer surface temperature and a semiconductor element characteristic which do not vary. The purpose is to provide a method.
【０００９】[0009]
【課題を解決するための手段】前記目的を達成するた
め、本発明では、ウェーハ表面にイオンを注入し、不純
物の増速拡散防止のため、このウェーハ表面を数１０℃
／秒以上の昇温率で９００℃以上に急速昇温する急速昇
温工程を施し、その後にウェーハの熱処理工程によって
半導体素子を形成する半導体製造方法において、前記急
速昇温工程時、５００℃以上７００℃以下の間で一旦昇
温を止め、その温度で１秒以上６０秒以下の時間保持す
ることを特徴とする半導体製造方法を提供する。In order to achieve the above object, according to the present invention, ions are implanted into a wafer surface, and the wafer surface is heated to several tens of degrees Celsius in order to prevent accelerated diffusion of impurities.
In a semiconductor manufacturing method in which a semiconductor device is formed by performing a rapid temperature increase step of rapidly increasing the temperature to 900 ° C. or higher at a rate of temperature increase of not less than / ° C. Provided is a method for manufacturing a semiconductor, wherein the temperature is temporarily stopped between 700 ° C. or lower and the temperature is maintained for 1 to 60 seconds.
【００１０】この構成によれば、９００℃以上の高温ま
で急速に昇温するとき、不純物の増速拡散の起こらない
温度で、一旦昇温を止めて保持するので、炉内温度が安
定し、ウェーハ面内温度も均一になるため製造された半
導体素子特性のバラツキが起こらない。ここで昇温を途
中で止める温度を５００℃以上７００℃以下としたの
は、５００℃未満で一旦昇温を止めると、その後の急速
昇温により１度に最高温度まで昇温させると、温度の面
内バラツキが生ずるおそれがあり、７００℃より高い温
度で昇温を止めるとその温度で増速拡散が起こるおそれ
があるからである。また、保持時間を１秒以上６０秒以
下としたのは、１秒未満では途中で昇温を止めて保持す
る効果がなく、６０秒より長くしたのでは増速拡散が起
こる可能性があるからである。According to this configuration, when the temperature is rapidly raised to a high temperature of 900 ° C. or more, the temperature is temporarily stopped and maintained at a temperature at which the accelerated diffusion of impurities does not occur. Since the temperature in the wafer surface is also uniform, the characteristics of the manufactured semiconductor elements do not vary. Here, the reason why the temperature at which the heating is stopped halfway is 500 ° C. or more and 700 ° C. or less is that once the heating is stopped at a temperature lower than 500 ° C., the temperature is raised to the maximum temperature at a time by a rapid temperature rising. This is because in-plane variation may occur, and if the temperature rise is stopped at a temperature higher than 700 ° C., there is a risk that accelerated diffusion may occur at that temperature. In addition, the reason why the holding time is set to 1 second or more and 60 seconds or less is that if it is less than 1 second, there is no effect of stopping and maintaining the temperature rise midway, and if it is longer than 60 seconds, there is a possibility that accelerated diffusion may occur. It is.
【００１１】好ましい構成例においては、前記急速昇温
工程は、薄膜形成又は拡散処理の熱処理工程の前に、こ
れらの熱処理工程での不純物増速拡散防止のために行わ
れるものであることを特徴としている。In a preferred configuration example, the rapid temperature raising step is performed before the heat treatment step of forming or diffusing the thin film, in order to prevent the accelerated diffusion of impurities in these heat treatment steps. And
【００１２】この構成によれば、薄膜形成や拡散処理の
熱処理工程で生じる増速拡散を、事前に急速昇温工程を
行うことにより抑制することができる。According to this configuration, the accelerated diffusion that occurs in the heat treatment step of forming a thin film or the diffusion processing can be suppressed by performing a rapid temperature raising step in advance.
【００１３】[0013]
【発明の実施の形態】図１は、本発明の実施形態のフロ
ーチャートである。図示したように、イオン注入を行っ
た後（Ｓ１）、一回又はそれ以上のPre Stable 工程を
含む２段階又はそれ以上の多段ＲＴＡを行い（Ｓ２）、
そしてＣＶＤなどで熱処理を施しながら絶縁膜を形成す
る（Ｓ３）。このように、多段のＲＴＡを絶縁膜形成の
前に行うことにより、絶縁膜形成のための熱処理での不
純物の増速拡散が阻止されるとともにウェーハ面内温度
のバラツキを抑制することができる。FIG. 1 is a flowchart of an embodiment of the present invention. As shown in the figure, after performing the ion implantation (S1), two or more multi-step RTAs including one or more Pre Stable processes are performed (S2),
Then, an insulating film is formed while performing heat treatment by CVD or the like (S3). As described above, by performing the multi-stage RTA before forming the insulating film, it is possible to prevent the accelerated diffusion of the impurities in the heat treatment for forming the insulating film and to suppress the variation in the temperature in the wafer surface.
【００１４】[0014]
【実施例】昇温率を５０℃／秒、Pre Stable 工程の保
持時間を１０秒として本発明のＲＴＡにおける温度と時
間を表したものが図２と図３である。EXAMPLE FIGS. 2 and 3 show the temperature and time in the RTA of the present invention with the rate of temperature rise being 50 ° C./sec and the holding time of the Pre Stable step being 10 seconds.
【００１５】図２は、ＲＴＡ工程において、１回のPre
Stable工程を行って２段階の急速昇温を行った時の温度
と時間の関係図である。イオン注入などの手段でボロン
（Ｂ）等の３族の原子を導入したＳｉ基板に１０ｎｍ程
度の金属汚染防止用の絶縁膜を堆積した後、イオン注入
機を用いて、この基板にヒ素（Ａｓ）をエネルギー５０
ｋｅＶ、ドーズ量３ｅ１５／ｃｍ2 でイオン注入する。
そして時間ＡからＢまでは７００℃の温度に達するまで
５０℃／秒以上の昇温率で昇温を行い、時間ＣまでPre
Stable 工程を１０秒間行う。その後時間Ｄまでは、１
０００℃に達するまで５０℃／秒以上の昇温率で昇温を
行い、その温度で１０秒間保持し、時間ＥからＦまで降
温率５０℃／秒で室温まで降温工程を行う。FIG. 2 shows one pre-processing in the RTA process.
It is a relation diagram of temperature and time at the time of performing a two-step rapid temperature rise by performing a Stable process. After depositing an insulating film for preventing metal contamination of about 10 nm on a Si substrate into which atoms of Group 3 such as boron (B) have been introduced by ion implantation or the like, arsenic (As) is deposited on the substrate using an ion implanter. ) Energy 50
Ion implantation is performed at keV and a dose of 3e15 / cm 2 .
From time A to time B, the temperature is raised at a rate of 50 ° C./sec or more until the temperature reaches 700 ° C.
Perform the Stable process for 10 seconds. After that, until time D, 1
The temperature is raised at a rate of 50 ° C./sec or more until the temperature reaches 000 ° C., the temperature is maintained for 10 seconds, and the temperature is reduced from time E to F at a rate of 50 ° C./sec to room temperature.
【００１６】図３はＲＴＡ工程において、２回のPre St
able工程を行って３段階の急速昇温を行った時の温度と
時間の関係図である。イオン注入などの手段でボロン
（Ｂ）等の３族の原子を導入したＳｉ基板に１０ｎｍ程
度の金属汚染防止などの絶縁膜を堆積した後、イオン注
入機を用いて、この基板にヒ素（Ａｓ）をエネルギー５
０ｋｅＶ、ドーズ量３ｅ１５／ｃｍ2 でイオン注入す
る。そして時間ＧからＨまでは５００℃の温度に達する
まで５０℃／秒以上の昇温率で昇温を行い、時間Ｉまで
Pre Stable 工程を１０秒間行う。その後時間Ｊまでは
また５０℃／秒の昇温率で７００℃まで昇温し、時間Ｋ
まで再びPre Stable 工程を１０秒間行い、時間Ｌまで
５０℃／秒の昇温率で１０００℃まで昇温を行い、その
温度で１０秒間保持し、時間ＭからＮまで降温率５０℃
／秒で室温まで降温工程を行う。FIG. 3 shows two pre-stamps in the RTA process.
It is a relation diagram of temperature and time at the time of performing three steps of rapid temperature rises by performing the able process. After depositing an insulating film of about 10 nm for preventing metal contamination on a Si substrate into which atoms of group 3 such as boron (B) have been introduced by ion implantation or the like, arsenic (As) is deposited on the substrate using an ion implanter. ) Energy 5
Ion implantation is performed at 0 keV and a dose of 3e15 / cm 2 . From time G to H, the temperature is raised at a rate of 50 ° C./sec or more until the temperature reaches 500 ° C., and until time I.
Perform the Pre Stable process for 10 seconds. Thereafter, until time J, the temperature is raised to 700 ° C. at a rate of 50 ° C./sec.
The pre-stable process is performed again for 10 seconds, the temperature is raised to 1000 ° C. at a rate of 50 ° C./second up to time L, and the temperature is maintained for 10 seconds, and the temperature is reduced from M to N at 50 ° C.
The temperature is lowered to room temperature at a rate of / sec.
【００１７】このようにしてPre Stable 工程を含むＲ
ＴＡを行えば、その後の薄膜形成工程での熱処理におけ
る不純物の増速拡散を防止できるとともにこの増速拡散
防止のためのＲＴＡによるウェーハ面内温度などのバラ
ツキを抑制することができる。 以上のような温度分布
のバラツキを抑えた増速拡散防止のための多段ＲＴＡ
は、例えばＭＯＳＦＥＴ、ｎ型又はｐ型ダイオード、バ
イポーラドランジスタ、サイリスタトランジスタ、発光
ダイオードその他各種半導体素子の製造プロセスに適用
できる。As described above, R including the Pre Stable step
By performing TA, it is possible to prevent accelerated diffusion of impurities in the heat treatment in the subsequent thin film forming step, and to suppress variations in the wafer surface temperature due to RTA for preventing the accelerated diffusion. Multi-stage RTA for preventing accelerated diffusion by suppressing variation in temperature distribution as described above
Can be applied to the manufacturing process of, for example, MOSFETs, n-type or p-type diodes, bipolar transistors, thyristor transistors, light-emitting diodes, and other various semiconductor elements.
【００１８】[0018]
【発明の効果】以上説明したように、本発明では、増速
拡散防止のために９００度以上の高温まで急速に昇温す
るとき、途中の不純物の増速拡散の起こらない温度で、
一旦昇温を止めて保持するので、炉内温度が安定し、ウ
ェーハ面内温度も均一になるため製造された半導体素子
特性のバラツキが起こらず、歩留まりの向上を図ること
ができる。As described above, according to the present invention, when the temperature is rapidly raised to a high temperature of 900 ° C. or more to prevent the accelerated diffusion, at the temperature at which the accelerated diffusion of impurities does not occur,
Since the temperature rise is once stopped and held, the temperature in the furnace is stabilized and the temperature in the wafer surface becomes uniform, so that the characteristics of the manufactured semiconductor elements do not vary, and the yield can be improved.
【図１】 本発明の実施の形態に係る半導体製造方法の
フローチャート。FIG. 1 is a flowchart of a semiconductor manufacturing method according to an embodiment of the present invention.
【図２】 ＲＴＡ工程において、１回のPre Stable工程
を行った時の温度と時間の関係図。FIG. 2 is a diagram showing a relationship between temperature and time when one Pre Stable process is performed in an RTA process.
【図３】 ＲＴＡ工程において、２回のPre Stable工程
を行った時の温度と時間の関係図。FIG. 3 is a diagram showing a relationship between temperature and time when two Pre Stable processes are performed in an RTA process.
【図４】 従来のＲＴＡ工程の時間と温度の関係図。FIG. 4 is a diagram showing the relationship between time and temperature in a conventional RTA process.
Claims (2)
０℃／秒以上の昇温率で９００℃以上に急速昇温する急
速昇温工程を施し、 その後にウェーハの熱処理工程によって半導体素子を形
成する半導体製造方法において、 前記急速昇温工程時に、５００℃以上７００℃以下の間
で一旦昇温を止めて、その温度で１秒以上６０秒以下の
時間保持することを特徴とする半導体製造方法。An ion is implanted into the wafer surface, and the surface of the wafer is reduced to several tens to prevent accelerated diffusion of impurities.
In a semiconductor manufacturing method for performing a rapid temperature raising step of rapidly raising the temperature to 900 ° C. or higher at a temperature rising rate of 0 ° C./second or higher, and then forming a semiconductor element by a heat treatment step of the wafer, A method for manufacturing a semiconductor device, comprising: temporarily stopping the temperature rise between 700C and 700C, and maintaining the temperature for 1 second to 60 seconds.
理の熱処理工程の前に、これらの熱処理工程での不純物
増速拡散防止のために行われるものであることを特徴と
する請求項１に記載の半導体製造方法。2. The method according to claim 1, wherein said rapid temperature raising step is performed prior to heat treatment steps for thin film formation or diffusion processing in order to prevent accelerated diffusion of impurities in said heat treatment steps. 2. The semiconductor manufacturing method according to 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10262091A JP2000091260A (en) | 1998-09-16 | 1998-09-16 | Manufacture of semiconductor |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10262091A JP2000091260A (en) | 1998-09-16 | 1998-09-16 | Manufacture of semiconductor |
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| Publication Number | Publication Date |
|---|---|
| JP2000091260A true JP2000091260A (en) | 2000-03-31 |
Family
ID=17370919
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10262091A Pending JP2000091260A (en) | 1998-09-16 | 1998-09-16 | Manufacture of semiconductor |
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| Country | Link |
|---|---|
| JP (1) | JP2000091260A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006261191A (en) * | 2005-03-15 | 2006-09-28 | Oki Electric Ind Co Ltd | Method of manufacturing semiconductor device |
-
1998
- 1998-09-16 JP JP10262091A patent/JP2000091260A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006261191A (en) * | 2005-03-15 | 2006-09-28 | Oki Electric Ind Co Ltd | Method of manufacturing semiconductor device |
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