JP2000090140A - Estimation method for area and number of layers of printed board - Google Patents
Estimation method for area and number of layers of printed boardInfo
- Publication number
- JP2000090140A JP2000090140A JP10259757A JP25975798A JP2000090140A JP 2000090140 A JP2000090140 A JP 2000090140A JP 10259757 A JP10259757 A JP 10259757A JP 25975798 A JP25975798 A JP 25975798A JP 2000090140 A JP2000090140 A JP 2000090140A
- Authority
- JP
- Japan
- Prior art keywords
- area
- board
- printed board
- parts
- layers
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Supply And Installment Of Electrical Components (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】この発明は、電子機器用のプ
リント基板の部品規模から必要な基板面積を推定する方
法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for estimating a required board area from a component size of a printed board for electronic equipment.
【０００２】[0002]
【従来の技術】従来のピン密度を使った予測方法を、図
４に動作フロー図として示す。従来は、ピン密度−基板
面積、部品密度−基板面積どちらかの相関によって基板
面積を推定していた。図４の方法では、ピン密度に基づ
いて基板面積を決めており、予め過去のデータを蓄積し
ておき、ステップ１５でこれらデータと照合し、適正範
囲であればステップ１４’でプリント基板面積を定めて
いた。このため、推定の精度が悪く事前の基板設計着手
可否の判断が困難で、設計着手後に設計の見直しを行う
場合が多かった。2. Description of the Related Art A conventional prediction method using a pin density is shown in an operation flowchart of FIG. Conventionally, the board area has been estimated based on either the correlation between the pin density and the board area or between the component density and the board area. In the method of FIG. 4, the board area is determined based on the pin density, the past data is stored in advance, and the data is collated in step 15 with the data. I had decided. For this reason, the accuracy of the estimation is poor and it is difficult to judge whether or not to start the board design in advance, and the design is often reviewed after the start of the design.
【０００３】[0003]
【発明が解決しようとする課題】機器の小型化が著しく
進んでいる分野においては、プリント基板は機器内部で
他のデバイスとスペースを最適に分配する必要性があ
り、構想設計段階で実現確度の高い最小の基板サイズを
推定する必要がある。デバイス類は寸法が決定している
が、プリント基板は論理設計と並行して進むため具体的
な寸法を決定しにくい。その結果、サイズにマージンを
取り過ぎたプリント基板設計となり、小型化が十分狙え
ない設計となるか、または、開発の検討初期段階でサイ
ズ検討を時間をかけて行うために、筐体設計の検討を遅
延させるという課題があった。In the field where the miniaturization of equipment has been remarkably progressing, it is necessary to optimally distribute the space between the printed circuit board and other devices inside the equipment. It is necessary to estimate a high minimum substrate size. Although the dimensions of the devices are determined, it is difficult to determine the specific dimensions of the printed circuit board because it proceeds in parallel with the logical design. As a result, a printed circuit board design with an excessive margin in size will result in a design that cannot be aimed at miniaturization sufficiently, or a housing design study will be conducted in order to take time to study the size in the early stage of development study There was a problem of delaying.
【０００４】この発明は、上記のような課題を解決する
ためになされたもので、ピン密度（ｐ）、部品面積率
（ｅ）の２つのパラメータを用いて簡単に精度良く必要
最小限の基板面積を推定することを目的としている。SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and it is simple and accurate using two parameters of a pin density (p) and a component area ratio (e) to minimize a required minimum substrate. It is intended to estimate the area.
【０００５】[0005]
【課題を解決するための手段】この発明に係るプリント
基板面積層数予測方法は、複数の部品を実装する多層プ
リント基板の層数と面積を設定するために、各部品の端
子ピン数を集計するピン総数集計ステップと、各部品の
基板面での実装面積を集計する部品面積集計ステップ
と、所定のピン密度／基板層数／部品面積相関関係に基
づいて基板面積と層数を設定する評価ステップを備え
た。According to the present invention, a method for estimating the number of layers of a printed circuit board according to the present invention collects the number of terminal pins of each component in order to set the number of layers and the area of a multilayer printed circuit board on which a plurality of components are mounted. Totaling step for totaling the number of pins, component area totaling step for totalizing the mounting area of each component on the board surface, and evaluation for setting the board area and the number of layers based on a predetermined pin density / number of board layers / component area correlation. With steps.
【０００６】また更に、所定のピン密度／基板層数／部
品面積相関関係に基づいて得た基板面積と層数が別に定
めた規定の基板面積を超える場合は、基板面積を増減さ
せる評価ステップを繰り返すようにした。Further, when the board area and the number of layers obtained based on the predetermined pin density / number of board layers / component area correlation exceed a prescribed board area defined separately, an evaluation step of increasing or decreasing the board area is performed. I tried to repeat.
【０００７】[0007]
【発明の実施の形態】実施の形態１．当然のことなが
ら、プリント基板の面積を定めるには多くのパラメータ
に基づいて決定するほど矛盾が少なく、適切な値が得ら
れる。ただ、最小のパラメータ数で適正値を得るにはど
んなパラメータ値がよいか判らなかった。本実施の形態
においては、ピン密度（ｐ）、部品面積率（ｅ）の２つ
のパラメータからプリント基板の必要面積を推定するこ
とが最もよいことが判った。この具体的な面積推定方法
として、ここで、ピン密度（ｐ）を次の式（１）で表現
し、 ｐ＝Ｐｓ／Ｅ （１） ここで、Ｐｓ：プリント基板に搭載する部品のピン総数
［ピン］ Ｅ：プリント基板面積［ｃｍ2 ］ 部品面積率（ｅ）を次式（２）で表現し、 ｅ＝Ｅｐ／Ｅ （２） ここで、Ｅｐ：プリント基板に搭載する部品の総面積
［ｃｍ2 ］ Ｅ：プリント基板面積［ｃｍ2 ］ この２つの式で表される数値を図２の相関図上にプロッ
トして、予め判っている適正範囲領域にあるかを調べる
のである。DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 As a matter of course, in determining the area of the printed circuit board, the inconsistency becomes smaller as the number of parameters is determined based on many parameters, and an appropriate value is obtained. However, I did not know what parameter value was good to obtain an appropriate value with the minimum number of parameters. In the present embodiment, it has been found that it is best to estimate the required area of the printed circuit board from the two parameters of the pin density (p) and the component area ratio (e). As a specific area estimation method, the pin density (p) is expressed by the following equation (1): p = Ps / E (1) where Ps: the total number of pins of components mounted on a printed circuit board [Pin] E: Printed circuit board area [cm 2 ] Component area ratio (e) is expressed by the following equation (2): e = Ep / E (2) where Ep: Total area of components mounted on printed circuit board [Cm 2 ] E: Printed circuit board area [cm 2 ] The numerical values represented by these two equations are plotted on the correlation diagram of FIG. 2 to check whether or not the values are within a proper range that is known in advance.
【０００８】以下、実施の形態における基板面積層数予
測方法を説明する。図１は、本実施の形態における予測
方法の手順を示すフローチャートである。図において、
１は既存回路部品表の有無確認ステップ、２は回路部品
表新規作成ステップ、３は既存回路部品表検索ステッ
プ、４は回路部品表編集のための部品型名確認ステッ
プ、５は部品型名検索ステップ、６は回路部品表の編集
ステップ、７は回路部品表編集作業完了確認ステップ、
８は部品表名と基板仕様選択ステップ、９は部品面積集
計ステップ、１０はピン総数集計ステップ、１１は図３
に示すフォーマットの部品の外形寸法データを格納して
ある部品形状データベース部、１２は部品面積率、ピン
密度評価ステップ、１３は基板面積変更ステップ、１４
は基板必要面積決定ステップ、１６は図２に示すピン密
度／部品面積率相関関係データベース部である。Hereinafter, a method of estimating the number of layers in the substrate area according to the embodiment will be described. FIG. 1 is a flowchart showing the procedure of the prediction method according to the present embodiment. In the figure,
1 is a step for confirming the existence of an existing circuit parts table, 2 is a step for newly creating a circuit parts table, 3 is a step for searching an existing circuit parts table, 4 is a step for confirming a part type name for editing a circuit parts table, and 5 is a part type name search. Step 6, a step of editing a circuit parts list, step 7, a step of confirming completion of editing work of a circuit parts list,
8 is a part table name and board specification selecting step, 9 is a part area totaling step, 10 is a total pin number totaling step, and 11 is FIG.
, A component area database and a pin density evaluation step, 13 a board area change step, and 14 a component area database.
Denotes a board necessary area determining step, and 16 denotes a pin density / component area ratio correlation database section shown in FIG.
【０００９】図２は、過去の設計データを元にプロット
した設計実績データである。図において、部品面積率、
ピン密度評価ステップ１２で得た値をプロットして部品
搭載可否を判断するために、適切なピン密度（ｐ）、部
品面積率（ｅ）の範囲が基板仕様毎に濃色の枠で囲んで
示してある。FIG. 2 shows design result data plotted based on past design data. In the figure, the component area ratio,
In order to plot the values obtained in the pin density evaluation step 12 to determine whether or not components can be mounted, the range of appropriate pin density (p) and component area ratio (e) is surrounded by a dark frame for each board specification. Is shown.
【００１０】具体的に面積層数を推定する動作を説明す
る。 （１）図１の集計ステップ９と１０により図３に示す部
品形状データベースに格納されているパッド外形Ｘ，Ｙ
とピン数のデータを参照して、部品表からピン総数（Ｐ
ｓ）と部品総面積（Ｅｐ）を求める。 （２）また、構造設計における制約条件などから許され
る基板面積を仮定する。 （３）評価ステップ１２において、ピン密度と部品面積
率を上記パラメータから式（１）と式（２）により求め
る。 （４）このｐ（ｚ），ｅ（ｚ）を図２上にプロットす
る。 （５）プロットした点が過去の実績領域、即ち、濃色枠
内から大きく逸脱する場合は、（２）に戻り基板面積の
仮定を緩めて再度（３），（４）のプロセスを行う。即
ち、プロットした値が過去の実績領域より小さい場合
は、基板面積を更に小さくし、大きな場合は、基板面積
を更に大きくすることにより、プロット値を領域内に入
るように最適値を決定する。プロット点が過去の実績領
域の近傍になるまでこの操作を繰り返し、或いは、層数
を増加して最適面積を決定する。The operation for estimating the number of area layers will be specifically described. (1) Pad outlines X and Y stored in the component shape database shown in FIG. 3 by the counting steps 9 and 10 in FIG.
And the data of the number of pins, and refer to the total number of pins (P
s) and the total component area (Ep) are determined. (2) Assume a substrate area that is allowed due to constraints in the structural design and the like. (3) In the evaluation step 12, the pin density and the component area ratio are obtained from the above parameters by the equations (1) and (2). (4) P (z) and e (z) are plotted on FIG. (5) If the plotted points greatly deviate from the past result area, that is, from within the dark frame, the process returns to (2), relaxes the assumption of the substrate area, and performs the processes (3) and (4) again. That is, when the plotted value is smaller than the past performance area, the substrate area is further reduced, and when the plotted value is larger, the substrate area is further increased, so that the optimum value is determined so that the plot value falls within the area. This operation is repeated until the plot point is in the vicinity of the past performance area, or the optimum area is determined by increasing the number of layers.
【００１１】このようにして、従来では手直しが不可避
であったのが、２つの適切なパラメータを選ぶことで相
互の許容領域を相関図示に明示して修正方向を明らかに
して、小型化限界と実現性を両立させたプリント基板面
積（Ｅ）を容易に決定することができる。なお、図１の
ステップ１２，１３を繰り返しても、図２のいずれの適
正枠内にも納まらない場合は、設計不可を出力し、装置
の基本設計を見直すよう警告をする。こうして、できる
だけ設計の前段階で修正を行い、大幅な手戻りを防ぐ効
果がある。In this way, in the past, rework was unavoidable. However, by selecting two appropriate parameters, the mutual permissible area is clearly shown in the correlation diagram to clarify the correction direction, and the miniaturization limit and The printed circuit board area (E) that achieves both feasibility can be easily determined. Note that, even if steps 12 and 13 in FIG. 1 are repeated, if the values do not fall within any of the appropriate frames in FIG. 2, a design failure is output and a warning is issued to review the basic design of the apparatus. In this way, there is an effect that the correction is made as much as possible before the design to prevent a significant rework.
【００１２】[0012]
【発明の効果】以上のように、この発明によれば、２つ
のパラメータピン密度（ｐ）、部品面積率（ｅ）の相関
関係を利用するので、プリント基板の必要面積を精度良
く推定して設計の手戻りを防ぐ効果がある。As described above, according to the present invention, since the correlation between the two parameters, pin density (p) and component area ratio (e), is used, the required area of the printed circuit board can be accurately estimated. This has the effect of preventing design rework.
【図１】 この発明の実施の形態１におけるプリント基
板面積層予測方法の手順を示すフローチャート図であ
る。FIG. 1 is a flowchart showing a procedure of a printed circuit board area layer prediction method according to Embodiment 1 of the present invention.
【図２】 部品搭載可否を判断するためのピン密度
（ｐ）、部品面積率（ｅ）の適正範囲を枠表示した相関
図である。FIG. 2 is a correlation diagram in which an appropriate range of a pin density (p) and a component area ratio (e) for judging whether components can be mounted is framed.
【図３】 部品形状データベースのフォーマット例を示
す図である。FIG. 3 is a diagram showing a format example of a part shape database.
【図４】 従来の実装面積推定方法の手順を示すフロー
チャート図である。FIG. 4 is a flowchart illustrating a procedure of a conventional mounting area estimation method.
１ 既存回路部品表の有無確認判断ステップ、２ 回路
部品表新規作成ステップ、３ 既存回路部品表検索ステ
ップ、４ 回路部品表編集のための部品型名確認ステッ
プ、５ 部品型名検索ステップ、６ 回路部品表の編集
ステップ、７回路部品表編集作業完了確認ステップ、８
部品表名と基板仕様選択ステップ、９ 部品面積集計
ステップ、１０ ピン総数集計ステップ、１１ 部品形
状データベース部、１２ 部品面積率、ピン密度評価ス
テップ、１３ 基板面積変更ステップ、１４ 基板必要
面積決定ステップ、１５ ピン密度評価ステップ、１６
ピン密度／部品面積率相関関係データベース部。1. Checking step of existence of existing circuit parts list, 2. Creating new circuit parts table, 3. Searching existing circuit parts table, 4. Checking part type name for editing circuit parts list, 5. Part type name searching step, 6. Circuit BOM editing step, 7 Circuit BOM editing work completion confirmation step, 8
Parts table name and board specification selection step, 9 parts area totaling step, 10 pins totaling step, 11 parts shape database part, 12 parts area ratio, pin density evaluation step, 13 board area changing step, 14 board necessary area determining step, 15 Pin density evaluation step, 16
Pin density / part area ratio correlation database part.
Claims (2)
の層数と面積を設定するために、 上記各部品の端子ピン数を集計するピン総数集計ステッ
プと、 上記各部品の基板面での実装面積を集計する部品面積集
計ステップと、 所定のピン密度／基板層数／部品面積相関関係に基づい
て基板面積と層数を設定する評価ステップを備えたこと
を特徴とするプリント基板面積層数予測方法。A step of totalizing the number of terminal pins of each of the components to set the number of layers and the area of a multilayer printed circuit board on which a plurality of components are mounted; and mounting the components on the board surface. A printed circuit board area layer number prediction, comprising: a component area totaling step of totaling areas; and an evaluation step of setting a board area and a layer number based on a predetermined pin density / number of board layers / component area correlation. Method.
関関係に基づいて得た基板面積と層数が別に定めた規定
の基板面積を超える場合は、基板面積を増減させる評価
ステップを繰り返すことを特徴とする請求項１記載のプ
リント基板面積層数予測方法。2. When the board area and the number of layers obtained based on a predetermined pin density / number of board layers / component area correlation exceed a prescribed board area defined separately, an evaluation step of increasing or decreasing the board area is repeated. 2. The method according to claim 1, further comprising the steps of:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10259757A JP2000090140A (en) | 1998-09-14 | 1998-09-14 | Estimation method for area and number of layers of printed board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10259757A JP2000090140A (en) | 1998-09-14 | 1998-09-14 | Estimation method for area and number of layers of printed board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2000090140A true JP2000090140A (en) | 2000-03-31 |
Family
ID=17338543
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10259757A Pending JP2000090140A (en) | 1998-09-14 | 1998-09-14 | Estimation method for area and number of layers of printed board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2000090140A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008009909A (en) * | 2006-06-30 | 2008-01-17 | Ricoh Co Ltd | Circuit board design support system, circuit board design support method, and program |
| US7356790B2 (en) | 2004-07-01 | 2008-04-08 | Nec Corporation | Device, method and program for estimating the number of layers BGA component mounting substrate |
| WO2023013708A1 (en) * | 2021-08-04 | 2023-02-09 | 株式会社Flosfia | Design assistance device, design assistance program and design assistance method |
-
1998
- 1998-09-14 JP JP10259757A patent/JP2000090140A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7356790B2 (en) | 2004-07-01 | 2008-04-08 | Nec Corporation | Device, method and program for estimating the number of layers BGA component mounting substrate |
| JP2008009909A (en) * | 2006-06-30 | 2008-01-17 | Ricoh Co Ltd | Circuit board design support system, circuit board design support method, and program |
| JP4647554B2 (en) * | 2006-06-30 | 2011-03-09 | 株式会社リコー | Substrate design support system and program |
| WO2023013708A1 (en) * | 2021-08-04 | 2023-02-09 | 株式会社Flosfia | Design assistance device, design assistance program and design assistance method |
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