JP2000077527A - Manufacturing process for semiconductor element provided with mutual connection of copper - Google Patents
Manufacturing process for semiconductor element provided with mutual connection of copperInfo
- Publication number
- JP2000077527A JP2000077527A JP11239079A JP23907999A JP2000077527A JP 2000077527 A JP2000077527 A JP 2000077527A JP 11239079 A JP11239079 A JP 11239079A JP 23907999 A JP23907999 A JP 23907999A JP 2000077527 A JP2000077527 A JP 2000077527A
- Authority
- JP
- Japan
- Prior art keywords
- copper
- layer
- substrate
- electroplated
- grain size
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 title claims abstract description 105
- 229910052802 copper Inorganic materials 0.000 title claims abstract description 105
- 239000010949 copper Substances 0.000 title claims abstract description 105
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 239000004065 semiconductor Substances 0.000 title description 9
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 230000004888 barrier function Effects 0.000 claims abstract description 20
- 239000003989 dielectric material Substances 0.000 claims abstract description 11
- 238000000137 annealing Methods 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 43
- 238000011049 filling Methods 0.000 claims description 6
- 238000007373 indentation Methods 0.000 claims description 4
- 150000002894 organic compounds Chemical class 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 22
- 238000009792 diffusion process Methods 0.000 abstract description 15
- 238000009713 electroplating Methods 0.000 abstract description 12
- 239000000463 material Substances 0.000 abstract description 12
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 11
- 239000000377 silicon dioxide Substances 0.000 abstract description 11
- 229910052751 metal Inorganic materials 0.000 description 24
- 239000002184 metal Substances 0.000 description 24
- 238000000151 deposition Methods 0.000 description 18
- 230000008021 deposition Effects 0.000 description 14
- 238000005240 physical vapour deposition Methods 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 238000005498 polishing Methods 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 5
- 230000009977 dual effect Effects 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 5
- 235000012431 wafers Nutrition 0.000 description 5
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 4
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 4
- 239000004642 Polyimide Substances 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 230000002950 deficient Effects 0.000 description 3
- 230000001590 oxidative effect Effects 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 229920001721 polyimide Polymers 0.000 description 3
- 229920000642 polymer Polymers 0.000 description 3
- RTZKZFJDLAIYFH-UHFFFAOYSA-N Diethyl ether Chemical compound CCOCC RTZKZFJDLAIYFH-UHFFFAOYSA-N 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 230000004913 activation Effects 0.000 description 2
- 229910052786 argon Inorganic materials 0.000 description 2
- ARUVKPQLZAKDPS-UHFFFAOYSA-L copper(II) sulfate Chemical compound [Cu+2].[O-][S+2]([O-])([O-])[O-] ARUVKPQLZAKDPS-UHFFFAOYSA-L 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 239000006259 organic additive Substances 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 239000005360 phosphosilicate glass Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- QAOWNCQODCNURD-UHFFFAOYSA-L Sulfate Chemical compound [O-]S([O-])(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-L 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 230000002378 acidificating effect Effects 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000003197 catalytic effect Effects 0.000 description 1
- 239000003153 chemical reaction reagent Substances 0.000 description 1
- 229910000365 copper sulfate Inorganic materials 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000001627 detrimental effect Effects 0.000 description 1
- 230000003292 diminished effect Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004070 electrodeposition Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229920002313 fluoropolymer Polymers 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
- 239000003446 ligand Substances 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000006263 metalation reaction Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910052758 niobium Inorganic materials 0.000 description 1
- 239000010955 niobium Substances 0.000 description 1
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 description 1
- 230000006911 nucleation Effects 0.000 description 1
- 238000010899 nucleation Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920000728 polyester Polymers 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000002310 reflectometry Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- -1 silicon oxide nitride Chemical class 0.000 description 1
- 239000002002 slurry Substances 0.000 description 1
- 229910021653 sulphate ion Inorganic materials 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
- H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electroplating Methods And Accessories (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は集積回路素子、特に銅に
よる相互接続を有する半導体素子の製造プロセスに関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a process for manufacturing integrated circuit devices, particularly semiconductor devices having copper interconnects.
【0002】[0002]
【従来の技術】素子がサブミクロンの寸法で設計される
ようになり、信頼のおけるサブミクロンの相互接続を形
成することが次第に困難になりつつある。多くの技術を
用いて相互接続が形成されてきた。しかしながらサブミ
クロンの相互接続の寸法が小さくなるにれて、これまで
の技術の有用性は減少してきた。BACKGROUND OF THE INVENTION As devices are being designed with sub-micron dimensions, it is becoming increasingly difficult to form reliable sub-micron interconnects. Interconnects have been formed using a number of techniques. However, as sub-micron interconnect dimensions shrink, the usefulness of previous techniques has diminished.
【0003】例えばエネルギー感受性材料層に画成され
たパターンが適切なエッチングによって下層にある金属
層に転写されるというリソグラフィー技術を用いて金属
層のパターン付けによって相互接続線を形成することを
必要とする技術はいくつかの問題を含んでいる。これら
の技術ではコンタクトホール(窓やバイアス)が誘電体
材料層に形成される。そのコンタクトホールは誘電体層
の上に金属層を堆積することによって金属によって満た
される。誘電体層上に堆積された金属層の部分はエッチ
ングや化学的機械的研磨(CMP)のような適切な手段
で除去される。金属層の残存部分が誘電体層に形成され
たコンタクトホール部分にある。[0003] It is necessary to form interconnect lines by patterning the metal layer using, for example, lithographic techniques in which the pattern defined in the layer of energy sensitive material is transferred to the underlying metal layer by appropriate etching. The techniques involved have several problems. In these techniques, contact holes (windows and vias) are formed in the dielectric material layer. The contact hole is filled with a metal by depositing a metal layer over the dielectric layer. Portions of the metal layer deposited on the dielectric layer are removed by any suitable means such as etching or chemical mechanical polishing (CMP). The remaining portion of the metal layer is in a contact hole portion formed in the dielectric layer.
【0004】金属の第二の層が金属で充填されたコンタ
クトホールを伴う誘電体層の上に形成される。第二の金
属層は従来の減色法によって相互接続を形成するために
パターン付けされる。典型としてはコンタクトホールを
満たしている金属が第一の金属(例えばCVD(化学的
蒸着法)によるタングステン)で、パターン付けされた
金属が第二の金属(例えばアルミニウム)である。第二
の金属層はリソグラフィー技術を用いてパターン付けさ
れる。[0004] A second layer of metal is formed over the dielectric layer with contact holes filled with metal. The second metal layer is patterned to form an interconnect by a conventional subtractive color method. Typically, the metal filling the contact hole is a first metal (eg, tungsten by CVD (chemical vapor deposition)) and the patterned metal is a second metal (eg, aluminum). The second metal layer is patterned using lithographic techniques.
【0005】そのようなプロセスはある種の関連した問
題を有している。特にパターン付けされたアルミニウム
層が側壁腐食にさらされることである。パターン付けさ
れた金属線の間のスペースもまた、更なるプロセスの前
に誘電体層で満たされなければならない。さらに相互接
続(例えばタングステン)とワイヤー(例えばアルミニ
ウム)に対して異なる金属を用いることは機械的な強度
と相互接続の電気的な質との両方に対して悪影響を及ぼ
す。[0005] Such a process has certain related problems. In particular, the patterned aluminum layer is subject to sidewall corrosion. The space between the patterned metal lines must also be filled with a dielectric layer before further processing. Furthermore, the use of different metals for interconnects (eg, tungsten) and wires (eg, aluminum) has a detrimental effect on both mechanical strength and electrical quality of the interconnect.
【0006】[0006]
【発明が解決しようとする課題】銅は低価格で低抵抗で
あるために、現在相互接続用の金属材料として研究され
ている。しかし、銅をエッチングすることは困難であ
る。それゆえ金属による相互接続線をエッチングするこ
とを必要とするプロセスは銅による相互接続を形成する
際に役に立たない。見込みのある相互接続を形成するた
めの技術として二重ダマシーンプロセスがある。(また
は一つのダマシーンプロセスを組み合わせ)二重ダマシ
ーンプロセスにおいて一層の誘電体層が堆積され、2段
階エッチングプロセスを用いてパターン付けされる。第
一段階では誘電体層の厚みの半分か更に多くを通すコン
タクト開口部をエッチングし、第二段階では残りの厚み
の誘電体層から下層までコンタクト開口部をエッチング
して誘電体層を通して相互接続チャネル(すなわち溝)
を分割する。Copper is currently being studied as a metal material for interconnects because of its low cost and low resistance. However, it is difficult to etch copper. Therefore, processes that require etching metal interconnect lines are useless in forming copper interconnects. A technique for forming potential interconnects is a dual damascene process. In a dual damascene process (or a combination of one damascene process), one dielectric layer is deposited and patterned using a two-step etching process. The first stage etches the contact openings that pass through half or more of the thickness of the dielectric layer, and the second stage etches the contact openings from the remaining thickness of the dielectric layer to the bottom and interconnects through the dielectric layer Channel (ie groove)
Split.
【0007】二重ダマシーンプロセスにおいてリソグラ
フィー技術とエッチング手段は銅層のパターン付けを必
要としないので、二重ダマシーンプロセスは従来の減色
法に比較すると銅による相互接続形成に対して有利であ
る。しかし二重ダマシーンプロセスでコンタクト開口部
の縦横比(例えば高さとへこみの幅の比)が2:1、
3:1あるいはそれ以上であるため、銅の堆積は困難で
ある。縦横比が高いときスパッター蒸着は困難である。
銅はコンタクト開口部と相互接続チャネルにCVD法に
より堆積される。しかしながら銅をCVD法によって堆
積することは困難であるか高価であるか、又はその両方
である。結果として銅は一般的な製造過程でCVD法に
よって堆積されていない。[0007] The dual damascene process is advantageous for copper interconnect formation as compared to conventional subtractive methods, because the lithographic techniques and etching means do not require patterning of the copper layer in the dual damascene process. . However, in the dual damascene process, the aspect ratio of the contact opening (for example, the ratio of the height to the width of the depression) is 2: 1,
Since it is 3: 1 or higher, copper deposition is difficult. Sputter deposition is difficult when the aspect ratio is high.
Copper is deposited by CVD on contact openings and interconnect channels. However, depositing copper by the CVD method is difficult, expensive, or both. As a result, copper has not been deposited by CVD in a typical manufacturing process.
【0008】非電気金属堆積(すなわち非電気メッキ)
が誘電体材料のパターン付けされた層に銅を堆積するた
めの技術として研究されてきた。この技術においてメッ
キされる表面(例えばコンタクト開口部(窓やバイア
ス)と相互接続チャネル)は、非電気堆積を達成する金
属の堆積の前に前処理されなければならない。低い堆積
レートと溶液の安定性という問題がこの手法をもちいて
製作することを魅力のないものとしている。さらに触媒
金属や活性化溶液処理の物理的蒸着(PVD、例えばス
パッター)のような現在の表面活性化技術は困難である
か現在の素子作成プロセスに相反するかのどちらかであ
る。Non-electrometallic deposition (ie non-electroplating)
Has been studied as a technique for depositing copper on patterned layers of dielectric material. Surfaces to be plated in this technique (eg, contact openings (windows and vias) and interconnect channels) must be pre-treated before metal deposition to achieve non-electrodeposition. The problems of low deposition rates and solution stability make fabrication with this approach unattractive. In addition, current surface activation techniques, such as physical vapor deposition (PVD, e.g., sputtering) of catalytic metal and activation solution treatment, are either difficult or conflict with current device fabrication processes.
【0009】銅によるその主な利点はその相対的な低価
格と低抵抗である。しかし銅はシリコン、二酸化シリコ
ン、ポリイミドのような低い誘電定数のポリマーのなか
での比較的大きい拡散係数を持っている。相互接続から
の銅が二酸化シリコンやポリマーの層を通して下層のシ
リコンに拡散するかも知れない。下層シリコン基板への
銅の拡散は完成したデバイスのトランジスター特性を低
下させ得る。銅による相互接続線は二酸化シリコン層へ
の拡散を防ぐために少なくとも一つの拡散障壁によって
隔てられるべきである。この拡散障壁の形成は銅による
相互接続形成に関連したもう一つの問題でもある。[0009] The main advantage of copper is its relatively low cost and low resistance. However, copper has a relatively large diffusion coefficient in low dielectric constant polymers such as silicon, silicon dioxide, and polyimide. Copper from the interconnect may diffuse into the underlying silicon through layers of silicon dioxide or polymer. Diffusion of copper into the underlying silicon substrate can degrade the transistor characteristics of the finished device. Copper interconnect lines should be separated by at least one diffusion barrier to prevent diffusion into the silicon dioxide layer. The formation of this diffusion barrier is another problem associated with copper interconnect formation.
【0010】US特許第5,627,102号でShinri
ki等が記載しているように金属相互接続の形成に関連し
た一つの問題はへこみを満たした金属のなかに隙間が形
成されることである。そのような欠陥のある充填は確実
な電気コンタクトの確立の失敗を導く。縦横比の増加に
つれて欠陥のある充填の問題は増加する。したがって、
へこみの幅が減少するにつれて欠陥のある充填に関連す
る問題は増大する。それゆえ、銅による相互接続に関連
した現在の問題を計算に入れた銅による相互接続作成の
ためのプロセスが望まれている。No. 5,627,102 to Shinri
One problem associated with the formation of metal interconnects, as described by ki et al., is that gaps are formed in the metal that fills the dents. Such defective filling leads to a failure to establish a reliable electrical contact. As the aspect ratio increases, the problem of defective filling increases. Therefore,
The problem associated with defective filling increases as the width of the indent decreases. Therefore, there is a need for a process for making copper interconnects that accounts for current problems associated with copper interconnects.
【0011】[0011]
【課題を解決するための手段】本発明は、少なくとも一
つの相互接続が銅によって構成される半導体素子製造プ
ロセスに関する。本発明のプロセスにおいて、銅や銅の
合金は、半導体基板上の誘電体層の表面に形成されたへ
こみに電気的に堆積される。(すなわち単一のダマシー
ンプロセス)誘電体層には二酸化シリコンや低い誘電定
数の例えばポリイミドやポリエステルのようなポリマー
といった材料が用いられる。便宜上、へこみは溝に言及
するが、当業者であればへこみ部分の形状がデザインの
選択によるものだと理解できるだろう。SUMMARY OF THE INVENTION The present invention relates to a semiconductor device manufacturing process wherein at least one interconnect is comprised of copper. In the process of the present invention, copper or an alloy of copper is electrically deposited in a dent formed on the surface of the dielectric layer on the semiconductor substrate. (I.e., a single damascene process) For the dielectric layer, a material such as silicon dioxide or a polymer having a low dielectric constant such as polyimide or polyester is used. For convenience, the indentation refers to the groove, but those skilled in the art will recognize that the shape of the indentation is a matter of design choice.
【0012】銅は誘電材料に拡散するので、銅の拡散に
対する障壁が一般的に必要である。そのような障壁は一
般的には銅がへこみに堆積される前に誘電体層のへこみ
に形成される。しかしながら障壁は、銅がへこみに堆積
された後に隣接する誘電体材料へ銅の拡散を防ぐように
銅と誘電体の界面に障壁層を形成するために銅のドーピ
ング及びドーパント材料を外部拡散させることによって
形成されるかもしれない。銅の拡散に対する障壁として
働く材料は当業者には良く知られている。ふさわしい障
壁材料の例として、タンタル、タンタル窒化物やチタニ
ウム窒化物がある。障壁層の厚さは少なくとも約10n
mである。Since copper diffuses into the dielectric material, a barrier to copper diffusion is generally required. Such barriers are typically formed in the dielectric layer depressions before the copper is deposited in the depressions. However, the barrier may be a copper doping and outdiffusion of the dopant material to form a barrier layer at the copper-dielectric interface to prevent the diffusion of copper into the adjacent dielectric material after the copper is deposited in the depression. May be formed by Materials that act as barriers to copper diffusion are well known to those skilled in the art. Examples of suitable barrier materials include tantalum, tantalum nitride and titanium nitride. The thickness of the barrier layer is at least about 10 n
m.
【0013】溝への銅の電気メッキの前に種層がそこに
形成される。種層の厚さは少なくとも約5nmである。
種層はへこみへの銅の電気メッキに対する陰極として作
用する。銅の種層はPVD,CVDや非電気メッキのよ
うな従来法によって堆積される。[0013] A seed layer is formed therein prior to electroplating the trench with copper. The thickness of the seed layer is at least about 5 nm.
The seed layer acts as a cathode for copper electroplating into the dents. The copper seed layer is deposited by conventional methods such as PVD, CVD and non-electroplating.
【0014】銅の層は基板上に形成された誘電体層の障
壁によって覆われた表面に電気メッキされる。銅の層は
基板の全表面に形成される。銅の層は研磨され、銅の残
存部分は溝の中の銅の部分だけとなる。電気メッキされ
た銅の層は当業者には良く知られた従来法によって研磨
される。化学的機械的研磨が適した方法の一例である。A layer of copper is electroplated on the surface covered by the barrier of the dielectric layer formed on the substrate. A layer of copper is formed on the entire surface of the substrate. The copper layer is polished, leaving only the copper in the trench. The electroplated copper layer is polished by conventional methods well known to those skilled in the art. Chemical mechanical polishing is an example of a suitable method.
【0015】銅の電気メッキ層研磨の前後のどちらかで
基板がアニールされる。アニールの温度と時間は、堆積
時の小さい粒状態から大きい粒状態に電気メッキされた
銅の粒構造がなるように選択される。本発明の目的のた
めの小さい粒状態とは平均して約0.1μmないし約
0.2μmの粒の大きさである。大きい粒の状態とは粒
の大きさが少なくとも1方向において少なくとも1ミク
ロンの状態である。ある実施例では粒の大きさは銅が堆
積されるへこみの大きさによって制限される。例えば銅
が1ミクロンより狭い幅の溝に堆積されるとき、大きい
粒の平均の大きさは少なくとも銅が堆積された溝の幅と
同じであり、少なくとも溝の長さ方向には約1μmの大
きさである。限られた範囲で銅が堆積されるとき、粒の
大きさが小さくなればなるほど充填率は良くなる。しか
し銅が堆積された後、完成された素子の電気特性を改善
するために銅の粒の大きさを大きい粒の状態まで増加さ
せることが都合がよい。The substrate is annealed either before or after polishing the copper electroplated layer. The temperature and duration of the anneal are selected so that the grain structure of the electroplated copper changes from a small grain state during deposition to a large grain state. A small grain state for the purposes of the present invention is a grain size on average of about 0.1 μm to about 0.2 μm. The large grain state is a state where the grain size is at least 1 micron in at least one direction. In some embodiments, the size of the grains is limited by the size of the pit on which the copper is deposited. For example, when copper is deposited in trenches less than 1 micron wide, the average size of the large grains is at least as large as the width of the trench in which the copper was deposited, and at least about 1 μm along the length of the trench. That's it. When copper is deposited in a limited area, the smaller the grain size, the better the filling factor. However, after the copper has been deposited, it is convenient to increase the size of the copper grains to a larger grain size in order to improve the electrical properties of the completed device.
【0016】有機添加物の入った電解漕を用いて小さい
粒の銅を電気メッキしたとき、銅の粒の構造は周囲の状
況により不安定である。本発明のプロセスにおいて堆積
の後、時がたっても安定な銅の粒の構造を作成するため
に堆積された銅はアニールされる。When electroplating small grains of copper using an electrolytic bath containing organic additives, the structure of the grains of copper is unstable due to the surrounding conditions. After deposition in the process of the present invention, the deposited copper is annealed to create a copper grain structure that is stable over time.
【0017】溝の幅が約0.1μmないし約5μmの場
合での本発明の実施例において、もしメッキされた銅の
膜(堆積時の小さい粒の状態)の粒の平均直径が約0.
1μmないし0.2μmまでであれば都合がよい。必要
とされる安定性を持った大きい粒状態の銅を得るために
基板は非酸化雰囲気の下で約100度ないし400度の
範囲の温度で約1分から約1時間アニールされる。本発
明の目的のための非酸化雰囲気とは真空か、あるいは水
素、窒素又はアルゴンのような非酸化ガスである。In embodiments of the present invention where the width of the groove is from about 0.1 μm to about 5 μm, if the plated copper film (in the form of small grains at the time of deposition) has an average grain diameter of about 0.5 μm.
It is convenient if it is up to 1 μm to 0.2 μm. The substrate is annealed in a non-oxidizing atmosphere at a temperature in the range of about 100 degrees to about 400 degrees for about 1 minute to about 1 hour to obtain large grain copper with the required stability. A non-oxidizing atmosphere for the purposes of the present invention is a vacuum or a non-oxidizing gas such as hydrogen, nitrogen or argon.
【0018】銅の層が研磨され、アニールされた後、基
板上に不活性層が形成される。不活性層は銅の相互接続
線の酸化、拡散を妨げるように意図されている。適切な
不活性層の材料の一例は窒化シリコン(Si3N4)であ
る。After the copper layer has been polished and annealed, an inert layer is formed on the substrate. The passivation layer is intended to prevent oxidation and diffusion of the copper interconnect lines. An example of a suitable inert layer material is silicon nitride (Si 3 N 4).
【0019】[0019]
【実施例】本発明の実施例として、半導体素子に相互接
続チャネルと銅含有相互接続を形成する。一般に誘電体
層が基板上に堆積され、相互接続チャネルを形成するた
めにパターン付けされる。相互接続層はパターン付けさ
れた誘電体層上で相互接続チャネルの中に堆積される。
基板は研磨用スラリで研磨され、パターン付けされた誘
電体層の上の相互接続層の部分を除去し、相互接続線を
形成する。相互接続層の研磨の前後のどちらかで基板は
アニールされる。アニールの時間と温度は銅が所望の粒
のサイズを持つ銅含有相互接続層を供給できるように選
択される。相互接続層は銅層に加えて障壁層や種層を含
み得る。もし必要であれば拡散障壁層はもう一つの相互
接続レベルを形成する前に堆積される。不活性層は各々
の相互接続レベルの上に堆積される。DETAILED DESCRIPTION OF THE INVENTION As an embodiment of the present invention, an interconnect channel and a copper-containing interconnect are formed in a semiconductor device. Generally, a dielectric layer is deposited on the substrate and patterned to form an interconnect channel. An interconnect layer is deposited in the interconnect channel on the patterned dielectric layer.
The substrate is polished with a polishing slurry to remove portions of the interconnect layer above the patterned dielectric layer, forming interconnect lines. The substrate is annealed either before or after polishing of the interconnect layer. The time and temperature of the anneal are selected so that the copper can provide a copper-containing interconnect layer with the desired grain size. The interconnect layer may include a barrier layer and a seed layer in addition to the copper layer. If necessary, a diffusion barrier layer is deposited before forming another interconnect level. An inert layer is deposited over each interconnect level.
【0020】相互接続レベルはたいてい、そこに接触を
形成しながら誘電体材料層の上に形成される。相互接続
は少なくとも下層の誘電体層に形成された下層の金属の
特徴(窓をとおして)に電気的に接触される。本発明の
プロセスにおいて下層の金属の特徴もまた、銅の電気メ
ッキによって形成される。The interconnect level is usually formed on a layer of dielectric material, making contacts there. The interconnect is in electrical contact with at least an underlying metal feature (through a window) formed in the underlying dielectric layer. Underlying metal features in the process of the present invention are also formed by copper electroplating.
【0021】たくさんの材料が本発明に使われうる。一
般に誘電体層はシリコン窒化物、二酸化シリコン(ドー
プされた又はドープされない)、酸化シリコン窒素物、
フッ化ポリマー、ポリアリルエーテル、又はポリイミド
である。相互接続用金属は銅である。Many materials can be used in the present invention. Generally, the dielectric layer comprises silicon nitride, silicon dioxide (doped or undoped), silicon nitride,
It is a fluorinated polymer, polyallyl ether, or polyimide. The interconnect metal is copper.
【0022】銅は一般的な誘電体材料や特に二酸化シリ
コンに拡散する傾向にあるので拡散障壁として働く材料
の層が必要とされる。この層は基板に銅のメッキが成さ
れる前に障壁層を堆積するか、あるいは銅自身からの外
部拡散のいずれかによって形成することができる。もし
障壁層が材料の別個の層ならば、例は窒化シリコン、ホ
スホシリケートガラス(PSG)、酸化シリコン窒化
物、酸化アルミニウム(AlxOy)、タンタル、窒化チ
タニウム、ニオブ、またはモリブデンを含む。これらの
材料はCVD又は、PVDといった従来法によって堆積
される。Since copper tends to diffuse into common dielectric materials, and especially silicon dioxide, a layer of material that acts as a diffusion barrier is required. This layer can be formed either by depositing a barrier layer before the substrate is plated with copper, or by out-diffusion from the copper itself. If the barrier layer is a separate layer of material, examples include silicon nitride, phosphosilicate glass (PSG), silicon oxide nitride, aluminum oxide (Al x O y ), tantalum, titanium nitride, niobium, or molybdenum. These materials are deposited by conventional methods such as CVD or PVD.
【0023】本発明のプロセスはポリシリコンゲート、
ワードライン、ソース領域、ドレイン領域、ビットライ
ン、ベースエミッタ、コレクタなどを含む素子構造のた
めの銅による相互接続を作成するために使用される。当
業者にとって本発明が、例えばMOS(金属酸化物半導
体)素子(例えばNMOS,PMOS,CMOS,Bi
CMOS)、バイポーラ素子、複数チップモジュール、
III−V族半導体のようないずれかの半導体技術に使用
できることは明かであろう。The process of the present invention comprises a polysilicon gate,
Used to create copper interconnects for device structures including word lines, source regions, drain regions, bit lines, base emitters, collectors, etc. For those skilled in the art, the present invention is applicable to, for example, MOS (metal oxide semiconductor) devices (eg, NMOS, PMOS, CMOS, Bi).
CMOS), bipolar devices, multiple chip modules,
Obviously, it can be used in any semiconductor technology, such as III-V semiconductors.
【0024】図1は本発明の一つの実施例での流れ図を
示している。ステップ10において二酸化シリコン層が
シリコン基板(基板の最上層が、たいていそこに形成さ
れた下層の素子に接触した誘電体材料のパターン付けさ
れた層である)上に形成され、相互接続チャネルを形成
するためにパターン付けされる。示された実施例のステ
ップ11において銅の拡散障壁として働く層は基板上の
相互接続チャネルの中に堆積される。ステップ12にお
いて、続く銅の電気メッキの間に陰極として働く材料層
はパターン付けされた誘電体層のうえで相互接続チャネ
ルの中に形成される。FIG. 1 shows a flowchart in one embodiment of the present invention. In step 10, a silicon dioxide layer is formed on a silicon substrate (the top layer of the substrate is usually a patterned layer of dielectric material in contact with underlying devices formed thereon) to form interconnect channels. To be patterned. In step 11 of the illustrated embodiment, a layer serving as a copper diffusion barrier is deposited in the interconnect channel on the substrate. In step 12, a layer of material serving as a cathode during subsequent copper electroplating is formed in the interconnect channel over the patterned dielectric layer.
【0025】ステップ13において、銅はパターン付け
された誘電体層の上で相互接続チャネルの中に電気メッ
キされる。ステップ14において、基板は必要とされる
安定性を備えた大きい粒の構造を持つ銅を供給するため
にアニールされる。基板は化学的、機械的に研磨され
(15)、パターン付けされた二酸化シリコン層の表面
の銅の層の部分が除去される。本発明のプロセスにおい
て研磨とアニールのステップは互いに入れ替えて行うこ
とができる。シリコン窒化物の不活性層はステップ16
における各々の相互接続層の上に形成される。In step 13, copper is electroplated into the interconnect channel over the patterned dielectric layer. In step 14, the substrate is annealed to provide copper with a large grain structure with the required stability. The substrate is chemically and mechanically polished (15) to remove portions of the copper layer on the surface of the patterned silicon dioxide layer. In the process of the present invention, the steps of polishing and annealing can be performed interchangeably. Step 16: Deactivate Silicon Nitride
Formed on each interconnect layer.
【0026】例1ダマシーン溝が150nmのシリコン
基板上の0.5μmの厚みの二酸化シリコン層に形成さ
れた。二酸化シリコン層はPETEOS(プラズマエン
ハンステトラエチルオルトシリケート)から形成され
た。溝は8種類の幅とスペースの組合せを用いて形成さ
れた。溝の幅は0.3μmないし5μmの範囲にある。
これらの幅は回路の低い物からより高いレベルに見られ
る相互接続線の幅を示している。ダマシーン溝はグレー
ティングアレイとして用意された(例えば多くの等しい
幅の溝と一定の間隔のスペースがある)。サブミクロン
の溝の幅(0.3μm、0.5μm、0.8μm)に対
して、だいたい溝と等しい幅からほぼ3μmまでの範囲
のスペースを持ったグレーティングが近接効果を検査す
るために作製された。EXAMPLE 1 A damascene trench was formed in a 0.5 μm thick silicon dioxide layer on a 150 nm silicon substrate. The silicon dioxide layer was formed from PETEOS (plasma enhanced tetraethyl orthosilicate). The groove was formed using eight combinations of width and space. The width of the groove is in the range of 0.3 μm to 5 μm.
These widths indicate the width of the interconnect lines found at the lower levels of the circuit and at higher levels. The damascene grooves were prepared as a grating array (eg, with many equally-width grooves and regularly spaced spaces). For submicron groove widths (0.3 μm, 0.5 μm, 0.8 μm), gratings with spaces ranging from approximately the width of the groove to approximately 3 μm are fabricated to test proximity effects. Was.
【0027】溝の形成後、50nmの厚みのタンタル窒
化物の層がPVDによって酸化物の上に形成された。タ
ンタル窒化物は酸化物や付着層への銅の拡散に対する障
壁となる。100nmの厚みの銅層がタンタル窒化物層
の上に電気メッキの陰極として作用するように形成され
た。銅の膜もまたPVDによって形成された。PVD膜
は真空を破ることなしにカリフォルニア、サンジョゼの
ノーベラスからのM2iTMクラスタ堆積ツールのDCマ
グネトロンスパッタを用いてウェーハ上に形成された。
タンタル窒化物は3.1kWのパワー(バイアスなし)
で1:1のコリメータによって堆積された。堆積圧は
2.9Torrでアルゴンと窒素のフローレートは共に35
sccmであった。ウェーハの温度は150度であった。銅
は3.1kWのパワー(バイアスなし)で1:1コリメ
ータによって堆積された。堆積圧はPVD銅堆積の標準
でありフローレートは35sccmであった。ウェーハの温
度は50度であった。After formation of the trench, a 50 nm thick layer of tantalum nitride was formed over the oxide by PVD. Tantalum nitride provides a barrier to the diffusion of copper into the oxide and adhesion layers. A 100 nm thick copper layer was formed on the tantalum nitride layer to act as an electroplating cathode. Copper films were also formed by PVD. PVD films were formed on the wafers without breaking vacuum using DC magnetron sputtering of an M2i ™ cluster deposition tool from Novelas, San Jose, California.
3.1 kW power of tantalum nitride (no bias)
With a 1: 1 collimator. The deposition pressure is 2.9 Torr and the flow rates of argon and nitrogen are both 35.
sccm. The temperature of the wafer was 150 degrees. Copper was deposited by a 1: 1 collimator at a power of 3.1 kW (no bias). The deposition pressure was the standard for PVD copper deposition and the flow rate was 35 sccm. The temperature of the wafer was 50 degrees.
【0028】銅はモンタナのカリスペルのセミツールか
らのEquinoxTM噴水メッキシステムを用いて金属メッキ
された。ウェーハはエンソンから購入したCUBATH
(登録商標)SC電解漕の中に配置された。電解漕は銅
硫酸塩/硫酸メッキ化学装置を持っている。95msecの
オンと35msecのオフの周期で4.9アンペアの電流を
流すパルス波形が基板上に銅をメッキするために用いら
れた。銅はパターン付けされていない150nmの直径
のシリコンウェーハ上の1μmの膜と電量等量になるま
でメッキされた。メッキ時に銅の膜は約0.1ないし約
0.2μmの均一な細かい粒で高い反射率であるように
観察された。Copper was metal plated using the Equinox ™ fountain plating system from Kalispell Semitool, Montana. The wafer is CUBATH purchased from Enson
(Registered trademark) placed in a SC electrolyzer. The electrolyzer has a copper sulphate / sulphate plating chemistry. A pulse waveform of 4.9 amps with a 95 msec on and 35 msec off cycle was used to plate copper on the substrate. Copper was plated to an equivalence to a 1 μm film on an unpatterned 150 nm diameter silicon wafer. During plating, the copper film was observed to have high reflectivity with uniform fine grains of about 0.1 to about 0.2 μm.
【0029】銅メッキされた基板のいくつかは400度
で一時間、大気圧、形成ガス(N2/10%H2)下で筒
状炉のなかでアニールされた。アニールされた銅膜の粒
の大きさはアニールされていない銅膜の粒の大きさと比
較された。アニールされていない銅膜の粒の大きさは時
の経過と共に増加することが観察された。室温において
アニールされていない銅膜の粒の大きさは堆積時の平均
直径である0.1から0.2μmよりも増加した。数時
間から数週間の期間の後、アニールされていない膜の粒
の大きさは1μmよりも大きく増加することが確認され
た。粒の大きさの増加は均一には起こらなかった。粒の
大きさの増加は膜の孤立した点(核発生部位)から始ま
り、その部位の大きさと数は時間の経過と共に増加する
ことが観察された。長い時間を経て銅の粒の大きさに起
こるこのような変化は動的であり、制御されていないた
めに望まれてはいない。銅の膜は長い時間の間に大小の
粒の混合構造を持った。Some of the copper plated substrates were annealed in a cylindrical furnace at 400 ° C. for one hour under atmospheric pressure and forming gas (N 2 /10% H 2 ). The grain size of the annealed copper film was compared to the grain size of the unannealed copper film. It has been observed that the grain size of the unannealed copper film increases over time. The grain size of the copper film that had not been annealed at room temperature increased from 0.1 to 0.2 μm, the average diameter at the time of deposition. After a period of several hours to several weeks, it has been found that the grain size of the unannealed film increases to more than 1 μm. The increase in grain size did not occur uniformly. The increase in grain size began at an isolated point (nucleation site) in the membrane, and the size and number of that site was observed to increase over time. Such changes in copper grain size over time are dynamic and undesired because they are uncontrolled. The copper film had a mixed structure of large and small grains for a long time.
【0030】対照的にアニールされた銅は均一な大きい
粒の大きさの構造を持っている。大小の粒の混合は存在
していない。アニールされた(膜がCMPにさらされる
前後のどちらかで)銅の膜の粒の大きさが時の経過につ
れて増大するようには観察されなかった。In contrast, annealed copper has a uniform large grain size structure. There is no mixing of large and small grains. The grain size of the annealed copper film (either before or after the film was exposed to CMP) was not observed to increase with time.
【0031】堆積時の状態の銅の粒の大きさは基板に銅
を電気メッキするために使われる電気メッキ電解漕の組
成によって影響される。特に有機化合物を含む電解漕だ
けが堆積時に所望の粒の大きさ(約0.1μmないし約
0.2μm)を供給することが観察された。有機添加物
を用いない酸性の銅硫酸塩電気メッキ電解漕化学装置が
用いられると得られる電気メッキされた銅の堆積時の平
均的粒の大きさがあまりに大きく所望の充填度を作成で
きなかった。出願人は特定の理論に固執しているわけで
はないが、堆積時に所望の小さい粒の大きさを持つ電気
メッキされた銅の膜は、有機化合物(いずれかの配位
子、光沢剤、水準試薬)を含む銅の電解漕化学装置が使
われたときにのみ得られると出願人は信じている。The size of the copper grains as deposited is affected by the composition of the electroplating bath used to electroplate the copper on the substrate. In particular, it has been observed that only electrolytic baths containing organic compounds provide the desired grain size (about 0.1 μm to about 0.2 μm) during deposition. When an acidic copper sulfate electroplating electrolyzer with no organic additives is used, the average grain size during deposition of the resulting electroplated copper is too large to produce the desired degree of packing. . Applicants are not bound to any particular theory, but electroplated copper films with the desired small grain size upon deposition can be made of organic compounds (any ligand, brightener, level Applicant believes that it can only be obtained when a copper electrolyzer chemistry containing reagents is used.
【0032】[0032]
【発明の効果】本発明によれば、相互接続に銅のみを用
いて従来法に比べて機械的な強度及び電気的性質の向上
した半導体素子を製作することができる。According to the present invention, a semiconductor device having improved mechanical strength and electrical properties as compared with the conventional method can be manufactured by using only copper for interconnection.
【図1】本発明の一つの実施例についての流れ図であ
る。FIG. 1 is a flow chart for one embodiment of the present invention.
フロントページの続き (72)発明者 クリストフ リンク アメリカ合衆国 07922 ニュージャーシ ィ,バークリー ハイツ,スプリング リ ッヂ ドライヴ 200Continued on the front page (72) Inventor Christophe Link United States 07922 New Jersey, Berkeley Heights, Spring Ridge Drive 200
Claims (9)
ステップと、 前記誘電体材料の前記へこみを電気メッキされた銅で満
たすステップであって、電気メッキされた銅の粒の平均
的な大きさが約0.1μmないし約0.2μmであるス
テップと、 前記電気メッキされた銅の粒の平均的大きさが少なくと
も1方向で少なくとも1μmまで増大するような条件で
前記基板をアニールするステップとを含むプロセス。1. A process for manufacturing a device, comprising: forming a layer of a dielectric material on a substrate; forming at least one dent in the dielectric material layer; Filling the dents with electroplated copper, wherein the average size of the electroplated copper grains is from about 0.1 μm to about 0.2 μm; Annealing the substrate under conditions such that the average size of the grains increases in at least one direction to at least 1 μm.
記基板が約100度ないし約400度の温度範囲で約1
分ないし約1時間の間、アニールされるプロセス。2. The process according to claim 1, wherein the substrate has a temperature in a range from about 100 degrees to about 400 degrees.
A process that is annealed for between a minute and about an hour.
記銅が前記基板上に電気メッキされる前に前記へこみに
障壁層が形成されるプロセス。3. The process of claim 1, wherein a barrier layer is formed in the depression before the copper is electroplated on the substrate.
記銅層が基板上に電気メッキされる前に前記障壁層の上
に種層が形成されるプロセス。4. The process according to claim 3, wherein a seed layer is formed on the barrier layer before the copper layer is electroplated on a substrate.
記種層が前記へこみの上に形成されるプロセス。5. The process of claim 2, wherein said seed layer is formed over said indentation.
誘電体層の上に形成された前記電気メッキされた銅の部
分を除去し、前記へこみの中に前記電気メッキされた銅
だけを残すプロセス。6. The process of claim 1 wherein portions of said electroplated copper formed on said dielectric layer are removed, leaving only said electroplated copper in said recess. .
記へこみが長さ、幅及び高さを持つプロセス。7. The process according to claim 1, wherein said indentation has a length, a width and a height.
ニール後の前記粒の平均的な大きさが少なくとも前記へ
こみと同程度の幅で、へこみの長さ方向に少なくとも1
ミクロンであるプロセス。8. The process of claim 7, wherein the average size of the grains after annealing is at least as wide as the dents and at least one along the length of the dents.
A process that is micron.
と少なくとも一つの有機化合物を含む電解漕で前記銅が
電気メッキされるプロセス。9. The process of claim 1, wherein said copper is electroplated in an electrolytic bath containing copper and at least one organic compound.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/143,037 US6297154B1 (en) | 1998-08-28 | 1998-08-28 | Process for semiconductor device fabrication having copper interconnects |
US09/143037 | 1998-08-28 |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2000077527A true JP2000077527A (en) | 2000-03-14 |
Family
ID=22502333
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11239079A Pending JP2000077527A (en) | 1998-08-28 | 1999-08-26 | Manufacturing process for semiconductor element provided with mutual connection of copper |
Country Status (5)
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---|---|
US (1) | US6297154B1 (en) |
EP (1) | EP0982771B1 (en) |
JP (1) | JP2000077527A (en) |
KR (1) | KR100711526B1 (en) |
DE (1) | DE69901142T2 (en) |
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- 1999-08-17 EP EP99306470A patent/EP0982771B1/en not_active Expired - Lifetime
- 1999-08-25 KR KR1019990035378A patent/KR100711526B1/en not_active IP Right Cessation
- 1999-08-26 JP JP11239079A patent/JP2000077527A/en active Pending
Also Published As
Publication number | Publication date |
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KR20000017528A (en) | 2000-03-25 |
US6297154B1 (en) | 2001-10-02 |
EP0982771B1 (en) | 2002-04-03 |
KR100711526B1 (en) | 2007-04-26 |
DE69901142T2 (en) | 2002-11-07 |
EP0982771A1 (en) | 2000-03-01 |
DE69901142D1 (en) | 2002-05-08 |
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