JP2000049280A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JP2000049280A JP2000049280A JP21704898A JP21704898A JP2000049280A JP 2000049280 A JP2000049280 A JP 2000049280A JP 21704898 A JP21704898 A JP 21704898A JP 21704898 A JP21704898 A JP 21704898A JP 2000049280 A JP2000049280 A JP 2000049280A
- Authority
- JP
- Japan
- Prior art keywords
- conductor
- electrode
- semiconductor device
- wiring board
- semiconductor switching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L24/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
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- H01L2224/37001—Core members of the connector
- H01L2224/37099—Material
- H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/37138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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- H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
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- H01L2224/45124—Aluminium (Al) as principal constituent
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Abstract
Description
【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION
【０００１】[0001]
【発明の属する技術分野】本発明は、スイッチング素子
を有する半導体装置で、特にパワーエレクトロニクスの
分野で使用されるサイリスタやパワートランジスタなど
の実装構造で、配線インダクタンスが低く、かつ、熱応
力を小さくした接合部を有する半導体装置とその製造方
法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a switching element, and more particularly to a mounting structure of a thyristor or a power transistor used in the field of power electronics, which has a low wiring inductance and a small thermal stress. The present invention relates to a semiconductor device having a junction and a method for manufacturing the same.
【０００２】[0002]
【従来の技術】近年、産業用ポンプやファン等のパワー
エレクトロニクスの制御分野では、エネルギーの有効利
用の観点からインバータ装置が注目されている。インバ
ータ装置の心臓部は電流をスイツチングする半導体素子
である。2. Description of the Related Art In recent years, in the field of control of power electronics such as industrial pumps and fans, inverter devices have attracted attention from the viewpoint of effective use of energy. The heart of the inverter device is a semiconductor element for switching a current.
【０００３】半導体スィッチング素子としては従来から
サイリスタ、パワー・トランジスタなどが知られてお
り、最近ではＧＴＯ（ゲート・ターン・オフ・サイリス
タ）やＩＧＢＴ（インシユレーテツド・ゲート・バイポ
ーラ・トランジスタ）などが広く使用されている。As a semiconductor switching element, a thyristor, a power transistor and the like have been conventionally known, and recently, a GTO (gate turn-off thyristor), an IGBT (insulated gate bipolar transistor) and the like have been known. Widely used.
【０００４】半導体スイッチング素子は種類により呼び
方は異なるものの、いずれも正極（エミッタ）電極、負
極（コレクタ）電極と制御極（ゲート）電極の３端子で
構成され、制御極への電圧、電流を制御することにより
正極と負極間の導通の制御を行なつている。これらの素
子をパッケージ内に実装する場合には、正極、負極には
大電流が通電されるため配線の電流容量を考慮すると共
に、スイッチングにより著しく発熱するため放熱構造に
留意した構造が採用されている。Although the semiconductor switching element is called differently depending on the type, each of the semiconductor switching elements has three terminals of a positive electrode (emitter) electrode, a negative electrode (collector) electrode and a control electrode (gate) electrode. By controlling, conduction between the positive electrode and the negative electrode is controlled. When these elements are mounted in a package, a large current is applied to the positive electrode and the negative electrode, so that the current capacity of the wiring is taken into consideration, and a structure that pays attention to the heat dissipation structure is adopted because the switching generates significant heat. I have.
【０００５】図５は、従来のバッケ一ジ内部での実装例
を示す断面図である。半導体スイツチング素子の一種で
あるＩＧＢＴ１０１は、裏面に設けられたコレクタ電極
１０５がＤＢＣ基板（銅張りセラミツク基板）１０２の
表面銅パターン１０３に半田１０４により接合されてい
る。ＩＧＢＴ１０１の表面にはエミッタ電極１１０が設
けられており、ＤＢＧ基板１０２の表面銅パターン１０
６にアルミニウム線を用いたワイヤボンディング１０７
により複数のワイヤで接続されている。FIG. 5 is a sectional view showing an example of mounting inside a conventional bucket. In an IGBT 101 which is a kind of semiconductor switching element, a collector electrode 105 provided on a back surface is joined to a surface copper pattern 103 of a DBC substrate (copper clad ceramic substrate) 102 by solder 104. An emitter electrode 110 is provided on the surface of the IGBT 101, and the surface copper pattern 10 of the DBG substrate 102 is provided.
6. Wire bonding 107 using aluminum wire
Are connected by a plurality of wires.
【０００６】また、ＩＧＢＴ１０１の表面にはゲート電
極１０８が設けられて、ＤＢＣ基板１０２の表面銅パタ
ーン１０９にアルミニウム線を用いたワイヤボンディン
グ１１０により接続されている。ゲート電極は大電流を
流す必要がないため、通常１本のワイヤで構成されてい
る。A gate electrode 108 is provided on the surface of the IGBT 101, and is connected to a surface copper pattern 109 of the DBC substrate 102 by wire bonding 110 using an aluminum wire. Since the gate electrode does not need to flow a large current, it is usually composed of one wire.
【０００７】また、ＤＢＣ基板１０２の裏面銅パターン
１１１はヒートシンク１１２と半田１１３により接合さ
れており、ＩＧＢＴ１０１で発生した熱は、半田１０
４、表面銅パターン１０３、セラミック層１１４、裏面
銅パターン１１１、半田１１３を経てヒートシンク１１
２に達し外部に放熱される。[0007] The backside copper pattern 111 of the DBC substrate 102 is joined to a heat sink 112 by solder 113, and the heat generated by the IGBT 101 is
4. Heat sink 11 through front surface copper pattern 103, ceramic layer 114, rear surface copper pattern 111, and solder 113
2 and heat is radiated outside.
【０００８】また、ここでは図示しないが、ヒートシン
クの周囲にはプラスチック製の外囲器が設けられてお
り、ＩＧＢＴ１０１やＤＢＣ基板１０２の表面は絶縁の
ためのシリコンゲル等で封止されている。Although not shown here, a plastic envelope is provided around the heat sink, and the surfaces of the IGBT 101 and the DBC substrate 102 are sealed with silicon gel or the like for insulation.
【０００９】なお、半導体スイッチング素子としてＧＴ
Ｏを使用したの場合も、エミッタ電極をアノード電極、
コレクタ電極をカソード電極と読み替えることで、実装
構造は同様である。Note that GT is used as a semiconductor switching element.
Also when O is used, the emitter electrode is used as the anode electrode,
By replacing the collector electrode with the cathode electrode, the mounting structure is the same.
【００１０】図６は、配線に銅製の平板を用いて、接合
部を半田で接合したパッケージ内部の実装例を示す断面
図である。FIG. 6 is a cross-sectional view showing an example of mounting inside a package in which a joint portion is joined by soldering using a copper flat plate for wiring.
【００１１】半導体スィッチング素子の一種であるＩＧ
ＢＴ１５１は、裏面に設けられたコレクタ電極１５０が
ＤＢＣ基板１５２の表面銅パターン１５３に半田１５４
により接合されている。ＩＧＢＴ１５１の表面にはエミ
ッタ電極１５５が設けられており、ＤＢＣ基板１５２の
表面銅パターン１５６と平板状の導体１５７により接続
されている。IG which is a kind of semiconductor switching element
The BT 151 has a collector electrode 150 provided on the back surface and a solder 154 attached to the surface copper pattern 153 of the DBC substrate 152.
It is joined by. An emitter electrode 155 is provided on the surface of the IGBT 151, and is connected to a surface copper pattern 156 of the DBC substrate 152 by a flat conductor 157.
【００１２】また、ＩＧＢＴ１５１の表面にはゲート電
極１５８が設けられており、ＤＢＣ基板１５２の表面銅
パターン１５３（紙面に垂直方向にあるため図示せず）
に、同様に平板状の導体１５９（紙面に垂直方向に延
長）により接続されている。ゲート電極は大電流を流す
必要がないため、通常は細い導体１本で構成されてい
る。A gate electrode 158 is provided on the surface of the IGBT 151, and a surface copper pattern 153 of the DBC substrate 152 (not shown because it is perpendicular to the plane of the drawing).
Are similarly connected by a flat conductor 159 (extending in a direction perpendicular to the paper surface). Since a large current does not need to flow through the gate electrode, it is usually composed of one thin conductor.
【００１３】また、ＤＢＣ基板１５２の裏面銅パターン
１６１はヒートシンク１６２と半田１６３により接合さ
れており、ＩＧＢＴ１５１で発生した熱は、半田１５
４、表面銅パターン１５３、セラミック層１６４、裏面
銅パターン１６１、半田１６３を経てヒートシンク１６
２に達し、外部に放熱される。The backside copper pattern 161 of the DBC substrate 152 is joined to a heat sink 162 by solder 163, and the heat generated by the IGBT 151
4, the heat sink 16 through the front surface copper pattern 153, the ceramic layer 164, the rear surface copper pattern 161, and the solder 163.
2 and heat is radiated to the outside.
【００１４】また、ここでは図示しないが、ヒートシン
ク１６２の周囲にはプラスチック製の外囲器があり、Ｉ
ＧＢＴ１６１やＤＢＣ基板１５２の表面は絶縁のための
シリコンゲル等で封止されている。Although not shown here, a plastic envelope is provided around the heat sink 162.
The surfaces of the GBT 161 and the DBC substrate 152 are sealed with silicon gel or the like for insulation.
【００１５】なお半導体スイッチング素子としてＧＴ０
を使用したの場合も、エミッタ電極をアノード電極、コ
レクタ電極をカソード電極と読み替えることで、実装構
造は同様である。GT0 is used as a semiconductor switching element.
Is used, the mounting structure is the same by replacing the emitter electrode with the anode electrode and the collector electrode with the cathode electrode.
【００１６】[0016]
【発明が解決しようとする課題】以上述べた様に、図５
で示した技術では、特に高負荷下で使用した場合、エミ
ッタ電極のワイヤボンディング部が熱応力による疲労に
より破壊することが挙げられる。As described above, FIG.
In the technique described in (1), particularly when used under a high load, the wire bonding portion of the emitter electrode may be broken by fatigue due to thermal stress.
【００１７】その対策として、エミッタ電極についても
コレクタ電極と同様に半田接合とする方法が試みられて
いる。しかしながら、この方法では平板または棒状の電
極によりコレクタ電極を構成しているが、接続プロセス
を一元化するためゲート電極を同様の構造で構成する
と、配線同士が相互に干渉する場合が生じたり、配線の
引き回しによっては電極の製作が困難となる欠点が生じ
ていた。As a countermeasure, a method of soldering the emitter electrode similarly to the collector electrode has been attempted. However, in this method, the collector electrode is formed by a flat or rod-shaped electrode. However, if the gate electrode is formed to have the same structure in order to unify the connection process, the wirings may interfere with each other, or the wiring may not be formed. Some drawbacks have made it difficult to manufacture electrodes.
【００１８】また、図６に示した技術では、 平板また
は棒状の電極によりコレクタ電極を構成するが、電極の
剛性が高いと、素子発熱時の熱応力が大きくなり、これ
による疲労で素子や接合部などが破壊する欠点があっ
た。In the technique shown in FIG. 6, the collector electrode is constituted by a flat or rod-shaped electrode. However, if the electrode has a high rigidity, the thermal stress at the time of heat generation of the element increases, and the element and the junction are fatigued due to the fatigue. There was a drawback that the part was destroyed.
【００１９】本発明は、素子発熱時の熱応力で素子や接
合部などが破壊することのない実装がなされたさ半導体
装置とその製造方法を提供するものである。An object of the present invention is to provide a semiconductor device and a method of manufacturing the semiconductor device, which are mounted without destruction of an element or a joint due to a thermal stress when the element is heated.
【００２０】[0020]
【課題を解決するための手段】請求項１の発明による手
段によれば、一表面に正極電極と制御電極とが形成され
他表面に負極電極が形成された半導体スイッチング素子
と、金属導体が設けられ且つ前記半導体スイッチング素
子が実装される配線基板とを具備し、この配線基板の、
金属導体と前記正極電極及び制御電極及び負極電極の少
なくとも一つに対する電気的接続は、細導線を編み上げ
た導体により行われていることを特徴とする半導体装置
にある。According to the first aspect of the present invention, there is provided a semiconductor switching element having a positive electrode and a control electrode formed on one surface and a negative electrode formed on the other surface, and a metal conductor. And a wiring board on which the semiconductor switching element is mounted.
The semiconductor device is characterized in that the electrical connection to the metal conductor and at least one of the positive electrode, the control electrode and the negative electrode is made by a conductor in which fine conductive wires are woven.
【００２１】請求項２の発明による手段によれば、前記
配線基板の金属導体と、前記細導線を編み上げた導体と
は半田接合により接合されていることを特徴とする請求
項１記載の半導体装置にある。According to a second aspect of the present invention, in the semiconductor device according to the first aspect of the present invention, the metal conductor of the wiring board and the conductor formed by knitting the fine conductive wires are joined by soldering. It is in.
【００２２】請求項３の発明による手段によれば、前記
細導線を編み上げた導体と接続されている前記正極電極
及び前記制御電極及び前記負極電極の少なくとも一つは
半田接合により接合されていることを特徴とする請求項
１記載の半導体装置にある。According to the third aspect of the present invention, at least one of the positive electrode, the control electrode, and the negative electrode connected to the conductor in which the fine conductive wire is woven is joined by soldering. 2. The semiconductor device according to claim 1, wherein:
【００２３】請求項４の発明による手段によれば、前記
半導体スイツチング素子がＩＧＢＴ素子又はＩＥＧＴ素
子であることを特徴とする請求項１記載の半導体装置に
ある。According to the fourth aspect of the present invention, there is provided the semiconductor device according to the first aspect, wherein the semiconductor switching element is an IGBT element or an IEGT element.
【００２４】請求項５の発明による手段によれば、前記
配線基板がセラミック基板上に金属導体を形成したもの
であることを特徴とする請求項１記載の半導体装置にあ
る。According to a fifth aspect of the present invention, there is provided the semiconductor device according to the first aspect, wherein the wiring substrate is formed by forming a metal conductor on a ceramic substrate.
【００２５】請求項６の発明による手段によれば、前記
配線基板は金属べース上に絶縁層を形成し、さらにその
上に金属導体を形成したものであることを特徴とする請
求項１記載の半導体装置にある。According to a sixth aspect of the present invention, the wiring board is formed by forming an insulating layer on a metal base and further forming a metal conductor thereon. In the described semiconductor device.
【００２６】請求項７の発明による手段によれば、前記
細導線は銅製の線材を平帯状に編み上げたものであるこ
とを特徴とする請求項１記載の半導体装置にある。According to a seventh aspect of the present invention, there is provided the semiconductor device according to the first aspect, wherein the fine conductive wire is formed by braiding a copper wire into a flat band shape.
【００２７】請求項８の発明による手段によれば、前記
細導線を平帯状に編み上げた導体の長手方向の弾性率が
１ＧＰａ以下であることを特徴とする請求項７記載の半
導体装置にある。According to the means of the invention of claim 8, there is provided the semiconductor device according to claim 7, wherein the elastic modulus in the longitudinal direction of the conductor in which the fine conductive wire is woven in a flat band shape is 1 GPa or less.
【００２８】請求項９の発明による手段によれば、前記
半導体スイッチング素子が複数個前記配線基板上設けら
れた際に、各半導体スイッチング素子間の配線の一部と
して細導線を編み上げた導体を使用したことを特徴とす
る半導体装置にある。According to the ninth aspect of the present invention, when a plurality of the semiconductor switching elements are provided on the wiring board, a conductor in which a fine conductive wire is woven is used as a part of a wiring between the semiconductor switching elements. A semiconductor device is characterized in that:
【００２９】請求項１０の発明による手段によれば、一
表面に正極電極と制御電極とが形成され且つ他裏面に負
極電極が形成された半導体スイッチング素子と、金属導
体が設けられ且つ前記半導体スイッチ素子が実装される
配線基板とを具備する半導体装置の製造方法において、
前記正極電極と前記制御電極とを前記配線基板の金属導
体に対して半田接合するか、又は、前記負極電極を前記
配線基板の金属導体に対して半田接合する第１の半田接
合工程と、前記正極電極及び前記制御電極及び前記負極
電極の少なくとも一つを一端が前記配線基板の金属導体
に電気的に接続される細導線を編み上げた導体の他端に
半田接合する第２の半田接合工程とを有することを特徴
とする半導体装置の製造方法にある。According to the tenth aspect of the present invention, there is provided a semiconductor switching element in which a positive electrode and a control electrode are formed on one surface and a negative electrode is formed on the other surface, A method of manufacturing a semiconductor device comprising: a wiring board on which an element is mounted;
A first soldering step of soldering the positive electrode and the control electrode to a metal conductor of the wiring board, or a soldering step of soldering the negative electrode to a metal conductor of the wiring board; A second soldering step of soldering at least one of the positive electrode, the control electrode, and the negative electrode to the other end of a conductor formed by braiding a thin conductive wire having one end electrically connected to the metal conductor of the wiring board; A method for manufacturing a semiconductor device, comprising:
【００３０】[0030]
【発明の実施の形態】図１は本発明にかかる半導体装置
の第１の実施の形態を示したものである。半導体スイッ
チング素子の一種であるＩＧＢＴ１は、裏面に設けられ
たコレクタ電極５がＤＢＣ基板２の表面銅パターン３に
半田６により接合されている。ＩＧＢＴ１の表面にはエ
ミッタ電極４が設けられており、ＤＢＣ基板２の表面銅
パターン３と銅製の細導線を平帯状に編み上げた導体７
により接続されている。この導体の長手方向の弾性率
は、１ＧＰａ以下が好ましい。またＩＧＢＴ１の表面に
はゲート電極８が設けられており、ＤＢＣ基板２の表面
銅パターン（紙面に垂直方向にあるため図示せず）に同
様に平板状の導体９（紙面に垂直方向に延長）により接
続されている。FIG. 1 shows a first embodiment of a semiconductor device according to the present invention. In an IGBT 1 which is a kind of semiconductor switching element, a collector electrode 5 provided on a back surface is joined to a surface copper pattern 3 of a DBC substrate 2 by solder 6. An emitter electrode 4 is provided on the surface of the IGBT 1, and a copper pattern 3 on the surface of the DBC substrate 2 and a conductor 7 formed by braiding a thin copper wire into a flat band shape.
Connected by The elastic modulus in the longitudinal direction of this conductor is preferably 1 GPa or less. Further, a gate electrode 8 is provided on the surface of the IGBT 1, and similarly to the copper pattern on the surface of the DBC substrate 2 (not shown because it is perpendicular to the plane of the drawing), a flat conductor 9 (extending in the direction perpendicular to the plane of drawing) Connected by
【００３１】ゲート電極８は大電流を流す必要がないた
め、通常細い導体１本で構成されている。なお、ＩＧＢ
Ｔ１の表面および裏面の各電極４、５、８、は、半田接
合が可能なようにメタライズされている。メタライズの
方法は特定されるものではなく、アルミニウム電極上に
チタン・白金・金やチタン・パラジウム・金などの方法
で表面に金属層を設ける方法やニッケル等で被覆する方
法等を用いる。Since there is no need to flow a large current, the gate electrode 8 is usually composed of one thin conductor. In addition, IGB
The electrodes 4, 5, and 8 on the front surface and the back surface of T1 are metallized so that solder bonding can be performed. The method of metallizing is not specified, and a method of providing a metal layer on the surface of the aluminum electrode using a method such as titanium, platinum, gold or titanium, palladium, gold, or a method of coating with a nickel or the like is used.
【００３２】また、ＤＢＣ基板２の裏面銅パターン１１
はヒートシンク１２に半田１３を介して接合されてお
り、ＩＧＢＴ１で発生した熱は、半田６、表面銅パター
ン３、セラミック層１４、裏面銅パターン１１、半田１
３を経てヒートシンク１２に達し、外部に放熱される。The backside copper pattern 11 of the DBC substrate 2
Is bonded to a heat sink 12 via a solder 13, and heat generated by the IGBT 1 is applied to the solder 6, the front copper pattern 3, the ceramic layer 14, the back copper pattern 11, and the solder 1.
3, the heat reaches the heat sink 12 and is radiated to the outside.
【００３３】また、ここでは図示しないが、ヒートシン
ク１２の周囲にはプラスチツク製の外囲器があり、ＩＧ
ＢＴ１やＤＢＣ基板２の表面は絶縁のためのシリコンゲ
ル等で封止されている。なお半導体スイッチング素子と
してＧＴ０を使用したの場合も、エミッタ電極５をアノ
ード電極、コレクタ電極１０をカソード電極と読み替え
ることで、実装構造は同様である。Although not shown here, there is a plastic envelope around the heat sink 12, and an IG
The surface of the BT1 or DBC substrate 2 is sealed with silicon gel or the like for insulation. In the case where GT0 is used as the semiconductor switching element, the mounting structure is the same by replacing the emitter electrode 5 with the anode electrode and the collector electrode 10 with the cathode electrode.
【００３４】本発明によれば、エミッタ電極４と配線基
板２間に形成された配線を銅製の細導線を平帯状に編み
上げた導体７とすることにより、素子の発熱によりエミ
ッタ電極４とＤＢＣ基板２の間が変位して熱応力による
疲労が発生する状態となっても、配線部分の剛性を小さ
くすることにより、熱応力発生を大幅に軽減することが
出来る。According to the present invention, the wiring formed between the emitter electrode 4 and the wiring substrate 2 is made of a conductor 7 formed by braiding a copper thin conductive wire into a flat band, so that the emitter electrode 4 and the DBC substrate are generated by the heat generated by the element. Even when the gap between the two is displaced and fatigue occurs due to thermal stress, the generation of thermal stress can be greatly reduced by reducing the rigidity of the wiring portion.
【００３５】従って、半導体素子との半田接合の破壊を
免れることができ、さらに長寿命化を図ることが可能と
なる。Accordingly, it is possible to avoid the destruction of the solder joint with the semiconductor element, and it is possible to further extend the life.
【００３６】なお、細導線を編み上げた導体の材質や形
状は、これを限定するものではないが、電気伝導性の点
からは銅線であることが好ましく、またパッケージ形状
を薄型とする観点からは、平帯状に形成されたいわゆる
平網線とすることが好ましい。The material and shape of the conductor formed by knitting the fine conductor are not limited, but are preferably copper wires from the viewpoint of electrical conductivity, and from the viewpoint of reducing the thickness of the package. Is preferably a so-called flat mesh wire formed in a flat band shape.
【００３７】平網線はその素線径と数により各種ある
が、ここでは応力緩和を目的とするため、長手方向の弾
性率が１ＧＰａ以下とすることが特に好ましい。また編
線の端子部分はそのままであつても、薄板等でばらけ防
止のため端子処理したものでも良い。Although there are various types of flat wire depending on the diameter and number of the wires, it is particularly preferable that the elastic modulus in the longitudinal direction is 1 GPa or less for the purpose of relaxing stress. Further, the terminal portion of the braided wire may be used as it is, or may be a thin plate or the like which has been subjected to terminal treatment in order to prevent dispersion.
【００３８】配線基板は、半導体素子で発生する熱を放
熱するため、放熱性に優れた基板が好ましい。このため
アルミニウム・インバー・鉄などの金属べース上にエボ
キシ・ポリブタジエン・ポリイミドなどの絶縁層を形成
し、その上に銅箔などで配線パターンを形成したいわゆ
るメタルコア基板や、アルミニウム・窒化アルミニウム
などのセラミック材料を基材として、表面に銅・アルミ
ニウムなどの金属による配線を形成した基板が好適で、
中でも絶縁耐圧が要求される分野では、アルミニウム・
窒化アルミニウムなどに銅箔を直接貼り付けたいわゆる
ＤＢＣ基板（銅張りセラミック基板）等が好適である。The wiring board is preferably a board excellent in heat dissipation, in order to radiate heat generated in the semiconductor element. For this reason, a so-called metal core substrate in which an insulating layer such as ethoxy, polybutadiene, polyimide, etc. is formed on a metal base such as aluminum, invar, iron, etc., and a wiring pattern is formed with copper foil, etc., or aluminum, aluminum nitride, etc. A substrate having a wiring formed of a metal such as copper or aluminum on the surface thereof is preferable, using a ceramic material as a base material,
In fields where dielectric strength is required, aluminum
A so-called DBC substrate (copper-clad ceramic substrate) in which a copper foil is directly attached to aluminum nitride or the like is suitable.
【００３９】また、半田接合の材料としては各種の半田
材料をし使用することが可能であるが、本発明の半田接
合部は、高い熱ストレスに晒されることから、耐ストレ
ス性を有する半田材料が好適である。また複数の半田接
合部が存在する場合には、これらを順次、単独に半田付
けしても、また複数の部位を一括して半田付けしても良
く、前者においては順位に応じて融点を順次低くしてい
かなければならないことは当然である。Various solder materials can be used as the material for the solder joint. However, since the solder joint of the present invention is exposed to high thermal stress, a solder material having stress resistance can be used. Is preferred. When there are a plurality of solder joints, these may be soldered individually and sequentially, or a plurality of portions may be soldered collectively. In the former, the melting points are sequentially determined according to the order. It is natural that we have to keep it low.
【００４０】次にこれらの構造の製造方法について説明
すると、図示しない実装装置であるダイマウンターの所
定位置に銅張りセラミック基板２をセットし、ＩＧＢＴ
１を保持したヘッドが所定位置に降下してコレクタ電極
１０を銅張りセラミック基板２の所定位置にダイマウン
ティングを行う。このダイマウンティングは窒素雰囲気
中でフラックスレス半田を用いてスクラブマウントを行
う。半田はシート半田でも滴下による半田供給でもよ
い。Next, a method of manufacturing these structures will be described. A copper-clad ceramic substrate 2 is set at a predetermined position of a die mounter, which is a mounting device (not shown), and an IGBT is mounted.
The head holding 1 is lowered to a predetermined position, and the collector electrode 10 is die-mounted at a predetermined position on the copper-clad ceramic substrate 2. In this die mounting, scrub mounting is performed using fluxless solder in a nitrogen atmosphere. The solder may be sheet solder or solder supplied by dropping.
【００４１】次の工程でＩＧＢＴ１のエミッタ電極４と
ゲート電極８をそれぞれ銅製の平織線である導体７、９
と半田接合する。その後、ヒートシンク１２を銅張りセ
ラミック基板２の裏面に半田接合する。これらの半田接
合はそれぞれ仮付けしておきリフロー炉で同時に半田付
けを行う。In the next step, the emitter electrode 4 and the gate electrode 8 of the IGBT 1 are connected to conductors 7 and 9 which are copper plain weave wires, respectively.
And soldering. Thereafter, the heat sink 12 is soldered to the back surface of the copper-clad ceramic substrate 2. These solder joints are temporarily attached, and are simultaneously soldered in a reflow furnace.
【００４２】なお、これらの半田付はリフロー炉で同時
に行わず順次それぞれの個所を行ってもよい。The soldering may be carried out in each place sequentially without performing the soldering simultaneously in the reflow furnace.
【００４３】図２は本発明にかかる半導体装置の第２の
実施の形態を示したものである。第１のＩＥＧＴ２１と
第２のＩＥＧＴ２２は、いづれも半導体スイツチング素
子の一種である。第１のＩＥＧＴ２１の表面に設けられ
たエミッタ電極２３はＤＢＣ基板２４の表面銅パターン
２５と細導線を編み上げた第１の導体２６により接続さ
れている。FIG. 2 shows a second embodiment of the semiconductor device according to the present invention. Each of the first IEGT 21 and the second IEGT 22 is a kind of semiconductor switching element. The emitter electrode 23 provided on the surface of the first IEGT 21 is connected to the surface copper pattern 25 of the DBC substrate 24 by a first conductor 26 formed by knitting fine conductive wires.
【００４４】第２のＩＥＧＴ２２の表面エミッタ電極２
７は、銅製の細導線を平帯状に編み上げた第２の導体２
８により、引き出し端子２９と接続されている。また第
１のＩＥＧＴ２１と第２のＩＥＧＴ２２の表面にはそれ
ぞれゲート電極３０、３１が設けられており、ＤＢＣ基
板２４の表面銅パターン（紙面に垂直方向にあるため図
示せず）に平帯状の導体３２と３３（紙面に垂直方向に
延長）により接続されている。また、また第１のＩＥＧ
Ｔ２１と第２のＩＥＧＴ２２の裏面にはそれぞれコレク
タ電極４３、４４が設けられていて、それぞれＤＢＣ基
板２４の表面銅パターン２５、３９に半田接続されてい
る。Surface emitter electrode 2 of second IEGT 22
7 is a second conductor 2 formed by braiding a copper thin conductive wire into a flat band shape.
8 connects to the extraction terminal 29. Gate electrodes 30 and 31 are provided on the surfaces of the first IEGT 21 and the second IEGT 22, respectively, and a flat strip-shaped conductor is formed on the surface copper pattern of the DBC substrate 24 (not shown because it is perpendicular to the plane of the paper). 32 and 33 (extended in the direction perpendicular to the paper). Also, the first IEG
Collector electrodes 43 and 44 are provided on the back surfaces of T21 and the second IEGT 22, respectively, and are connected by soldering to the surface copper patterns 25 and 39 of the DBC substrate 24, respectively.
【００４５】ゲート電極３０、３１は大電流を流す必要
がないため、通常細い導体１本で構成されている。また
ＤＢＣ基板２４の裏面銅パターン３４はヒートシンク３
５と半田３６により接合されており、ＩＥＧＴ２１で発
生した熱は、半田３７、３８、表面銅パターン２５と銅
パターン３９、セラミック層４０、裏面銅パターン３
４、半田３６を経てヒートシンク３５に達して外部に放
熱される。The gate electrodes 30 and 31 do not need to flow a large current, and are therefore usually composed of one thin conductor. The backside copper pattern 34 of the DBC substrate 24 is
5 and the solder 36, and heat generated by the IEGT 21 is applied to the solders 37 and 38, the surface copper pattern 25 and the copper pattern 39, the ceramic layer 40, and the back copper pattern 3.
4. The heat reaches the heat sink 35 via the solder 36 and is radiated to the outside.
【００４６】また、ここでは図示しないが、ヒートシン
ク３５の周囲にはプラスチック製の外囲器があり、ＩＥ
ＧＴ２１やＤＢＣ基板２４の表面は絶縁のためのシリコ
ンゲル等で封止されている。Although not shown here, there is a plastic envelope around the heat sink 35, and the IE
The surfaces of the GT 21 and the DBC substrate 24 are sealed with silicon gel or the like for insulation.
【００４７】なお、半導体スイッチング素子としてＧＴ
０を使用したの場合も、エミッタ電極を正極（アノー
ド）電極、コレクタ電極を負極（カソード）電極と読み
替えることで、実装構造は同様である。Note that GT is used as a semiconductor switching element.
Even when 0 is used, the mounting structure is the same by replacing the emitter electrode with a positive electrode (anode) electrode and the collector electrode with a negative electrode (cathode) electrode.
【００４８】次にこれらの構造の製造方法について説明
すると、図示しない実装装置であるダイマウンターの所
定位置に銅張りセラミック基板２４をセットし、第１の
ＩＧＢＴ２１を保持したヘッドが所定位置に降下してコ
レクタ電極４３を銅張りセラミック基板２４にダイマウ
ンティングを行う。続いて同様に、第２のＩＧＢＴ２２
を保持したヘッドが所定位置に降下してコレクタ電極４
４を銅張りセラミック基板２４の所定位置にダイマウン
ティングを行う。このダイマウンティングは窒素・水素
混合雰囲気中でフラックスレス半田を用いてスクラブマ
ウントを行う。半田はシート半田でも滴下による半田供
給でもよい。Next, a method of manufacturing these structures will be described. The copper-clad ceramic substrate 24 is set at a predetermined position of a die mounter, which is a mounting device (not shown), and the head holding the first IGBT 21 is lowered to the predetermined position. The collector electrode 43 is die-mounted on the copper-clad ceramic substrate 24. Subsequently, similarly, the second IGBT 22
Is lowered to a predetermined position and the collector electrode 4
4 is die-mounted at a predetermined position on the copper-clad ceramic substrate 24. In this die mounting, scrub mounting is performed using fluxless solder in a nitrogen / hydrogen mixed atmosphere. The solder may be sheet solder or solder supplied by dropping.
【００４９】次の工程でＩＧＢＴ２１のエミッタ電極２
３とゲート電極３０をそれぞれ銅製の平織線である導体
２６、３２と半田接合する。続いて同様に、ＩＧＢＴ２
２のエミッタ電極２７とゲート電極３１をそれぞれ銅製
の平織線である導体２８、３３と半田接合する。さら
に、導体２８、３３の他端部を基板２４上の所定の導体
に半田接続する。その後、ヒートシンク３５を銅張りセ
ラミック基板２４の裏面に半田接合する。これらの半田
接合はそれぞれ仮付けしておきリフロー炉で同時に半田
付けを行う。In the next step, the emitter electrode 2 of the IGBT 21 is
3 and the gate electrode 30 are respectively soldered to the conductors 26 and 32 which are copper plain woven wires. Then, in the same manner, IGBT2
The two emitter electrodes 27 and the gate electrode 31 are soldered to conductors 28 and 33, which are copper plain woven wires, respectively. Further, the other ends of the conductors 28 and 33 are soldered to predetermined conductors on the substrate 24. Thereafter, the heat sink 35 is soldered to the back surface of the copper-clad ceramic substrate 24. These solder joints are temporarily attached, and are simultaneously soldered in a reflow furnace.
【００５０】なお、これらの半田付けはリフロー炉で同
時に行わず順次それぞれの個所を行ってもよい。It is to be noted that these soldering operations may be performed sequentially at respective locations instead of simultaneously in a reflow furnace.
【００５１】この第２の実施の形態によれば、半導体ス
イッチング素子の発熱による熱応力は配線部分の剛性を
小さくすることにより、応力発生を大幅に軽減すること
が出来る。したがって、半導体スイッチ素子との半田接
合部の半田の疲労を抑えることが可能になり、接合寿命
の高信頼かが可能となる。従って、半導体スイッチング
素子や半田接合部の半田の疲労を押さえることが可能と
なり、接合寿命の高信頼性化が可能となる。According to the second embodiment, the generation of the thermal stress due to the heat generated by the semiconductor switching element can be greatly reduced by reducing the rigidity of the wiring portion. Therefore, it is possible to suppress the fatigue of the solder at the solder joint portion with the semiconductor switch element, and it is possible to achieve high reliability of the joint life. Therefore, it is possible to suppress the fatigue of the semiconductor switching element and the solder at the solder joint, and to increase the reliability of the joint life.
【００５２】図３は本発明に関する半導体装置の第３の
実施の形態を示す断面図である。半導体スイッチング素
子の一つであるＩＧＢＴ１ａは、裏面に正極電極である
エミッタ電極４ａが配線基板である銅張セラミック基板
２ａの表面の銅パターン３ａの所定位置に半田層６ａに
よって半田接合されている。また、その裏面の端部には
制御電極であるゲート電極８ａが設けられ、同様に銅張
セラミック基板２ａの所定位置に半田層６ａによって半
田接合されている。また、銅張セラミック基板２ａの裏
面側には裏面の銅パターン３ａを介してヒートシンク１
２ａが半田層６ａによって半田接合されている。このヒ
ートシンク１２ａの周囲には図示しないプラスチック製
の外囲器が設けられ、ＩＧＢＴ１ａや銅張セラミック基
板２ａの表面は絶縁のためシリコンゲル等で封止されて
いる。FIG. 3 is a sectional view showing a third embodiment of the semiconductor device according to the present invention. An IGBT 1a, which is one of the semiconductor switching elements, has an emitter electrode 4a, which is a positive electrode, on the back surface, and is soldered to a predetermined position of a copper pattern 3a on the surface of a copper-clad ceramic substrate 2a, which is a wiring substrate, by a solder layer 6a. A gate electrode 8a serving as a control electrode is provided at an end of the back surface, and is similarly solder-bonded to a predetermined position of the copper-clad ceramic substrate 2a by a solder layer 6a. A heat sink 1 is provided on the back side of the copper-clad ceramic substrate 2a via the copper pattern 3a on the back side.
2a is soldered by the solder layer 6a. A plastic envelope (not shown) is provided around the heat sink 12a, and the surfaces of the IGBT 1a and the copper-clad ceramic substrate 2a are sealed with silicon gel or the like for insulation.
【００５３】ＩＧＢＴ１ａの表面には負極電極のコレク
タ電極５ａが所定の対向位置（半導体装置として表面側
に位置）に配設された導体７ａに半田層６ａを介して半
田接合されている。この導体７ａは、銅製の細導線を平
帯状に編み上げて成形されたものである。そして、この
導体７ａの長手方向の弾性率は１ＧＰａ以下が好まし
い。On the surface of the IGBT 1a, a collector electrode 5a of a negative electrode is solder-bonded via a solder layer 6a to a conductor 7a disposed at a predetermined facing position (position on the front side as a semiconductor device). The conductor 7a is formed by braiding a copper thin conductive wire into a flat band shape. The elastic modulus in the longitudinal direction of the conductor 7a is preferably 1 GPa or less.
【００５４】その結果、この第３の実施の形態の半導体
装置も、熱応力の発生を大幅に軽減することができるの
で、半田接合破壊を防止して長寿命化を図ることができ
る。As a result, also in the semiconductor device of the third embodiment, the occurrence of thermal stress can be greatly reduced, so that solder joint destruction can be prevented and the life can be extended.
【００５５】図４は、本発明の第４の実施の形態を示す
断面図である。半導体スイッチング素子の一つであるＩ
ＥＧＴ１１ａは、裏面に正極電極であるエミッタ電極４
ａが銅張りセラミック基板２ａの表面の銅パターン３a
の所定位置に半田接合され半田層６ａを形成している。
この半田層６ａの中には熱応力を緩和するための緩衝板
１６ａが挿入されている。緩衝板１６ａはＩＥＧＴ１１
ａに応力を加えないためにＩＥＧＴ1１ａの基材である
シリコンと熱膨張率の近い材料が好ましく、モリブテ
ン、タングステン等の単体金属や銅−タングステン、４
２アロイ等の合金や銅−インバー−銅等のクラッド材を
用いる。FIG. 4 is a sectional view showing a fourth embodiment of the present invention. I, one of the semiconductor switching elements
The EGT 11a has an emitter electrode 4 as a positive electrode on the back surface.
a is a copper pattern 3a on the surface of the copper-clad ceramic substrate 2a
At a predetermined position to form a solder layer 6a.
A buffer plate 16a for reducing thermal stress is inserted in the solder layer 6a. The buffer plate 16a is IEGT11
In order not to apply stress to a, a material having a coefficient of thermal expansion close to that of silicon, which is the base material of IEGT 11a, is preferable.
2 An alloy such as an alloy or a clad material such as copper-invar-copper is used.
【００５６】また、ＩＥＧＴ１１ａ表面の端部には制御
電極であるゲート電極８ａが設けられ、同様に銅張りセ
ラミック基板２ａの所定位置に半田層６ａで半田接合さ
れている。この半田層６ａも同様に緩衝板１６ａが挿入
されている。また、銅張りセラミック基板２ａの裏面側
にも表面の銅パターン３Ｙを介してヒートシンク１２ａ
が半田層６ａによって半田接合されている。このヒート
シンク１２ａの周囲には図示しないプラスチック製の外
囲器が設けられ、ＩＥＧＴ１１ａや銅張りセラミック基
板２ａの表面は絶縁のためシリコンゲル等で封止されて
いる。ＩＥＧＴ１１ａの表面には負極電極のコレクタ電
極５ａが（半導体装置として表面側に位置）対向位置に
配設された所定の導体７ａに半田層６ａを介して半田接
合されている。この半田層６ａにもエミッタ電極４ａ等
と同様に緩衝板１６ａが挿入されている。A gate electrode 8a as a control electrode is provided at an end of the surface of the IEGT 11a, and is similarly solder-bonded to a predetermined position of the copper-clad ceramic substrate 2a with a solder layer 6a. The buffer plate 16a is similarly inserted into the solder layer 6a. The heat sink 12a is also provided on the back side of the copper-clad ceramic substrate 2a via the copper pattern 3Y on the front side.
Are joined by the solder layer 6a. A plastic envelope (not shown) is provided around the heat sink 12a, and the surfaces of the IEGT 11a and the copper-clad ceramic substrate 2a are sealed with silicon gel or the like for insulation. On the surface of the IEGT 11a, a collector electrode 5a of a negative electrode is soldered to a predetermined conductor 7a disposed at an opposite position (located on the front surface side as a semiconductor device) via a solder layer 6a. A buffer plate 16a is inserted into the solder layer 6a as in the case of the emitter electrode 4a and the like.
【００５７】前記導体７ａは、銅製の細導線を平帯状に
編み上げて成形されたものである。そして、この導体７
ａの長手方向の弾性率は１ＧＰａ以下が好ましい。その
結果、この第４の実施の形態の半導体装置も、熱応力の
発生を大幅に軽減することができるので、半田接合破壊
を防止して長寿命化を図ることができる。The conductor 7a is formed by braiding a thin copper wire into a flat band. And this conductor 7
The elastic modulus in the longitudinal direction of a is preferably 1 GPa or less. As a result, also in the semiconductor device of the fourth embodiment, the occurrence of thermal stress can be greatly reduced, so that solder joint destruction can be prevented and the life can be extended.
【００５８】特に、半田層６ａ内に挿入している緩衝板
１２ａにより、熱応力を緩和することができる効果は、
平帯状に編み上げられた導体７ａを用いる効果と相俟っ
て相乗的に作用する。In particular, the effect of reducing the thermal stress by the buffer plate 12a inserted in the solder layer 6a is as follows.
It works synergistically with the effect of using the conductor 7a woven in a flat band shape.
【００５９】なお、各緩衝板１６ａはそれぞれ半田層６
ａの中に挿入されているが、半田で接合される部材のい
ずれかに接合してもよい。Each of the buffer plates 16a is connected to the solder layer 6
a, but may be joined to any of the members joined by solder.
【００６０】[0060]
【発明の効果】以上に述べたように本発明によれば、従
来の平板または棒状の電極に代えて、細導線を編み上げ
た導体を用いることで、配線インダクタンスが低い平板
配線の利点を保ったまま、電極の剛性を低下させたと共
に熱応力を小さくした。As described above, according to the present invention, the advantage of a flat wiring having a low wiring inductance is maintained by using a conductor in which fine conductive wires are woven in place of the conventional flat or rod-shaped electrode. As it was, the rigidity of the electrode was reduced and the thermal stress was reduced.
【００６１】従って、熱疲労による半導体素子の接合部
等の破壊を確実に防止することができる。Accordingly, it is possible to reliably prevent the destruction of the junction of the semiconductor element due to thermal fatigue.
【図１】本発明の第１の実施の形態の半導体装置を示す
断面図である。FIG. 1 is a sectional view showing a semiconductor device according to a first embodiment of the present invention.
【図２】本発明の第２の実施の形態の半導体装置を示す
断面図である。FIG. 2 is a sectional view showing a semiconductor device according to a second embodiment of the present invention.
【図３】本発明の第３の実施の形態の半導体装置を示す
断面図である。FIG. 3 is a sectional view showing a semiconductor device according to a third embodiment of the present invention.
【図４】本発明の第４の実施の形態の半導体装置を示す
断面図である。FIG. 4 is a sectional view showing a semiconductor device according to a fourth embodiment of the present invention.
【図５】従来の半導体装置を基板に実装した例を示す断
面図である。FIG. 5 is a cross-sectional view showing an example in which a conventional semiconductor device is mounted on a substrate.
【図６】従来の半導体装置を基板に実装した別の例を示
す断面図である。FIG. 6 is a cross-sectional view showing another example in which a conventional semiconductor device is mounted on a substrate.
１、１ａ、２１、２２…ＩＧＢＴ、２、２ａ，２４…Ｄ
ＢＣ基板（銅張セラミック基板）、３、３ａ…表面銅パ
ターン、４、４ａ、２３、２７…エミッタ電極、５、５
ａ、１０、４３、４４…コレクタ電極、６、６ａ…半田
（層）、７、７ａ…導体、８、３０、３１…ゲート電
極、１１…裏面銅パターン1, 1a, 21, 22 ... IGBT, 2, 2a, 24 ... D
BC substrate (copper-clad ceramic substrate), 3, 3a ... surface copper pattern, 4, 4a, 23, 27 ... emitter electrode, 5, 5
a, 10, 43, 44 ... collector electrode, 6, 6a ... solder (layer), 7, 7a ... conductor, 8, 30, 31 ... gate electrode, 11 ... backside copper pattern
Claims (10)
れ他表面に負極電極が形成された半導体スイッチング素
子と、金属導体が設けられ且つ前記半導体スイッチング
素子が実装される配線基板とを具備し、この配線基板の
金属導体の、前記正極電極及び制御電極及び負極電極の
少なくとも一つに対する電気的接続は、細導線を編み上
げた導体により行われていることを特徴とする半導体装
置。1. A semiconductor switching element having a positive electrode and a control electrode formed on one surface and a negative electrode formed on the other surface, and a wiring board provided with a metal conductor and mounted with the semiconductor switching element. An electrical connection of the metal conductor of the wiring board to at least one of the positive electrode, the control electrode and the negative electrode is made by a conductor formed by knitting fine conductive wires.
を編み上げた導体とは半田接合により接合されているこ
とを特徴とする請求項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein the metal conductor of the wiring board and the conductor obtained by knitting the fine conductive wire are joined by soldering.
ている前記正極電極及び前記制御電極及び前記負極電極
の少なくとも一つは半田接合により接合されていること
を特徴とする請求項１記載の半導体装置。3. The method according to claim 1, wherein at least one of the positive electrode, the control electrode, and the negative electrode, which are connected to the conductor in which the fine conductive wire is braided, is joined by soldering. Semiconductor device.
素子又はＩＥＧＴ素子であることを特徴とする請求項１
記載の半導体装置。4. The semiconductor switching device according to claim 1, wherein the semiconductor switching element is an IGBT.
2. An element or an IEGT element.
13. The semiconductor device according to claim 1.
導体を形成したものであることを特徴とする請求項１記
載の半導体装置。5. The semiconductor device according to claim 1, wherein said wiring substrate is formed by forming a metal conductor on a ceramic substrate.
形成し、さらにその上に金属導体を形成したものである
ことを特徴とする請求項１記載の半導体装置。6. The semiconductor device according to claim 1, wherein said wiring board is formed by forming an insulating layer on a metal base and further forming a metal conductor thereon.
上げたものであることを特徴とする請求項１記載の半導
体装置。7. The semiconductor device according to claim 1, wherein the fine conductive wire is formed by braiding a copper wire into a flat band shape.
の長手方向の弾性率が１ＧＰａ以下であることを特徴と
する請求項７記載の半導体装置。8. The semiconductor device according to claim 7, wherein a longitudinal elastic modulus of the conductor in which the fine conductive wire is woven in a flat band shape is 1 GPa or less.
記配線基板上設けられた際に、各半導体スイッチング素
子間の配線の一部として細導線を編み上げた導体を使用
したことを特徴とする半導体装置。9. A semiconductor device, wherein when a plurality of the semiconductor switching elements are provided on the wiring board, a conductor in which a fine conductive wire is braided is used as a part of a wiring between the semiconductor switching elements.
され且つ他裏面に負極電極が形成された半導体スイッチ
ング素子と、金属導体が設けられ且つ前記半導体スイッ
チ素子が実装される配線基板とを具備する半導体装置の
製造方法において、 前記正極電極と前記制御電極とを前記配線基板の金属導
体に対して半田接合するか、又は、前記負極電極を前記
配線基板の金属導体に対して半田接合する第１の半田接
合工程と、 前記正極電極及び前記制御電極及び前記負極電極の少な
くとも一つを一端が前記配線基板の金属導体に電気的に
接続される細導線を編み上げた導体の他端に半田接合す
る第２の半田接合工程とを有することを特徴とする半導
体装置の製造方法。10. A semiconductor switching element having a positive electrode and a control electrode formed on one surface and a negative electrode formed on the other back surface, and a wiring board on which a metal conductor is provided and on which the semiconductor switch element is mounted. In the method for manufacturing a semiconductor device provided, the positive electrode and the control electrode are soldered to a metal conductor of the wiring board, or the negative electrode is soldered to a metal conductor of the wiring board. A first solder bonding step, and soldering at least one of the positive electrode, the control electrode, and the negative electrode to the other end of a conductor in which a fine conductive wire having one end electrically connected to a metal conductor of the wiring board is knitted; And a second solder bonding step of bonding.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21704898A JP2000049280A (en) | 1998-07-31 | 1998-07-31 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21704898A JP2000049280A (en) | 1998-07-31 | 1998-07-31 | Semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2000049280A true JP2000049280A (en) | 2000-02-18 |
Family
ID=16698023
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21704898A Pending JP2000049280A (en) | 1998-07-31 | 1998-07-31 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2000049280A (en) |
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| JP2002043508A (en) * | 2000-07-25 | 2002-02-08 | Mitsubishi Electric Corp | Semiconductor device and its manufacturing method |
| JP2003023137A (en) * | 2001-07-09 | 2003-01-24 | Sansha Electric Mfg Co Ltd | Power semiconductor module |
| JP4669650B2 (en) * | 2001-12-06 | 2011-04-13 | エー ビー ビー リサーチ リミテッド | Power semiconductor module |
| JP2003197864A (en) * | 2001-12-06 | 2003-07-11 | Abb Res Ltd | Power semiconductor module |
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