JP2000049168A - Semiconductor device - Google Patents

Semiconductor device

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Publication number
JP2000049168A
JP2000049168A JP10216679A JP21667998A JP2000049168A JP 2000049168 A JP2000049168 A JP 2000049168A JP 10216679 A JP10216679 A JP 10216679A JP 21667998 A JP21667998 A JP 21667998A JP 2000049168 A JP2000049168 A JP 2000049168A
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JP
Japan
Prior art keywords
region
semiconductor device
semiconductor
semiconductor substrate
conductivity type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10216679A
Other languages
Japanese (ja)
Other versions
JP3012227B2 (en
Inventor
Shinichi Sonetaka
真一 曽根高
Tetsuo Shirakawa
哲夫 白川
Shinji Fukumoto
信治 福本
Noriko Ohashi
則子 大橋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
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Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP10216679A priority Critical patent/JP3012227B2/en
Publication of JP2000049168A publication Critical patent/JP2000049168A/en
Application granted granted Critical
Publication of JP3012227B2 publication Critical patent/JP3012227B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
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    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

PROBLEM TO BE SOLVED: To reduce the input capacity of a junction type field effect semiconductor element. SOLUTION: An N type epitaxial layer 10 is formed on P type semiconductor substrates 8, 9 and a P type internal isolation region 1 is made through the N type epitaxial layer 10 in the center of the P type semiconductor substrate 8 until the bottom thereof reaches the P type semiconductor substrate 9 in order to separate the N type epitaxial layer 10 into inner and outer regions. The gate region 3 of a junction type field effect semiconductor element is provided on the inner region 15 of the N type epitaxial layer 10 serving as the source-drain region of the junction type field effect semiconductor element while being surrounded by the internal isolation region 1. Furthermore, an external connection region 2 of same conductivity type as the semiconductor substrate is provided at the end of the P type semiconductor substrate 8. A resistor element 12 is provided on the outer region of the N type epitaxial layer 10 and connected with the external connection region 2.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、接合型電界効果半
導体素子（ＪＦＥＴ）と他の回路素子を複合一体化した
半導体装置に関するものである。特に、得られる電荷量
が微少で内部インピーダンスの高いセンサ（例：赤外線
センサである焦電センサ等）の信号検出用半導体装置
で、他の回路素子が薄膜で中でも高抵抗であるものに関
する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a junction field effect semiconductor device (JFET) and another circuit device are combined and integrated. In particular, the present invention relates to a semiconductor device for detecting a signal of a sensor that obtains a small amount of electric charge and has a high internal impedance (eg, a pyroelectric sensor that is an infrared sensor), in which other circuit elements are thin films and have high resistance among them.

【０００２】[0002]

【従来の技術】従来、赤外線検出装置は、赤外線センサ
等で得られる微少な電荷を検出増幅することによって、
赤外線検出を行うものである。一例としては、特開平６
−１８８３７０号公報に開示されているような赤外線セ
ンサ回路２０を有した赤外線検出装置がある。2. Description of the Related Art Conventionally, an infrared detecting device detects and amplifies minute electric charges obtained by an infrared sensor or the like, thereby
It performs infrared detection. One example is disclosed in
There is an infrared detection device having an infrared sensor circuit 20 as disclosed in Japanese Patent Publication No. 188370.

【０００３】その回路構成は、図６に示すように、赤外
線センサ２１、接合型電界効果半導体素子（トランジス
タ）２３、抵抗２２、抵抗２４よりなる。２５は出力端
子、２６は電源端子、２７は接地端子である。赤外線セ
ンサ回路２０は、赤外線が赤外線センサ２１に当たると
センサ表面に電荷が発生し、この電荷が接合型電界効果
半導体素子２３のゲート電極に流れ、接合型電界効果半
導体素子２３をオン状態にし、その結果、接合型電界効
果半導体素子２３に電流が流れ、出力端子２５に出力電
圧が検出される。As shown in FIG. 6, the circuit configuration comprises an infrared sensor 21, a junction type field effect semiconductor element (transistor) 23, a resistor 22, and a resistor 24. 25 is an output terminal, 26 is a power supply terminal, and 27 is a ground terminal. The infrared sensor circuit 20 generates an electric charge on the sensor surface when the infrared light strikes the infrared sensor 21, the electric charge flows to the gate electrode of the junction field effect semiconductor element 23, and turns on the junction field effect semiconductor element 23. As a result, a current flows through the junction type field effect semiconductor element 23, and an output voltage is detected at the output terminal 25.

【０００４】通常、赤外線センサ回路２０は、赤外線セ
ンサ２１と接合型電界効果半導体素子２３と抵抗体２２
（例えばセラミックやタンタル化合物等）と抵抗器２４
との各単品素子等よりなるハイブリッド部品として製品
化されている。しかしながら、赤外線センサ２１が焦電
素子のように、内部インピーダンスが非常に大きく（十
ＧΩ〜数十ＧΩ）、得られる電荷量も少ない場合、接合
型電界効果半導体素子２３のインピーダンスと焦電素子
とのインピーダンスのマッチングを図るためには、極め
て抵抗値の高い抵抗体２２を赤外線センサ２１と接合型
電界効果半導体素子２３の間に並列に挿入する必要があ
る。また、高周波ノイズを除去して微少電荷を増幅し、
安定した出力を得るためには、低入力容量の接合型電界
効果半導体素子２３で高周波ノイズを除去することが必
要になる。Normally, the infrared sensor circuit 20 comprises an infrared sensor 21, a junction type field effect semiconductor element 23 and a resistor 22.
(For example, ceramic or tantalum compound) and the resistor 24
And has been commercialized as a hybrid component composed of individual components and the like. However, when the infrared sensor 21 has a very large internal impedance (ten GΩ to several tens GΩ) and a small amount of electric charge, like a pyroelectric element, the impedance of the junction type field effect semiconductor element 23 and the pyroelectric element In order to achieve the impedance matching, it is necessary to insert a resistor 22 having an extremely high resistance value between the infrared sensor 21 and the junction type field effect semiconductor element 23 in parallel. Also, remove high frequency noise and amplify minute charges,
In order to obtain a stable output, it is necessary to remove high-frequency noise with the junction type field effect semiconductor element 23 having a low input capacitance.

【０００５】また、一つの半導体チップ上に抵抗体と接
合型電界効果半導体素子を形成した焦電型赤外線センサ
の半導体装置も提供されている。この半導体装置につい
ては実開平６−３９７６７号公報に開示されている。図
７に上記半導体装置の断面図を示す。この半導体装置
は、図７に示すように、Ｐ型半導体（シリコン）基板３
１上にチャンネルとなるＮ型領域３２を形成し、このＮ
型領域３２上に内側Ｐ型ゲート領域３３を形成してい
る。この場合、Ｎ型領域３２と、Ｎ型領域３２に囲まれ
た内側Ｐ型ゲート領域３３および外側Ｐ型ゲート領域、
つまりＰ型半導体基板３１で接合型電界効果半導体素子
３８が構成されており、内側Ｐ型ゲート領域３３と外側
Ｐ型ゲート領域であるＰ型半導体基板３１とは電気的に
接続されている。Also, there has been provided a semiconductor device of a pyroelectric infrared sensor in which a resistor and a junction type field effect semiconductor element are formed on one semiconductor chip. This semiconductor device is disclosed in Japanese Utility Model Laid-Open No. 6-39767. FIG. 7 shows a cross-sectional view of the semiconductor device. This semiconductor device has a P-type semiconductor (silicon) substrate 3 as shown in FIG.
An N-type region 32 serving as a channel is formed on
An inner P-type gate region 33 is formed on the mold region 32. In this case, the N-type region 32, the inner P-type gate region 33 and the outer P-type gate region surrounded by the N-type region 32,
In other words, the junction type field effect semiconductor element 38 is constituted by the P-type semiconductor substrate 31, and the inner P-type gate region 33 and the P-type semiconductor substrate 31, which is the outer P-type gate region, are electrically connected.

【０００６】また、Ｐ型半導体基板３１表面上には、金
属膜等の抵抗素子３４が形成されている。この他に、Ｐ
型半導体基板３１表面上には、金属配線からなるドレイ
ン電極３５とソース電極３６と出力電極３７が形成され
ていて、ソース電極３６は延長されて抵抗素子３４の一
端にも接続されていて、接合型電界効果半導体素子３８
のソースと抵抗素子３４の一端が電気的に接続されてい
る。Ｐ型半導体基板３１の裏面には、金属膜等からなる
裏面ゲート電極３９が形成されている。On the surface of the P-type semiconductor substrate 31, a resistance element 34 such as a metal film is formed. In addition, P
On the surface of the mold semiconductor substrate 31, a drain electrode 35, a source electrode 36, and an output electrode 37 made of metal wiring are formed, and the source electrode 36 is extended and connected to one end of the resistance element 34. Type field effect semiconductor device 38
And one end of the resistance element 34 are electrically connected. On the back surface of the P-type semiconductor substrate 31, a back gate electrode 39 made of a metal film or the like is formed.

【０００７】この場合、接合型電界効果半導体素子３８
の入力容量は、接合型電界効果半導体素子３８が形成さ
れている領域のＰＮ接合容量と、配線およびボンディン
グパッド直下の容量とで決まる。通常、入力容量を低く
するためには、半導体チップの表面にゲート用ボンディ
ングパッドを設けず、外側Ｐ型ゲート領域となるＰ型半
導体基板３１の裏面ゲートに金属膜等で裏面ゲート電極
３９を設け、半導体チップを半導体素子載置部を有した
リードフレームにダイスボンドすることによりゲート用
外部リードと裏面ゲート電極３９を接続している。In this case, the junction type field effect semiconductor device 38
Is determined by the PN junction capacitance in the region where the junction field effect semiconductor element 38 is formed and the capacitance immediately below the wiring and the bonding pad. Normally, in order to lower the input capacitance, a bonding pad for a gate is not provided on the surface of the semiconductor chip, and a back gate electrode 39 made of a metal film or the like is provided on the back gate of the P-type semiconductor substrate 31 serving as an outer P-type gate region. The external lead for the gate and the back gate electrode 39 are connected by dice bonding the semiconductor chip to a lead frame having a semiconductor element mounting portion.

【０００８】[0008]

【発明が解決しようとする課題】１チップに接合型電界
効果半導体素子と抵抗素子を形成した従来の半導体装置
においては、接合型電界効果半導体素子の表面に抵抗領
域を設けた構成では、熱等の変動で抵抗領域に半導体基
板からの不純物の拡散等で抵抗値が変動した。また、接
合型電界効果半導体素子と抵抗領域が直接に接するため
に接合型電界効果半導体素子の入力容量が大きくなり、
焦電型赤外線センサにおいて外部からの高周波ノイズが
十分除去できないため、微少電荷を増幅するのに安定し
た出力が得られなかった。In a conventional semiconductor device in which a junction field-effect semiconductor element and a resistance element are formed on one chip, a structure in which a resistance region is provided on the surface of the junction field-effect semiconductor element requires heat or the like. , The resistance value fluctuated due to diffusion of impurities from the semiconductor substrate into the resistance region. In addition, since the junction field-effect semiconductor element and the resistance region are in direct contact, the input capacitance of the junction field-effect semiconductor element increases,
Since a pyroelectric infrared sensor cannot sufficiently remove high frequency noise from the outside, a stable output for amplifying minute charges cannot be obtained.

【０００９】また、様々なセンサ材料に対してインピー
ダンスマッチングをとるのに別々の半導体チップを作ら
なければならなかった。さらに、抵抗素子の抵抗値を測
定するのに、裏面ゲート−抵抗端子間の抵抗を測定する
検査方法では、接合型電界効果半導体素子を介して検査
するので、接合型電界効果半導体素子の不良と抵抗部の
抵抗値との区別が困難であった。In addition, separate semiconductor chips have to be manufactured to achieve impedance matching for various sensor materials. Furthermore, in order to measure the resistance value of the resistance element, in the inspection method of measuring the resistance between the back gate and the resistance terminal, the inspection is performed via the junction field effect semiconductor element. It was difficult to distinguish the resistance value from the resistance value.

【００１０】本発明の第１の目的は、接合型電界効果半
導体素子の入力容量を小さくすることができる半導体装
置を提供することである。本発明の第２の目的は、回路
素子例えば、抵抗素子の特性の変動のない半導体装置の
提供することである。本発明の第３の目的は、回路素子
例えば、抵抗素子の特性の調整を容易に行うことができ
る半導体装置を提供することである。A first object of the present invention is to provide a semiconductor device capable of reducing the input capacitance of a junction type field effect semiconductor element. A second object of the present invention is to provide a semiconductor device in which characteristics of a circuit element, for example, a resistance element do not change. A third object of the present invention is to provide a semiconductor device capable of easily adjusting characteristics of a circuit element, for example, a resistance element.

【００１１】本発明の第４の目的は、回路素子例えば、
抵抗素子の検査を容易に行うことができる半導体装置を
提供することである。A fourth object of the present invention is to provide a circuit element, for example,
An object of the present invention is to provide a semiconductor device capable of easily inspecting a resistance element.

【００１２】[0012]

【課題を解決するための手段】本発明の半導体装置は、
接合型電界効果半導体素子と薄膜でできた高抵抗素子を
複合一体化した半導体装置であり、以下のように構成す
ることで、上記の目的を達成するものである。請求項１
記載の半導体装置は、一導電型の半導体基板と、この半
導体基板上に形成された逆導電型層と、逆導電型層を貫
通して底部が半導体基板まで達する状態に半導体基板の
中央部付近に設けられて逆導電型層を内側領域と外側領
域とに分離する半導体基板と同一導電型の内部分離領域
と、内部分離領域で囲まれて接合型電界効果半導体素子
のソース／ドレイン領域となる逆導電型層の内側領域上
に設けられた接合型電界効果半導体素子のゲート領域
と、逆導電型層を貫通して底部が半導体基板まで達する
状態に半導体基板の端縁部に設けられた半導体基板と同
一導電型の外部接続領域と、逆導電型層の外側領域上に
設けられて外部接続領域に接続された回路素子とを備え
ている。According to the present invention, there is provided a semiconductor device comprising:
The present invention is a semiconductor device in which a junction field-effect semiconductor element and a high-resistance element made of a thin film are combined and integrated, and achieves the above object by configuring as follows. Claim 1
The described semiconductor device includes a semiconductor substrate of one conductivity type, a reverse conductivity type layer formed on the semiconductor substrate, and a central portion of the semiconductor substrate in a state in which the bottom portion reaches the semiconductor substrate through the reverse conductivity type layer. And an internal isolation region of the same conductivity type as the semiconductor substrate separating the opposite conductivity type layer into an inner region and an outer region, and a source / drain region of a junction field effect semiconductor element surrounded by the internal isolation region. A gate region of a junction field effect semiconductor device provided on an inner region of the opposite conductivity type layer, and a semiconductor provided at an edge of the semiconductor substrate so that the bottom portion reaches the semiconductor substrate through the opposite conductivity type layer An external connection region of the same conductivity type as the substrate and a circuit element provided on the outer region of the opposite conductivity type layer and connected to the external connection region are provided.

【００１３】この構成によれば、逆導電型層を内部分離
領域で内側領域と外側領域とに分離し、内側領域のみを
接合型電界効果半導体素子の形成領域とし、また、回路
素子を接合型電界効果半導体素子が形成されていない外
側領域上に配置したので、接合型電界効果半導体素子の
入力容量を小さくできる。請求項２記載の半導体装置
は、請求項１記載の半導体装置において、半導体基板が
矩形のチップ形状であって、外部接続領域が半導体基板
の周囲端部に矩形枠状に設けられ、逆導電型層の外側領
域上に少なくとも１個以上のボンディングパッドが設け
られたことを特徴とする。According to this structure, the reverse conductivity type layer is separated into an inner region and an outer region by the inner separation region, only the inner region is used as a junction type field effect semiconductor element formation region, and the circuit element is formed by the junction type. Since it is arranged on the outer region where the field effect semiconductor element is not formed, the input capacitance of the junction field effect semiconductor element can be reduced. According to a second aspect of the present invention, in the semiconductor device according to the first aspect, the semiconductor substrate has a rectangular chip shape, and the external connection region is provided in a rectangular frame shape at a peripheral end of the semiconductor substrate. At least one bonding pad is provided on an outer region of the layer.

【００１４】この構成によれば、請求項１と同様の作用
を有する。請求項３記載の半導体装置は、請求項２記載
の半導体装置において、ボンディングパッドとして、回
路素子に接続される少なくとも１個のボンディングパッ
ドと、ソース／ドレイン領域にそれぞれ接続される少な
くとも２個のボンディングパッドとがあり、各々のボン
ディングパッドが逆導電型層の外側領域上の矩形枠状の
外部接続領域の各コーナー部の近傍位置に配置されたこ
とを特徴とする。According to this configuration, the same operation as that of the first aspect is obtained. According to a third aspect of the present invention, in the semiconductor device according to the second aspect, at least one bonding pad connected to a circuit element and at least two bonding pads respectively connected to source / drain regions are provided as bonding pads. And bonding pads are arranged at positions near the corners of the rectangular frame-shaped external connection region on the outer region of the opposite conductivity type layer.

【００１５】この構成によれば、請求項１と同様の作用
を有する。請求項４記載の半導体装置は、請求項１記載
の半導体装置において、回路素子が機能領域と、この機
能領域の一端に設けた共通接続部と、機能領域の他端に
設けたボンディングパッド部とからなり、共通接続部が
外部接続領域に接続されていることを特徴とする。According to this configuration, the same operation as that of the first aspect is provided. According to a fourth aspect of the present invention, in the semiconductor device according to the first aspect, the circuit element includes a functional region, a common connection portion provided at one end of the functional region, and a bonding pad portion provided at the other end of the functional region. And the common connection portion is connected to the external connection region.

【００１６】この構成によれば、請求項１と同様の作用
を有する。請求項５記載の半導体装置は、請求項４記載
の半導体装置において、回路素子の共通接続部とボンデ
ィングパッド部とが半導体基板の端部側に設けられ、回
路素子の機能領域が半導体基板の内部側に設けられてい
ることを特徴とする。この構成によれば、請求項１と同
様の作用を有する。According to this configuration, the same operation as that of the first aspect is obtained. According to a fifth aspect of the present invention, in the semiconductor device according to the fourth aspect, the common connection portion of the circuit element and the bonding pad portion are provided on the end side of the semiconductor substrate, and the functional region of the circuit element is located inside the semiconductor substrate. It is characterized by being provided on the side. According to this configuration, the same operation as that of the first aspect is provided.

【００１７】請求項６記載の半導体装置は、請求項１ま
たは５記載の半導体装置において、回路素子の機能領域
の共通接続部側と反対側が少なくとも２つ以上に分岐さ
れ、分岐された機能領域の他端側の各々にボンディング
パッドが設けられていることを特徴とする。この構成に
よれば、請求項１と同様の作用を有する他、回路素子の
機能領域の共通接続部側と反対側が少なくとも２つ以上
に分岐され、分岐された機能領域の他端側の各々にボン
ディングパッドが設けられているので、ボンディングパ
ッドを用いて回路素子の検査を単体の接合型半導体素子
を経由せずに行うことができ、回路素子の特性を確実に
かつ容易に測定することができ、また、分岐した複数の
他端の一部を使用するか、全部を使用するかによって、
回路素子の特性を容易に調整することができる。According to a sixth aspect of the present invention, there is provided the semiconductor device according to the first or fifth aspect, wherein a side of the functional region of the circuit element opposite to the side of the common connection portion is branched into at least two or more. A bonding pad is provided on each of the other ends. According to this configuration, in addition to having the same operation as the first aspect, the side opposite to the common connection portion side of the functional region of the circuit element is branched into at least two or more, and each of the other ends of the branched functional region is Since bonding pads are provided, circuit elements can be inspected using the bonding pads without passing through a single junction type semiconductor element, and the characteristics of the circuit elements can be measured reliably and easily. Depending on whether some or all of the branched other ends are used,
The characteristics of the circuit element can be easily adjusted.

【００１８】請求項７記載の半導体装置は、請求項１記
載の半導体装置において、ゲート領域が半導体基板と同
一導電型であり、逆導電型層の内側領域上に逆導電型層
の内側領域をソース領域とドレイン領域とに分断するよ
うに両端が内部分離領域と接する状態に設けられたこと
を特徴とする。この構成によれば、請求項１と同様の作
用を有する。According to a seventh aspect of the present invention, in the semiconductor device of the first aspect, the gate region has the same conductivity type as the semiconductor substrate, and the inside region of the opposite conductivity type layer is formed on the inside region of the opposite conductivity type layer. It is characterized in that both ends are provided in contact with the internal isolation region so as to be divided into a source region and a drain region. According to this configuration, the same operation as that of the first aspect is provided.

【００１９】請求項８記載の半導体装置は、請求項１記
載の半導体装置において、回路素子が薄膜抵抗であり、
狭幅線状領域を実質的な機能領域とし、少なくとも狭幅
線状領域の一端部にボンディングパッドの外形よりも大
きい幅広領域を有し、幅広領域上にボンディングパッド
用の金属電極を設けたことを特徴とする。この構成によ
れば、請求項１と同様の作用を有する。According to an eighth aspect of the present invention, in the semiconductor device according to the first aspect, the circuit element is a thin film resistor,
The narrow linear region is regarded as a substantial functional region, and at least one end of the narrow linear region has a wide region larger than the outer shape of the bonding pad, and a metal electrode for the bonding pad is provided on the wide region. It is characterized by. According to this configuration, the same operation as that of the first aspect is provided.

【００２０】請求項９記載の半導体装置は、請求項１記
載の半導体装置において、回路素子が外部接続領域と内
部分離領域との間の逆導電型層上でそれと対応した配置
形状の第１の絶縁膜上に設けられたことを特徴とする。
この構成によれば、請求項１と同様の作用を有する他、
第１の絶縁膜の上に回路素子が設けられているので、不
純物が回路素子に拡散することがなく、その特性の変動
を防止することができる。According to a ninth aspect of the present invention, there is provided the semiconductor device according to the first aspect, wherein the circuit element is arranged on the opposite conductivity type layer between the external connection region and the internal isolation region in the first configuration having a corresponding arrangement shape. It is characterized by being provided on an insulating film.
According to this configuration, in addition to having the same operation as the first aspect,
Since the circuit element is provided on the first insulating film, the impurity does not diffuse into the circuit element, so that a change in the characteristic can be prevented.

【００２１】請求項１０記載の半導体装置は、請求項９
記載の半導体装置において、回路素子が第１の絶縁膜よ
り厚い第２の絶縁膜で覆われ、第２の絶縁膜の開き領域
を通して回路素子に接続される金属電極が設けられ、金
属電極を介して回路素子が外部接続領域と接続されるこ
とを特徴とする。この構成によれば、請求項１と同様の
作用を有する。According to a tenth aspect of the present invention, there is provided a semiconductor device according to the ninth aspect.
In the semiconductor device described above, the circuit element is covered with a second insulating film thicker than the first insulating film, and a metal electrode connected to the circuit element through an open region of the second insulating film is provided. And the circuit element is connected to the external connection region. According to this configuration, the same operation as that of the first aspect is provided.

【００２２】請求項１１記載の半導体装置は、請求項１
０記載の半導体装置において、内部分離領域上および逆
導電型層の内側領域上が第２の絶縁膜で保護され、外部
接続領域がスクライブライン部と兼ねられ、外部接続領
域にスクライブ用の第２の絶縁膜の開き領域が設けられ
ていることを特徴とする。この構成によれば、請求項１
と同様の作用を有する。The semiconductor device according to the eleventh aspect is the first aspect.
0, the inner isolation region and the inner region of the opposite conductivity type layer are protected by a second insulating film, the external connection region also serves as a scribe line portion, and a second scribe line is formed in the external connection region. Characterized in that an open region of the insulating film is provided. According to this configuration, claim 1
Has the same function as.

【００２３】請求項１２記載の半導体装置は、請求項１
記載の半導体装置において、半導体素子載置部を有した
リードフレームに半導体素子載置部から一体に導出され
たゲート用外部リードを設け、半導体素子載置部に一導
電型で下部に高濃度領域を設けた半導体基板を載置し、
半導体基板の外部接続領域を介して回路素子をゲート用
外部リードに接続したことを特徴とする。According to a twelfth aspect of the present invention, there is provided a semiconductor device according to the first aspect.
In the semiconductor device described above, a lead frame having a semiconductor element mounting portion is provided with an external lead for a gate that is integrally led out from the semiconductor element mounting portion, and the semiconductor element mounting portion has one conductivity type and a high-concentration region below. Place the semiconductor substrate provided with
The circuit element is connected to an external lead for a gate via an external connection region of the semiconductor substrate.

【００２４】この構成によれば、請求項１と同様の作用
を有する他、回路素子の接続のためのワイヤを省くこと
ができる。請求項１３記載の半導体装置は、請求項６記
載の半導体装置において、分岐された機能領域の他端側
の各々の少なくとも２個以上のボンディングパッド間を
測定することにより機能領域の製造上の部分的特性を計
測可能としたことを特徴とする。According to this configuration, in addition to having the same operation as the first aspect, it is possible to omit wires for connecting circuit elements. A semiconductor device according to a thirteenth aspect of the present invention is the semiconductor device according to the sixth aspect, wherein a portion between at least two or more bonding pads on each of the other end sides of the branched functional region is measured to manufacture the functional region. Characteristic characteristics can be measured.

【００２５】この構成によれば、請求項１と同様の作用
を有する他、機能素子の製造上の部分的特性を電界効果
型半導体素子の影響を受けずに計測することができる。
請求項１４記載の半導体装置は、矩形の半導体素子載置
部と、この半導体素子載置部から独立した状態で半導体
素子載置部のコーナー部付近から外方へ延出された外部
リードと、矩形のチップ形状を有し表面に一辺の近傍で
一辺の長さ方向に並んだ状態の２個以上のボンディング
パッドを有し、外部リードが延出された半導体素子載置
部のコーナー部に一辺が対向する状態に半導体素子載置
部に載置された半導体基板と、２個以上のボンディング
パッドと外部リードの基端部とを各々接続するほぼ均等
な長さの２本以上のワイヤとを備えている。According to this configuration, in addition to having the same operation as that of the first aspect, it is possible to measure a partial characteristic in manufacturing the functional element without being affected by the field effect semiconductor element.
The semiconductor device according to claim 14, a rectangular semiconductor element mounting portion, and an external lead extending outward from a vicinity of a corner of the semiconductor element mounting portion independently of the semiconductor element mounting portion, It has a rectangular chip shape, has two or more bonding pads on the surface in the vicinity of one side and arranged in the length direction of one side, and has one side at the corner of the semiconductor element mounting part where external leads are extended. Are connected to the semiconductor substrate mounted on the semiconductor element mounting portion and two or more wires having substantially equal lengths for connecting the two or more bonding pads and the base ends of the external leads, respectively. Have.

【００２６】この構成によれば、２個以上のボンディン
グパッドと外部リードの基端部とを各々ほぼ均等な長さ
の２本以上のワイヤで接続するので、２個以上のボンデ
ィングパッドと外部リードの基端部との間の配線抵抗を
ほぼ同じ値にすることができる。According to this configuration, the two or more bonding pads and the base ends of the external leads are connected by two or more wires each having a substantially equal length. Can be made substantially the same value.

【００２７】[0027]

【発明の実施の形態】本発明の実施の形態の半導体装置
について図面を参照しながら説明する。図１に実施の形
態の半導体装置における半導体チップ表面の平面図を示
し、図２に図１のＡ−Ａ’線断面図を示す。この半導体
装置は、図１および図２に示すように、一導電型の半導
体基板である１５０μｍ厚の高不純物濃度のＰ++型半導
体基板８上に１０〜１５μｍ厚のＰ型エピタキシャル層
９および逆導電型層である２．５〜３．５μｍ厚のＮ型
エピタキシャル層（逆導電型層）１０とを設けてある。
その上に、第１の絶縁膜１１としてシリコン酸化膜を熱
酸化で約６０００Åに形成してある。DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a plan view of a semiconductor chip surface in the semiconductor device according to the embodiment, and FIG. 2 is a cross-sectional view taken along line AA ′ of FIG. As shown in FIGS. 1 and 2, the semiconductor device has a P-type epitaxial layer 9 having a thickness of 10 to 15 μm on a P ++ type semiconductor substrate 8 having a high impurity concentration of 150 μm and a semiconductor substrate of one conductivity type. An N-type epitaxial layer (reverse conductivity type layer) 10 having a thickness of 2.5 to 3.5 μm, which is a reverse conductivity type layer, is provided.
On top of that, a silicon oxide film is formed as a first insulating film 11 at about 6000 ° by thermal oxidation.

【００２８】つぎに、接合型電界効果半導体素子機能領
域と周辺領域を分離し、接合型電界効果半導体素子を囲
んで接合型電界効果半導体素子機能領域となる開き領域
を有する矩形枠形のＰ+ 型の内部分離領域１と矩形のチ
ップ周辺部を囲む矩形枠形のＰ+ 型の外部接続領域２と
を、図５に示すように第１の絶縁膜１１に対してフォト
エッチングにより内部分離領域１およびチップ周辺部を
囲む外部接続領域２に対応する箇所を部分的に除去する
ようにパターンニングを行った後、第１の絶縁膜１１を
選択拡散のマスクとして用いることで形成する。具体的
には、第１の絶縁膜１１をマスクとして選択拡散を行う
ことにより、Ｐ型高濃度分離領域である内部分離領域１
と外部接続領域２とを第２のＮ型エピタキシャル層１０
より深く、つまり、底部が半導体基板８上のＰ型エピタ
キシャル層９に入り込む状態となるように、約５．５μ
ｍ厚に形成してある。Next, the junction field effect semiconductor device functional region and the peripheral region are separated, and a rectangular frame-shaped P + having an open region surrounding the junction field effect semiconductor device and serving as the junction field effect semiconductor device function region is provided. a type external connection region 2 of P + -type rectangular frame shape surrounding the inner isolation region 1 and the rectangular chip peripheral portion of the internal isolation region by photoetching on the first insulating film 11 as shown in FIG. 5 After patterning is performed so as to partially remove the portion corresponding to the external connection region 2 surrounding the chip 1 and the periphery of the chip, the first insulating film 11 is formed by using the mask as a selective diffusion mask. More specifically, by selectively performing diffusion using the first insulating film 11 as a mask, the internal isolation region 1 which is a P-type high-concentration isolation region is formed.
And the external connection region 2 are connected to the second N-type epitaxial layer 10.
A depth of about 5.5 μm is set so as to be deeper, that is, a state in which the bottom enters the P-type epitaxial layer 9 on the semiconductor substrate 8.
m thickness.

【００２９】つぎに、内部分離領域１の内側に両端が内
部分離領域１に重なるＰ+ 型のゲート領域３を第１の絶
縁膜１１をフォトエッチングにより部分的に除去してパ
ターンニングした後、それを選択拡散のマスクとして用
いることにより形成する。具体的には、第１の絶縁膜１
１をマスクとする選択拡散により、内部分離領域１の内
側のＮ型エピタキシャル層１５内にＮ型エピタキシャル
層１５より浅い深さで約１．５μｍ厚のＰ型高濃度ゲー
ト領域であるゲート領域３を形成してある。Next, the P + -type gate region 3 whose both ends overlap the internal isolation region 1 inside the internal isolation region 1 is patterned by partially removing the first insulating film 11 by photoetching. It is formed by using it as a mask for selective diffusion. Specifically, the first insulating film 1
1 as a mask, a gate region 3 which is a P-type high-concentration gate region having a depth of about 1.5 μm and a depth smaller than that of the N-type epitaxial layer 15 is formed in the N-type epitaxial layer 15 inside the internal isolation region 1. Is formed.

【００３０】この場合、ゲート領域３が半導体基板８と
同一導電型のＰ型であり、Ｎ型エピタキシャル素子１５
をソース領域とドレイン領域とに分断するように両端が
内部分離領域１と接する状態に設けられている。また、
内部分離領域１と外部接続領域２の間の第１の絶縁膜１
１上には、比抵抗が１０8 〜１０10Ωｃｍ程度のノンド
ープ多結晶シリコン層がＬＰＣＶＤ法によって抵抗素子
（機能素子）１２として形成してある。In this case, the gate region 3 is of the P-type having the same conductivity type as the semiconductor substrate 8 and the N-type epitaxial element 15 is formed.
Are separated from each other into a source region and a drain region so that both ends are in contact with the internal isolation region 1. Also,
First insulating film 1 between internal isolation region 1 and external connection region 2
On 1, a non-doped polycrystalline silicon layer having a specific resistance of about 10 8 to 10 10 Ωcm is formed as a resistance element (functional element) 12 by an LPCVD method.

【００３１】さらに、チップ表面全面に約９０００Å厚
の第２の絶縁膜（層間絶縁膜）１３である酸化膜がＣＶ
Ｄ法によって形成してある。抵抗素子１２であるノンド
ープ多結晶シリコン層上とチップ周辺部を囲む外部接続
領域２上の第２の絶縁膜１３を部分的にフォトエッチン
グにより除去してコンタクト窓（空き領域）を形成し、
アルミ等の金属配線１４によってチップ周辺部を囲む外
部接続領域２と抵抗素子１２とを接続している。Further, an oxide film as a second insulating film (interlayer insulating film) 13 having a thickness of about 9000 mm is
It is formed by the D method. The second insulating film 13 on the non-doped polycrystalline silicon layer serving as the resistance element 12 and the external connection region 2 surrounding the periphery of the chip is partially removed by photoetching to form a contact window (vacant region);
The external connection region 2 surrounding the periphery of the chip and the resistance element 12 are connected by a metal wiring 14 such as aluminum.

【００３２】なお、外部接続領域２上は、全周にわたっ
て第２の絶縁膜１３が除去されてスクライブ用の空き領
域が形成されており、外部接続領域２がウェハをチップ
状に分割する際のスクライブライン部と兼ねられてい
る。抵抗素子１２となるノンドープ多結晶シリコン層の
抵抗パターンは、チップ周辺部を囲む外部接続領域２に
金属配線１４によって接続された一端の共通接続部１６
から所望の抵抗値が得られるように抵抗パターンが引き
延ばされて途中でＴ字形に２つに分岐されている。分岐
部１６Ｂから先の抵抗パターンの幅および長さはほぼ等
しくなっており、各他端にはボンディングパッド６ａ，
６ｂを形成するために、ボンディングパッド６ａ，６ｂ
より大きい面積の幅広部１６Ｃ，１６Ｄが設けられてい
て、この幅広部１６Ｃ，１６Ｄには、ボンディングパッ
ド６ａ，６ｂ用の金属電極が設けられている。また、Ｐ
型半導体基板８の裏面には、アルミ等の金属膜からなる
裏面ゲート電極５が設けられており、この裏面ゲート電
極５の形成面は、高濃度となっている。これによって、
Ｐ型半導体基板８の表面のゲート電極用のボンディング
パッドをなくしている。On the external connection region 2, the second insulating film 13 is removed over the entire circumference to form a scribe free region, and the external connection region 2 is used when the wafer is divided into chips. Also serves as the scribe line section. The resistance pattern of the non-doped polycrystalline silicon layer serving as the resistance element 12 includes a common connection portion 16 at one end connected to the external connection region 2 surrounding the periphery of the chip by a metal wiring 14.
The resistance pattern is stretched so as to obtain a desired resistance value, and is branched into two in a T-shape on the way. The width and the length of the resistance pattern ahead of the branch portion 16B are substantially equal, and the bonding pads 6a,
6b, bonding pads 6a, 6b
Wide portions 16C and 16D having a larger area are provided, and the wide portions 16C and 16D are provided with metal electrodes for bonding pads 6a and 6b. Also, P
A back surface gate electrode 5 made of a metal film such as aluminum is provided on the back surface of the mold semiconductor substrate 8, and the surface on which the back surface gate electrode 5 is formed has a high concentration. by this,
The bonding pad for the gate electrode on the surface of the P-type semiconductor substrate 8 is eliminated.

【００３３】内部分離領域１内に形成される接合型電界
効果半導体素子のソース・ドレイン用引き出し配線４
ａ，４ｂと各々のボンディングパッド７ａ，７ｂおよび
抵抗素子１２における抵抗パターンの２つに分岐された
各他端のボンディングパッド６ａ，６ｂは、各々アルミ
等の金属で形成される。また、ボンディングパッド７
ａ，７ｂとボンディングパッド６ａ，６ｂは、内部分離
領域１とチップ周辺部である外部接続領域２の間の第２
の絶縁膜１３上において、チップ周辺部を囲む矩形枠状
外部接続領域２の４個のコーナー部の内側に各々配置さ
れる。Source / drain lead wire 4 of a junction type field effect semiconductor device formed in internal isolation region 1
The bonding pads 6a and 6b at the other ends of the a and 4b, the respective bonding pads 7a and 7b, and the resistance pattern of the resistance element 12, which are branched into two, are each formed of a metal such as aluminum. The bonding pad 7
a, 7b and the bonding pads 6a, 6b are formed between the internal isolation region 1 and the external connection region 2 which is a peripheral portion of the chip.
On the insulating film 13, are disposed inside the four corner portions of the rectangular frame-shaped external connection region 2 surrounding the peripheral portion of the chip.

【００３４】そして、抵抗素子１２の機能領域は、Ｐ型
半導体基板８の中央部付近に配置され、ボンディングパ
ッド６ａ，６ｂはＰ型半導体基板８の一辺の近傍に、共
通接続部１６を挟んで上記一辺の長さ方向に並んだ状態
に配置される。また、内部分離領域１もＰ型半導体基板
８の中央部付近に配置され、ボンディングパッド７ａ，
７ｂはＰ型半導体基板８の反対側の一辺の近傍に、その
一辺の長さ方向に並んだ状態に配置される。The functional region of the resistance element 12 is arranged near the center of the P-type semiconductor substrate 8, and the bonding pads 6 a and 6 b are arranged near one side of the P-type semiconductor substrate 8 with the common connection portion 16 interposed therebetween. They are arranged in a state where they are arranged in the length direction of the one side. Further, the internal isolation region 1 is also disposed near the center of the P-type semiconductor substrate 8, and the bonding pads 7a,
7b is arranged near one side on the opposite side of the P-type semiconductor substrate 8 so as to be arranged in the length direction of the one side.

【００３５】この実施の形態の構成では、接合型電界効
果半導体素子のボンディングパッド７ａ，７ｂの直下に
第１の絶縁膜１１と第２の絶縁膜１３を合わせた約１．
５μｍの厚い絶縁膜があり、かつ絶縁膜１１，１３の直
下にＰ型半導体基板８と逆導電型のＮ型エピタキシャル
層１０があるためボンディングパッドおよびＰ型半導体
基板８間の配線容量は低減する。結果として、接合型電
界効果半導体素子の入力容量の低減に寄与する。In the structure of this embodiment, the first insulating film 11 and the second insulating film 13 are combined just below the bonding pads 7a and 7b of the junction field effect semiconductor device.
Since a 5 μm thick insulating film is provided, and a P-type semiconductor substrate 8 and an N-type epitaxial layer 10 of the opposite conductivity type are provided immediately below the insulating films 11 and 13, the wiring capacitance between the bonding pad and the P-type semiconductor substrate 8 is reduced. . As a result, it contributes to the reduction of the input capacitance of the junction field effect semiconductor device.

【００３６】また、接合型電界効果半導体素子のＰＮ接
合面積も、内部分離領域１およびゲート領域３と、接合
型電界効果半導体素子の機能領域内のＮ型エピタキシャ
ル層１５との接触面積のみであるので、最小面積です
み、この点でも、接合型電界効果半導体素子の入力容量
の低減に寄与する。また、ボンディングパッド７ａ，７
ｂ，６ａ，６ｂの直下にＰ型エピタキシャル層９とＮ型
エピタキシャル層１０によるＰＮ接合を有しているの
で、ワイヤボンディング時の衝撃に起因するリークを防
ぐことができる。The PN junction area of the junction field effect semiconductor device is also only the contact area between the internal isolation region 1 and the gate region 3 and the N-type epitaxial layer 15 in the functional region of the junction field effect semiconductor device. Therefore, the minimum area is sufficient, and this also contributes to the reduction of the input capacitance of the junction field effect semiconductor device. The bonding pads 7a, 7
Since the PN junction of the P-type epitaxial layer 9 and the N-type epitaxial layer 10 is provided immediately below b, 6a, and 6b, it is possible to prevent a leak caused by an impact during wire bonding.

【００３７】さらに、抵抗素子１２用として２個のボン
ディングパッド６ａ，６ｂがあるため、プローブ針をあ
てることで、接合型電界効果半導体素子を通さずに抵抗
素子１２のみの抵抗値を容易に測定でき、なおかつ抵抗
素子１２の膜の不良解析も容易にできる。図３および図
４に本発明の実施の形態における半導体チップを半導体
素子載置部（リードフレーム）に載置して外部リードに
結線した半導体装置を示す。Further, since there are two bonding pads 6a and 6b for the resistance element 12, the resistance value of only the resistance element 12 can be easily measured by applying a probe needle without passing through the junction type field effect semiconductor element. In addition, the failure analysis of the film of the resistance element 12 can be easily performed. 3 and 4 show a semiconductor device in which a semiconductor chip according to an embodiment of the present invention is mounted on a semiconductor element mounting portion (lead frame) and connected to external leads.

【００３８】図１および図２で示された半導体チップ１
００には、その裏面に金属膜等を設けることによりゲー
ト電極５が形成されている。そして、半導体チップ１０
０を半導体素子載置部（コム）１７を有したリードフレ
ームにダイスボンドすることにより、接合型電界効果半
導体素子の裏面ゲート電極５がゲート用外部リード１９
ａと接続され、同時に抵抗素子１２の一端（共通接続部
１６）が金属電極１４および外部接続部２とＰ型半導体
基板８を介してゲート用外部リード１９ａと接続され
る。なお、上記のゲート用外部リード１９ａの他に、こ
のゲート用外部リード１９ａと平行な方向に、半導体素
子載置部１７の各コーナー部付近から３本の独立した外
部リード１９ｂ，１９ｃ，１９ｄが外方へ延出されてい
る。Semiconductor chip 1 shown in FIGS. 1 and 2
In 00, a gate electrode 5 is formed by providing a metal film or the like on the back surface. Then, the semiconductor chip 10
0 is die-bonded to a lead frame having a semiconductor element mounting portion (comb) 17, so that the back gate electrode 5 of the junction type field effect semiconductor element is connected to the gate external lead 19.
a, and at the same time, one end (common connection portion 16) of the resistance element 12 is connected to the gate external lead 19a via the metal electrode 14, the external connection portion 2, and the P-type semiconductor substrate 8. In addition to the above-described gate external lead 19a, three independent external leads 19b, 19c, and 19d are provided in the direction parallel to the gate external lead 19a from the vicinity of each corner of the semiconductor element mounting portion 17. It is extended outward.

【００３９】そして、抵抗素子１２の２個のボンディン
グパッド６ａ，６ｂのほぼ中心点を結んだ線の中点の垂
線上に抵抗用外部リード１９ｂの基端部が配置されるよ
うに、半導体チップ１００は半導体素子載置部１７に位
置決めされる。つまり、外部リード１９ｂが延出された
半導体素子載置部１７のコーナー部に一辺（ボンディン
グパッド６ａ，６ｂが近接した辺）が対向する状態に半
導体素子載置部１７に半導体チップ１００が配置され
る。Then, the semiconductor chip is arranged such that the base end of the external lead 19b for resistance is arranged on a perpendicular line to a middle point of a line connecting substantially the center points of the two bonding pads 6a and 6b of the resistance element 12. 100 is positioned on the semiconductor element mounting portion 17. That is, the semiconductor chip 100 is arranged on the semiconductor element mounting portion 17 such that one side (the side close to the bonding pads 6a and 6b) faces the corner of the semiconductor element mounting portion 17 from which the external leads 19b extend. You.

【００４０】つぎに、抵抗素子１２の２カ所のボンディ
ングパッド６ａ，６ｂから外部リード１９ｂとの間が、
ワイヤ１８ａ，１８ｂを介して共通接続される。この場
合、２本のワイヤ１８ａ，１８ｂがほぼ同じ長さにな
る。また、接合型電界効果半導体素子のソース・ドレイ
ンのボンディングパッド７ａ，７ｂは各々ワイヤ１８
ｃ，１８ｄによって外部リード１９ｃ，１９ｄにそれぞ
れ接続される。Next, the distance between the two bonding pads 6a and 6b of the resistance element 12 and the external lead 19b is
They are commonly connected via wires 18a and 18b. In this case, the two wires 18a and 18b have substantially the same length. The source / drain bonding pads 7a and 7b of the junction type field effect semiconductor element are connected to wires 18 respectively.
c and 18d are connected to the external leads 19c and 19d, respectively.

【００４１】なお、図４はワイヤ１８ｂを省いた状態を
示している。以上のように構成された半導体装置では抵
抗素子１２の２つに分岐されたパターン幅およびパター
ン長ならびに外部リード１９ｂに接続される２本のワイ
ヤ１８ａ，１８ｂの長さがほぼ等しいので、図４のよう
に抵抗素子１２の片方のボンディングパッド６ａについ
てのみ外部リード１９ｂとワイヤ１８ａで接続する場合
の抵抗値の約２分の１になる。FIG. 4 shows a state in which the wire 18b is omitted. In the semiconductor device configured as described above, the pattern width and pattern length of the two branches of the resistance element 12 and the lengths of the two wires 18a and 18b connected to the external lead 19b are substantially equal. As described above, only one of the bonding pads 6a of the resistance element 12 has a resistance value which is about one half of the resistance value when the connection is made to the external lead 19b and the wire 18a.

【００４２】約２分の１と記載しているのは、図１の抵
抗素子１２の共通接続部１６Ａから分岐部１６Ｂまでの
部分にも、ある程度の抵抗値が存在し、正確に２分の１
にならないからである。なお、共通接続部１６Ａから分
岐部１６Ｂまでの部分は、無くす場合もあり、他の部分
より太くする場合もあり、その抵抗値は分岐部１６Ｂか
ら先の部分より抵抗値を小さくすることが可能である。The reason that the half is described as being about half is that the resistance element 12 in FIG. 1 also has a certain resistance value in the portion from the common connection portion 16A to the branch portion 16B, and it 1
Because it does not become. The portion from the common connection portion 16A to the branch portion 16B may be omitted or thicker than the other portions, and the resistance value may be smaller than that of the portion beyond the branch portion 16B. It is.

【００４３】接合型電界効果半導体素子に共通接続する
抵抗素子の抵抗パターンの分岐本数をＮ本（Ｎは３以上
の整数）に増やし、２〜Ｎ個のボンディングパッドから
同じ長さのワイヤを介して外部リードに共通接続するこ
とによりパターン変更することなく抵抗値の異なる半導
体装置を得ることができる。また、本発明の実施の形態
では、半導体チップと抵抗用外部リード１９ｂの配置が
変わらず、半導体チップの半導体素子載置部１７へのダ
イスボンドが同じであり、ワイヤボンドの本数を変える
だけで容易に抵抗値を変えることができることから、量
産性に優れるという利点もある。The number of branches of the resistance pattern of the resistance element commonly connected to the junction type field effect semiconductor element is increased to N (N is an integer of 3 or more), and two to N bonding pads are connected to each other through a wire of the same length. Thus, a semiconductor device having a different resistance value can be obtained without changing the pattern by commonly connecting the external leads. In the embodiment of the present invention, the arrangement of the semiconductor chip and the external lead 19b for resistance does not change, the dice bond to the semiconductor element mounting portion 17 of the semiconductor chip is the same, and only the number of wire bonds is changed. Since the resistance value can be easily changed, there is also an advantage that mass productivity is excellent.

【００４４】以上のように本発明の半導体装置は、１つ
のＰ型半導体基板８上に入力容量の低い接合型電界効果
半導体素子と、高抵抗の抵抗素子１２とが一体形成され
た半導体チップからなり、接合型電界効果半導体素子を
囲む内部分離領域１とチップ周辺の外部接続領域２の間
のＰ型半導体基板８とＮ型エピタキシャル層１０上に十
分厚い絶縁膜１１，１３を介してボンディングパッド６
ａ，６ｂ，７ａ，７ｂと抵抗素子１２が形成され、抵抗
素子１２は金属配線１４で外部接続領域２に接続され外
部接続領域２からＰ型エピタキシャル層９およびＰ型半
導体基板８を介して内部分離領域１に接続されている半
導体チップである。そして、接合型電界効果半導体素子
のソース／ドレイン電極は、ワイヤ１８ｃ，１８ｄを介
して外部リード１９ｃ，１９ｄに接続され、半導体チッ
プの裏面ゲート電極がチップ載置部に直接接続されるこ
とにより外部リード１９ａに接続され、抵抗素子の外部
リード１９ｂには複数個の抵抗素子のボンディングパッ
ド６ａ，６ｂの少なくとも１個からほぼ同じ長さのワイ
ヤ長のワイヤ１８ａ，１８ｂで共通結線される。以上の
構成により、入力容量が低く、かつ一つの半導体チップ
の抵抗用ワイヤ数を変えることで、半導体素子の入力イ
ンピーダンスのバランスを崩すことなく様々な抵抗値を
もつ半導体装置を実現できるものである。As described above, the semiconductor device of the present invention comprises a semiconductor chip in which a junction type field effect semiconductor element having a low input capacitance and a high resistance element 12 are integrally formed on one P-type semiconductor substrate 8. The bonding pad is provided on the P-type semiconductor substrate 8 and the N-type epitaxial layer 10 between the internal isolation region 1 surrounding the junction type field effect semiconductor element and the external connection region 2 around the chip via sufficiently thick insulating films 11 and 13. 6
a, 6b, 7a, 7b and a resistance element 12 are formed, and the resistance element 12 is connected to the external connection region 2 by a metal wiring 14, and is internally connected from the external connection region 2 via a P-type epitaxial layer 9 and a P-type semiconductor substrate 8. The semiconductor chip is connected to the isolation region 1. The source / drain electrodes of the junction field-effect semiconductor element are connected to external leads 19c and 19d via wires 18c and 18d, and the back gate electrode of the semiconductor chip is directly connected to the chip mounting portion to allow external connection. The lead 19a is connected to the external lead 19b of the resistive element, and at least one of the bonding pads 6a and 6b of the resistive element is commonly connected by wires 18a and 18b having substantially the same wire length. With the above configuration, by changing the number of resistance wires of one semiconductor chip with a low input capacitance, it is possible to realize a semiconductor device having various resistance values without breaking the input impedance balance of the semiconductor element. .

【００４５】[0045]

【発明の効果】本発明の請求項１記載の半導体装置によ
れば、逆導電型層を内部分離領域で内側領域と外側領域
とに分離し、内側領域のみを接合型電界効果半導体素子
の形成領域とし、また、回路素子を接合型電界効果半導
体素子が形成されていない外側領域上に配置したので、
接合型電界効果半導体素子の入力容量を小さくできる。According to the semiconductor device of the first aspect of the present invention, the reverse conductivity type layer is separated into the inner region and the outer region by the inner separation region, and only the inner region is formed as the junction type field effect semiconductor element. Region, and the circuit element is arranged on the outer region where the junction type field effect semiconductor element is not formed,
The input capacitance of the junction field effect semiconductor device can be reduced.

【００４６】本発明の請求項２〜５記載の半導体装置に
よれば、請求項１と同様の効果を奏する。本発明の請求
項６記載の半導体装置によれば、請求項１と同様の効果
を奏する他、回路素子の機能領域の共通接続部側と反対
側が少なくとも２つ以上に分岐され、分岐された機能領
域の他端側の各々にボンディングパッドが設けられてい
るので、ボンディングパッドを用いて回路素子の検査を
単体の接合型半導体素子を経由せずに行うことができ、
回路素子の特性を確実にかつ容易に測定することがで
き、また、分岐した複数の他端の一部を使用するか、全
部を使用するかによって、回路素子の特性を容易に調整
することができる。According to the semiconductor device of the second to fifth aspects of the present invention, the same effect as that of the first aspect is obtained. According to the semiconductor device of the sixth aspect of the present invention, in addition to the same effects as those of the first aspect, at least two sides of the functional region of the circuit element opposite to the common connection portion side are branched, and the branched function is provided. Since a bonding pad is provided on each of the other end sides of the region, a circuit element can be inspected using the bonding pad without passing through a single junction type semiconductor element,
The characteristics of the circuit element can be measured reliably and easily, and the characteristics of the circuit element can be easily adjusted depending on whether some or all of the other ends of the branches are used. it can.

【００４７】本発明の請求項７，８記載の半導体装置に
よれば、請求項１の同様の効果を奏する。本発明の請求
項９記載の半導体装置によれば、請求項１と同様の効果
を奏する他、第１の絶縁膜の上に回路素子が設けられて
いるので、不純物が回路素子に拡散することがなく、そ
の特性の変動を防止することができる。According to the semiconductor device according to the seventh and eighth aspects of the present invention, the same effect as that of the first aspect is obtained. According to the semiconductor device of the ninth aspect of the present invention, the same effect as that of the first aspect is obtained, and since the circuit element is provided on the first insulating film, the impurity is diffused into the circuit element. Therefore, it is possible to prevent the characteristic from fluctuating.

【００４８】本発明の請求項１０，１１記載の半導体装
置によれば、請求項１と同様の効果を奏する。本発明の
請求項１２記載の半導体装置によれば、請求項１と同様
の効果を奏する他、回路素子の接続のためのワイヤを省
くことができる。本発明の請求項１３記載の半導体装置
によれば、請求項１と同様の効果を奏する他、機能素子
の製造上の部分的特性を電界効果型半導体素子の影響を
受けずに計測することができる。According to the semiconductor device according to the tenth and eleventh aspects of the present invention, the same effects as those of the first aspect can be obtained. According to the semiconductor device of the twelfth aspect of the present invention, the same effects as those of the first aspect can be obtained, and wires for connecting circuit elements can be omitted. According to the semiconductor device of the thirteenth aspect of the present invention, in addition to the same effect as the first aspect, it is also possible to measure a partial characteristic in manufacturing a functional element without being affected by a field effect type semiconductor element. it can.

【００４９】本発明の請求項１４記載の半導体装置によ
れば、２個以上のボンディングパッドと外部リードの基
端部とを各々ほぼ均等な長さの２本以上のワイヤで接続
するので、２個以上のボンディングパッドと外部リード
の基端部との間の配線抵抗をほぼ同じ値にすることがで
きる。According to the semiconductor device of the fourteenth aspect of the present invention, two or more bonding pads and the base end of the external lead are connected by two or more wires having substantially equal lengths. The wiring resistance between the one or more bonding pads and the base end of the external lead can be made substantially the same value.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の実施の形態の半導体装置の半導体チッ
プ表面を示す平面図である。FIG. 1 is a plan view showing a semiconductor chip surface of a semiconductor device according to an embodiment of the present invention.

【図２】図１のＡ−Ａ’線の断面図である。FIG. 2 is a sectional view taken along line A-A 'of FIG.

【図３】本発明の実施の形態の半導体装置のワイヤ接続
状態を示す概略図である。FIG. 3 is a schematic diagram illustrating a wire connection state of the semiconductor device according to the embodiment of the present invention;

【図４】本発明の実施の形態の半導体装置のワイヤ接続
状態を示す概略図である。FIG. 4 is a schematic diagram illustrating a wire connection state of the semiconductor device according to the embodiment of the present invention;

【図５】第１の絶縁膜の形状を示す平面図である。FIG. 5 is a plan view showing a shape of a first insulating film.

【図６】赤外線センサ回路の構成を示す回路図である。FIG. 6 is a circuit diagram illustrating a configuration of an infrared sensor circuit.

【図７】従来の半導体装置の半導体チップの断面図であ
る。FIG. 7 is a sectional view of a semiconductor chip of a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

１ 内部分離領域 ２ 外部接続領域 ３ ゲート領域 ４ａ，４ｂ ソース・ドレイン用引き出し配線 ５ 裏面ゲート電極 ６ａ，６ｂ ボンディングパッド ７ａ，７ｂ ボンディングパッド ８ Ｐ型半導体基板 ９ Ｐ型エピタキシャル層 １０ Ｎ型エピタキシャル層 １１ 第１の絶縁膜 １２ 抵抗素子 １３ 第２の絶縁膜 １４ 金属配線 １５ Ｎ型エピタキシャル層 １６Ａ 共通接続部 １６Ｂ 分岐部 １６Ｃ，１６Ｄ 幅広部 １７ 半導体素子載置部 １８ａ〜１８ｄ ワイヤ １９ａ〜１９ｄ 外部リード DESCRIPTION OF SYMBOLS 1 Internal isolation region 2 External connection region 3 Gate region 4a, 4b Lead-out wiring for source / drain 5 Back gate electrode 6a, 6b Bonding pad 7a, 7b Bonding pad 8 P-type semiconductor substrate 9 P-type epitaxial layer 10 N-type epitaxial layer 11 First insulating film 12 Resistive element 13 Second insulating film 14 Metal wiring 15 N-type epitaxial layer 16A Common connection portion 16B Branch portion 16C, 16D Wide portion 17 Semiconductor element mounting portions 18a to 18d Wires 19a to 19d External leads

【手続補正書】[Procedure amendment]

【提出日】平成１１年９月３日（１９９９．９．３）[Submission date] September 3, 1999 (1999.9.3)

【手続補正１】[Procedure amendment 1]

【補正対象書類名】明細書[Document name to be amended] Statement

【補正対象項目名】全文[Correction target item name] Full text

【補正方法】変更[Correction method] Change

【補正内容】[Correction contents]

【書類名】 明細書[Document Name] Statement

【発明の名称】 半導体装置[Title of the Invention] Semiconductor device

【特許請求の範囲】[Claims]

【請求項３】 回路素子が機能領域と、この機能領域の
一端に設けた共通接続部と、前記機能領域の他端に設け
たボンディングパッド部とからなり、前記共通接続部が
第２の分離領域に接続されていることを特徴とする請求
項１記載の半導体装置。 3. A circuit element comprising: a functional region; a common connecting portion provided at one end of the functional region; and a bonding pad portion provided at the other end of the functional region.
2. The semiconductor device according to claim 1, wherein the semiconductor device is connected to the second isolation region.

【請求項４】 回路素子の共通接続部とボンディングパ
ッド部とが半導体基板の端部側に設けられ、前記回路素
子の機能領域が半導体基板の内部側に設けられているこ
とを特徴とする請求項３記載の半導体装置。 4. The semiconductor device according to claim 1, wherein a common connection portion and a bonding pad portion of the circuit element are provided on an end of the semiconductor substrate, and a functional region of the circuit element is provided on an inner side of the semiconductor substrate. Item 4. The semiconductor device according to item 3 .

【請求項５】 回路素子の機能領域の共通接続部側と反
対側が少なくとも２つ以上に分岐され、前記分岐された
機能領域の他端側の各々にボンディングパッドが設けら
れていることを特徴とする請求項１または４記載の半導
体装置。 5. The circuit element according to claim 1, wherein a side opposite to the common connection portion side of the functional region of the circuit element is branched into at least two or more, and a bonding pad is provided on each of the other end sides of the branched functional region. the semiconductor device according to claim 1 or 4, wherein to.

【請求項６】 一導電型の第１の分離領域によって囲ま
れた逆導電型の第１の島領域内に形成された一導電型の
ゲート領域が、前記第１の島領域をソース領域とドレイ
ン領域とに分断するように両端が前記第１の分離領域と
接する状態に設けられたことを特徴とする請求項１記載
の半導体装置。 6. The semiconductor device is surrounded by a first isolation region of one conductivity type.
Of one conductivity type formed in the first island region of the opposite conductivity type.
2. The semiconductor device according to claim 1, wherein both ends of the gate region are in contact with the first isolation region so as to divide the first island region into a source region and a drain region. 3.

【請求項７】 回路素子が薄膜抵抗であり、狭幅線状領
域を実質的な機能領域とし、少なくとも前記狭幅線状領
域の一端部にボンディングパッドの外形よりも大きい幅
広領域を有し、前記幅広領域上に前記ボンディングパッ
ド用の金属電極を設けたことを特徴とする請求項１記載
の半導体装置。 7. The circuit element is a thin film resistor, the narrow linear region is a substantial functional region, and at least one end of the narrow linear region has a wide region larger than an outer shape of a bonding pad. 2. The semiconductor device according to claim 1, wherein a metal electrode for the bonding pad is provided on the wide area.

【請求項８】 回路素子が第１の絶縁膜より厚い第２の
絶縁膜で覆われ、前記第２の絶縁膜の開き領域を通して
前記回路素子に接続される金属電極が設けられ、前記金
属電極を介して前記回路素子が外部接続領域と接続され
ることを特徴とする請求項１記載の半導体装置。 8. A circuit element is covered with a first insulating film thicker second insulating film, a metal electrode connected to the circuit element through the region of opening of the second insulating film is provided, the metal electrode the semiconductor device according to claim 1, characterized in that said circuit element is connected to an external connection region via.

【請求項９】 第１の分離領域上および前記第１の分離
領域に囲まれた第１の島領域上が第２の絶縁膜で保護さ
れ、第２の分離領域がスクライブライン部と兼ねられ、
前記第２の分離領域にスクライブ用の前記第２の絶縁膜
の開き領域が設けられていることを特徴とする請求項８
記載の半導体装置。 9. The first isolation region and the first isolation
The first island region surrounded by the region is protected by the second insulating film, and the second isolation region also serves as a scribe line portion,
Claim 8, characterized in that the opening area of the second insulating film for scribing is provided in the second separation zone
13. The semiconductor device according to claim 1.

【請求項１０】 分岐された機能領域の他端側の各々の
少なくとも２個以上のボンディングパッド間を測定する
ことにより前記機能領域の製造上の部分的特性を計測可
能としたことを特徴とする請求項５記載の半導体装置。 [Claim 1 0] and characterized in that a measurable partial characteristics of the manufacturing of the functional area by measuring between at least two or more bonding pads of each of the other end of the branch functional area 6. The semiconductor device according to claim 5 , wherein:

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、接合型電界効果半
導体素子（ＪＦＥＴ）と他の回路素子を複合一体化した
半導体装置に関するものである。特に、得られる電荷量
が微少で内部インピーダンスの高いセンサ（例：赤外線
センサである焦電センサ等）の信号検出用半導体装置
で、他の回路素子が薄膜で中でも高抵抗であるものに関
する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a junction field effect semiconductor device (JFET) and another circuit device are combined and integrated. In particular, the present invention relates to a semiconductor device for detecting a signal of a sensor that obtains a small amount of electric charge and has a high internal impedance (eg, a pyroelectric sensor that is an infrared sensor), in which other circuit elements are thin films and have high resistance among them.

【０００２】[0002]

【従来の技術】従来、赤外線検出装置は、赤外線センサ
等で得られる微少な電荷を検出増幅することによって、
赤外線検出を行うものである。一例としては、特開平６
−１８８３７０号公報に開示されているような赤外線セ
ンサ回路２０を有した赤外線検出装置がある。2. Description of the Related Art Conventionally, an infrared detecting device detects and amplifies minute electric charges obtained by an infrared sensor or the like, thereby
It performs infrared detection. One example is disclosed in
There is an infrared detection device having an infrared sensor circuit 20 as disclosed in Japanese Patent Publication No. 188370.

【０００３】その回路構成は、図４に示すように、赤外
線センサ２１、接合型電界効果半導体素子（トランジス
タ）２３、抵抗２２、抵抗２４よりなる。２５は出力端
子、２６は電源端子、２７は接地端子である。赤外線セ
ンサ回路２０は、赤外線が赤外線センサ２１に当たると
センサ表面に電荷が発生し、この電荷が接合型電界効果
半導体素子２３のゲート電極に流れ、接合型電界効果半
導体素子２３をオン状態にし、その結果、接合型電界効
果半導体素子２３に電流が流れ、出力端子２５に出力電
圧が検出される。As shown in FIG. 4 , the circuit configuration comprises an infrared sensor 21, a junction type field effect semiconductor element (transistor) 23, a resistor 22, and a resistor 24. 25 is an output terminal, 26 is a power supply terminal, and 27 is a ground terminal. The infrared sensor circuit 20 generates an electric charge on the sensor surface when the infrared light strikes the infrared sensor 21, the electric charge flows to the gate electrode of the junction field effect semiconductor element 23, and turns on the junction field effect semiconductor element 23. As a result, a current flows through the junction type field effect semiconductor element 23, and an output voltage is detected at the output terminal 25.

【０００４】通常、赤外線センサ回路２０は、赤外線セ
ンサ２１と接合型電界効果半導体素子２３と抵抗体２２
（例えばセラミックやタンタル化合物等）と抵抗器２４
との各単品素子等よりなるハイブリッド部品として製品
化されている。Normally, the infrared sensor circuit 20 comprises an infrared sensor 21, a junction type field effect semiconductor element 23 and a resistor 22.
(For example, ceramic or tantalum compound) and the resistor 24
And has been commercialized as a hybrid component composed of individual components and the like.

【０００５】しかしながら、赤外線センサ２１が焦電素
子のように、内部インピーダンスが非常に大きく（十Ｇ
Ω〜数十ＧΩ）、得られる電荷量も少ない場合、接合型
電界効果半導体素子２３のインピーダンスと焦電素子と
のインピーダンスのマッチングを図るためには、極めて
抵抗値の高い抵抗体２２を赤外線センサ２１と接合型電
界効果半導体素子２３の間に並列に挿入する必要があ
る。また、高周波ノイズを除去して微少電荷を増幅し、
安定した出力を得るためには、低入力容量の接合型電界
効果半導体素子２３で高周波ノイズを除去することが必
要になる。However, the infrared sensor 21 has a very large internal impedance (10 G) like a pyroelectric element.
Ω to several tens GΩ), and when the amount of charge obtained is small, in order to match the impedance of the junction field-effect semiconductor element 23 with the impedance of the pyroelectric element, the resistor 22 having an extremely high resistance value is connected to the infrared sensor It is necessary to insert in parallel between 21 and the junction type field effect semiconductor element 23. Also, remove high frequency noise and amplify minute charges,
In order to obtain a stable output, it is necessary to remove high-frequency noise with the junction type field effect semiconductor element 23 having a low input capacitance.

【０００６】また、一つの半導体チップ上に抵抗体と接
合型電界効果半導体素子を形成した焦電型赤外線センサ
の半導体装置も提供されている。この半導体装置につい
ては実開平６−３９７６７号公報に開示されている。図
５に上記半導体装置の断面図を示す。この半導体装置
は、図５に示すように、Ｐ型半導体（シリコン）基板３
１上にチャンネルとなるＮ型領域３２を形成し、このＮ
型領域３２上に内側Ｐ型ゲート領域３３を形成してい
る。この場合、Ｎ型領域３２と、Ｎ型領域３２に囲まれ
た内側Ｐ型ゲート領域３３および外側Ｐ型ゲート領域、
つまりＰ型半導体基板３１で接合型電界効果半導体素子
３８が構成されており、内側Ｐ型ゲート領域３３と外側
Ｐ型ゲート領域であるＰ型半導体基板３１とは電気的に
接続されている。Further, there has been provided a semiconductor device of a pyroelectric infrared sensor in which a resistor and a junction type field effect semiconductor element are formed on one semiconductor chip. This semiconductor device is disclosed in Japanese Utility Model Laid-Open No. 6-39767. Figure
FIG. 5 shows a sectional view of the semiconductor device. The semiconductor device, as shown in FIG. 5, P-type semiconductor (silicon) substrate 3
An N-type region 32 serving as a channel is formed on
An inner P-type gate region 33 is formed on the mold region 32. In this case, the N-type region 32, the inner P-type gate region 33 and the outer P-type gate region surrounded by the N-type region 32,
In other words, the junction type field effect semiconductor element 38 is constituted by the P-type semiconductor substrate 31, and the inner P-type gate region 33 and the P-type semiconductor substrate 31, which is the outer P-type gate region, are electrically connected.

【０００７】また、Ｐ型半導体基板３１表面上には、金
属膜等の抵抗素子３４が形成されている。この他に、Ｐ
型半導体基板３１表面上には、金属配線からなるドレイ
ン電極３５とソース電極３６と出力電極３７が形成され
ていて、ソース電極３６は延長されて抵抗素子３４の一
端にも接続されていて、接合型電界効果半導体素子３８
のソースと抵抗素子３４の一端が電気的に接続されてい
る。Ｐ型半導体基板３１の裏面には、金属膜等からなる
裏面ゲート電極３９が形成されている。On the surface of the P-type semiconductor substrate 31, a resistance element 34 such as a metal film is formed. In addition, P
On the surface of the mold semiconductor substrate 31, a drain electrode 35, a source electrode 36, and an output electrode 37 made of metal wiring are formed, and the source electrode 36 is extended and connected to one end of the resistance element 34. Type field effect semiconductor device 38
And one end of the resistance element 34 are electrically connected. On the back surface of the P-type semiconductor substrate 31, a back gate electrode 39 made of a metal film or the like is formed.

【０００８】この場合、接合型電界効果半導体素子３８
の入力容量は、接合型電界効果半導体素子３８が形成さ
れている領域のＰＮ接合容量と、配線およびボンディン
グパッド直下の容量とで決まる。通常、入力容量を低く
するためには、半導体チップの表面にゲート用ボンディ
ングパッドを設けず、外側Ｐ型ゲート領域となるＰ型半
導体基板３１の裏面ゲートに金属膜等で裏面ゲート電極
３９を設け、半導体チップを半導体素子載置部を有した
リードフレームにダイスボンドすることによりゲート用
外部リードと裏面ゲート電極３９を接続している。In this case, the junction type field effect semiconductor device 38
Is determined by the PN junction capacitance in the region where the junction field effect semiconductor element 38 is formed and the capacitance immediately below the wiring and the bonding pad. Normally, in order to lower the input capacitance, a bonding pad for a gate is not provided on the surface of the semiconductor chip, and a back gate electrode 39 made of a metal film or the like is provided on the back gate of the P-type semiconductor substrate 31 serving as an outer P-type gate region. The external lead for the gate and the back gate electrode 39 are connected by dice bonding the semiconductor chip to a lead frame having a semiconductor element mounting portion.

【０００９】[0009]

【発明が解決しようとする課題】１チップに接合型電界
効果半導体素子と抵抗素子を形成した従来の半導体装置
においては、接合型電界効果半導体素子の表面に抵抗領
域を設けた構成では、熱等の変動で抵抗領域に半導体基
板からの不純物の拡散等で抵抗値が変動した。In a conventional semiconductor device in which a junction field-effect semiconductor element and a resistance element are formed on one chip, a structure in which a resistance region is provided on the surface of the junction field-effect semiconductor element requires heat or the like. , The resistance value fluctuated due to diffusion of impurities from the semiconductor substrate into the resistance region.

【００１０】また、接合型電界効果半導体素子と抵抗領
域が直接に接するために接合型電界効果半導体素子の入
力容量が大きくなり、焦電型赤外線センサにおいて外部
からの高周波ノイズが十分除去できないため、微少電荷
を増幅するのに安定した出力が得られなかった。 In addition, since the junction field-effect semiconductor element and the resistance region are in direct contact with each other, the input capacitance of the junction field-effect semiconductor element increases, and high-frequency noise from the outside cannot be sufficiently removed in the pyroelectric infrared sensor. A stable output could not be obtained to amplify the minute charge.

【００１１】さらに、抵抗素子の抵抗値を測定するの
に、裏面ゲート−抵抗端子間の抵抗を測定する検査方法
では、接合型電界効果半導体素子を介して検査するの
で、接合型電界効果半導体素子の不良と抵抗部の抵抗値
との区別が困難であった。Further, in the inspection method for measuring the resistance between the back gate and the resistance terminal when measuring the resistance value of the resistance element, the inspection is performed via the junction type field effect semiconductor element. It was difficult to distinguish the failure of the resistor from the resistance value of the resistance portion.

【００１２】本発明の第１の目的は、接合型電界効果半
導体素子の入力容量を小さくすることができる半導体装
置を提供することである。A first object of the present invention is to provide a semiconductor device capable of reducing the input capacitance of a junction type field effect semiconductor element.

【００１３】本発明の第２の目的は、回路素子例えば、
抵抗素子の特性の変動のない半導体装置を提供すること
である。 A second object of the present invention is to provide a circuit element, for example,
An object of the present invention is to provide a semiconductor device in which characteristics of a resistance element do not change.

【００１４】本発明の第３の目的は、回路素子例えば、
抵抗素子の検査を容易に行うことができる半導体装置を
提供することである。A third object of the present invention is to provide a circuit element, for example,
An object of the present invention is to provide a semiconductor device capable of easily inspecting a resistance element.

【００１５】[0015]

【課題を解決するための手段】本発明の半導体装置は、
接合型電界効果半導体素子と薄膜でできた高抵抗素子を
複合一体化した半導体装置であり、以下のように構成す
ることで、上記の目的を達成するものである。According to the present invention, there is provided a semiconductor device comprising:
The present invention is a semiconductor device in which a junction field-effect semiconductor element and a high-resistance element made of a thin film are combined and integrated, and achieves the above object by configuring as follows.

【００１６】請求項１記載の半導体装置は、一導電型の
半導体基板と、この半導体基板上に形成された逆導電型
層と、半導体基板の中央部付近に設けられて逆導電型層
を内側領域と外側領域とに分離する一導電型の第１の分
離領域と、半導体基板の端縁部に設けられて外側領域を
囲む一導電型の第２の分離領域と、第１の分離領域によ
って囲まれた内側領域である第１の島領域と、第１の分
離領域の外側領域であって第２の分離領域に囲まれた第
２の島領域と、第１の島領域内に形成された一導電型の
ゲート領域を有する接合型電界効果半導体素子と、第２
の島領域の主面上に形成された絶縁膜と、絶縁膜上に形
成された回路素子とを備え、回路素子の一方の電極を第
２の分離領域に導電体を介して電気的に接続させること
を特徴とする。According to a first aspect of the present invention, a semiconductor substrate of one conductivity type, a reverse conductivity type layer formed on the semiconductor substrate, and a reverse conductivity type layer provided near a central portion of the semiconductor substrate.
Is separated into an inner region and an outer region.
A separated region and an outer region provided at an edge of the semiconductor substrate.
An enclosing second isolation region of one conductivity type and a first isolation region;
A first island region, which is an inner region surrounded by
A region outside the separation region and surrounded by the second separation region.
2 island region and one conductivity type formed in the first island region.
A junction field-effect semiconductor device having a gate region;
The insulating film formed on the main surface of the island region of
Circuit element, and one electrode of the circuit element is connected to the
Electrically connecting the two isolation regions via a conductor
It is characterized by .

【００１７】この構成によれば、逆導電型層を第１の分
離領域で内側領域と外側領域とに分離し、第１の分離領
域によって囲まれた内側領域である第１の島領域のみを
接合型電界効果半導体素子の形成領域とし、また、回路
素子を接合型電界効果半導体素子が形成されていない、
第１の分離領域の外側領域であって第２の分離領域に囲
まれた第２の島領域の主面上に形成された絶縁膜上に配
置したので、接合型電界効果半導体素子の入力容量を小
さくできる。According to this configuration, it is separated into an inner and outer regions of the opposite conductivity type layer in the first minute <br/> away region, the first separation territory
Only the first island region, which is the inner region surrounded by the region, is a region for forming the junction field effect semiconductor element, and the circuit element is not formed with the junction field effect semiconductor element .
A region outside the first separation region and surrounded by the second separation region.
Since it is arranged on the insulating film formed on the main surface of the second island region, the input capacitance of the junction type field effect semiconductor device can be reduced.

【００１８】請求項２記載の半導体装置は、請求項１記
載の半導体装置において、半導体基板が矩形のチップ形
状であって、第２の分離領域が半導体基板の周囲端部に
矩形枠状に設けられ、逆導電型層の第２の島領域の主面
上に形成された絶縁膜上に少なくとも１個以上のボンデ
ィングパッドが設けられたことを特徴とする。According to a second aspect of the present invention, in the semiconductor device of the first aspect, the semiconductor substrate has a rectangular chip shape, and the second isolation region is provided in a rectangular frame shape at a peripheral end of the semiconductor substrate. Main surface of the second island region of the opposite conductivity type layer
At least one bonding pad is provided on the insulating film formed thereon.

【００１９】この構成によれば、請求項１と同様に接合
型電界効果半導体素子の入力容量を小さくできる。 According to this configuration , the bonding is performed in the same manner as in the first aspect.
The input capacitance of the field effect semiconductor device can be reduced.

【００２０】請求項３記載の半導体装置は、請求項１記
載の半導体装置において、回路素子が機能領域と、この
機能領域の一端に設けた共通接続部と、機能領域の他端
に設けたボンディングパッド部とからなり、共通接続部
が第２の分離領域に接続されていることを特徴とする。According to a third aspect of the present invention, in the semiconductor device of the first aspect, the circuit element is a functional region, a common connection portion provided at one end of the functional region, and a bonding portion provided at the other end of the functional region. And a pad portion, wherein the common connection portion is connected to the second isolation region.

【００２１】この構成によれば、請求項１と同様の作用
を有する。According to this configuration, the same operation as that of the first aspect is obtained.

【００２２】請求項４記載の半導体装置は、請求項３記
載の半導体装置において、回路素子の共通接続部とボン
ディングパッド部とが半導体基板の端部側に設けられ、
回路素子の機能領域が半導体基板の内部側に設けられて
いることを特徴とする。According to a fourth aspect of the present invention, there is provided the semiconductor device according to the third aspect , wherein the common connection portion of the circuit element and the bonding pad portion are provided on the end side of the semiconductor substrate.
The functional region of the circuit element is provided inside the semiconductor substrate.

【００２３】この構成によれば、請求項１と同様の作用
を有する。According to this configuration, the same operation as that of the first aspect is obtained.

【００２４】請求項５記載の半導体装置は、請求項１ま
たは４記載の半導体装置において、回路素子の機能領域
の共通接続部側と反対側が少なくとも２つ以上に分岐さ
れ、分岐された機能領域の他端側の各々にボンディング
パッドが設けられていることを特徴とする。A semiconductor device according to a fifth aspect of the present invention is the semiconductor device according to the first or fourth aspect , wherein a side of the functional region of the circuit element opposite to the side of the common connection portion is branched into at least two or more, A bonding pad is provided on each of the other ends of the branched functional regions.

【００２５】この構成によれば、請求項１と同様の作用
を有する他、回路素子の機能領域の共通接続部側と反対
側が少なくとも２つ以上に分岐され、分岐された機能領
域の他端側の各々にボンディングパッドが設けられてい
るので、ボンディングパッドを用いて回路素子の検査を
単体の接合型半導体素子を経由せずに行うことができ、
回路素子の特性を確実にかつ容易に測定することができ
る。 According to this configuration, in addition to having the same operation as that of the first aspect, the other side of the functional region of the circuit element opposite to the common connection portion side is branched into at least two or more, and the other end side of the branched functional region. Is provided with a bonding pad, so that a circuit element can be inspected using the bonding pad without passing through a single junction type semiconductor element,
The characteristics of circuit elements can be measured reliably and easily.
You.

【００２６】請求項６記載の半導体装置は、請求項１記
載の半導体装置において、一導電型の第１の分離領域に
よって囲まれた逆導電型の第１の島領域内に形成された
一導電型のゲート領域が、前記第１の島領域をソース領
域とドレイン領域とに分断するように両端が第１の分離
領域と接する状態に設けられたことを特徴とする。According to a sixth aspect of the present invention, there is provided the semiconductor device according to the first aspect, wherein the first isolation region of one conductivity type is provided in the first isolation region.
Therefore, it is formed in the first island region of the opposite conductivity type surrounded by
A gate region of one conductivity type is provided so that both ends are in contact with the first isolation region so as to divide the first island region into a source region and a drain region.

【００２７】この構成によれば、請求項１と同様の作用
を有する。According to this configuration, the same operation as that of the first aspect is provided.

【００２８】請求項７記載の半導体装置は、請求項１記
載の半導体装置において、回路素子が薄膜抵抗であり、
狭幅線状領域を実質的な機能領域とし、少なくとも狭幅
線状領域の一端部にボンディングパッドの外形よりも大
きい幅広領域を有し、幅広領域上にボンディングパッド
用の金属電極を設けたことを特徴とする。According to a seventh aspect of the present invention, in the semiconductor device of the first aspect, the circuit element is a thin film resistor,
The narrow linear region is regarded as a substantial functional region, and at least one end of the narrow linear region has a wide region larger than the outer shape of the bonding pad, and a metal electrode for the bonding pad is provided on the wide region. It is characterized by.

【００２９】この構成によれば、請求項１と同様の作用
を有する。 According to this configuration, the same operation as that of the first aspect is obtained.

【００３０】請求項８記載の半導体装置は、請求項１記
載の半導体装置において、回路素子が第１の絶縁膜より
厚い第２の絶縁膜で覆われ、第２の絶縁膜の開き領域を
通して回路素子に接続される金属電極が設けられ、金属
電極を介して回路素子が第２の島領域と接続されること
を特徴とする。[0030] The semiconductor device according to claim 8, in the semiconductor device according to claim 1, wherein the circuit element is covered with the first insulating film thicker second insulating film, the circuit through the area of opening of the second insulating film A metal electrode connected to the element is provided, and the circuit element is connected to the second island region via the metal electrode.

【００３１】この構成によれば、請求項１と同様の作用
を有する。According to this configuration, the same operation as that of the first aspect is obtained.

【００３２】請求項９記載の半導体装置は、請求項８記
載の半導体装置において、第１の分離領域上および第１
の分離領域に囲まれた第１の島領域上が第２の絶縁膜で
保護され、第２の分離領域がスクライブライン部と兼ね
られ、第２の分離領域にスクライブ用の第２の絶縁膜の
開き領域が設けられていることを特徴とする。According to a ninth aspect of the present invention, there is provided a semiconductor device according to the eighth aspect , wherein the first isolation region and the first isolation region are provided .
Is protected by a second insulating film, the second separating region also serves as a scribe line portion, and a second insulating film for scribing is formed in the second separating region. Is provided.

【００３３】この構成によれば、請求項１と同様の作用
を有する。 According to this configuration, the same operation as that of the first aspect is obtained.

【００３４】請求項１０記載の半導体装置は、請求項５
記載の半導体装置において、分岐された機能領域の他端
側の各々の少なくとも２個以上のボンディングパッド間
を測定することにより機能領域の製造上の部分的特性を
計測可能としたことを特徴とする。The semiconductor device according to claim 1 0, wherein the claim 5
In the semiconductor device described above, it is possible to measure a partial characteristic in manufacturing of the functional region by measuring between at least two or more bonding pads on each of the other end sides of the branched functional region. .

【００３５】この構成によれば、請求項１と同様の作用
を有する他、機能素子の製造上の部分的特性を電界効果
型半導体素子の影響を受けずに計測することができる。 According to this configuration, in addition to having the same function as that of the first aspect, it is possible to measure the partial characteristics of the functional element in the manufacture without being affected by the field effect semiconductor element.

【００３６】[0036]

【発明の実施の形態】本発明の実施の形態の半導体装置
について図面を参照しながら説明する。図１に実施の形
態の半導体装置における半導体チップ表面の平面図を示
し、図２に図１のＡ−Ａ’線断面図を示す。DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a plan view of a semiconductor chip surface in the semiconductor device according to the embodiment, and FIG. 2 is a cross-sectional view taken along line AA ′ of FIG.

【００３７】この半導体装置は、図１および図２に示す
ように、一導電型の半導体基板である１５０μｍ厚の高
不純物濃度のＰ++型半導体基板８上に１０〜１５μｍ厚
のＰ型エピタキシャル層９および逆導電型層である２．
５〜３．５μｍ厚のＮ型エピタキシャル層（逆導電型
層）１０とを設けてある。その上に、第１の絶縁膜１１
としてシリコン酸化膜を熱酸化で約６０００Åに形成し
てある。As shown in FIGS. 1 and 2, this semiconductor device has a P-type epitaxial layer having a thickness of 10 to 15 μm on a P ++ type semiconductor substrate 8 having a high impurity concentration of 150 μm and being a semiconductor substrate of one conductivity type. 1. Layer 9 and reverse conductivity type layer
An N-type epitaxial layer (reverse conductivity type layer) 10 having a thickness of 5 to 3.5 μm is provided. On top of that, the first insulating film 11
A silicon oxide film is formed at about 6000 ° by thermal oxidation.

【００３８】つぎに、接合型電界効果半導体素子機能領
域と周辺領域を分離し、接合型電界効果半導体素子を囲
んで接合型電界効果半導体素子機能領域となる第１の島
を有する矩形枠形のＰ+ 型の第１の分離領域１と矩形の
チップ周辺部を囲む矩形枠形のＰ+ 型の第２の分離領域
２とを、図３に示すように第１の絶縁膜１１に対してフ
ォトエッチングにより第１の分離領域１およびチップ周
辺部を囲む第２の分離領域２に対応する箇所を部分的に
除去するようにパターンニングを行った後、第１の絶縁
膜１１を選択拡散のマスクとして用いることで形成す
る。具体的には、第１の絶縁膜１１をマスクとして選択
拡散を行うことにより、Ｐ型高濃度分離領域である第１
の分離領域１と第２の分離領域２とを第２のＮ型エピタ
キシャル層１０より深く、つまり、底部が半導体基板８
上のＰ型エピタキシャル層９に入り込む状態となるよう
に、約５．５μｍ厚に形成してある。Next, the junction type field effect semiconductor device functional region and the peripheral region are separated, and the first island surrounding the junction type field effect semiconductor device and serving as the junction field effect semiconductor device functional region is provided . As shown in FIG. 3 , a P + type first isolation region 1 having a rectangular frame shape and a P + type second isolation region 2 surrounding a rectangular chip peripheral portion are connected to each other by a first insulating film. 11 is patterned by photoetching so as to partially remove a portion corresponding to the first isolation region 1 and the second isolation region 2 surrounding the periphery of the chip, and then the first insulating film 11 is formed. Is used as a mask for selective diffusion. Specifically, by performing selective diffusion using the first insulating film 11 as a mask, the first type, which is a P-type high-concentration isolation region, is formed .
The isolation region 1 and the second isolation region 2 deeper than the second N-type epitaxial layer 10, that is, the bottom semiconductor substrate 8
It is formed to a thickness of about 5.5 μm so as to enter the upper P-type epitaxial layer 9.

【００３９】つぎに、第１の分離領域１の内側に両端が
第１の分離領域１に重なるＰ+ 型のゲート領域３を第１
の絶縁膜１１をフォトエッチングにより部分的に除去し
てパターンニングした後、それを選択拡散のマスクとし
て用いることにより形成する。具体的には、第１の絶縁
膜１１をマスクとする選択拡散により、第１の分離領域
１の内側の第１の島であるＮ型エピタキシャル層１５内
にＮ型エピタキシャル層１５より浅い深さで約１．５μ
ｍ厚のＰ型高濃度ゲート領域であるゲート領域３を形成
してある。Next, both ends are placed inside the first separation region 1.
The P + type gate region 3 overlapping the first isolation region 1
After the insulating film 11 is partially removed by photoetching and patterned, it is formed by using it as a mask for selective diffusion. Specifically, selective diffusion by, N-type shallower than the epitaxial layer 15 to the N-type epitaxial layer 15 is a first island inside the first isolation region 1 to the first insulating film 11 as a mask About 1.5μ
A gate region 3 which is a P-type high-concentration gate region having a thickness of m is formed.

【００４０】この場合、ゲート領域３が半導体基板８と
同一導電型のＰ型であり、Ｎ型エピタキシャル素子１５
をソース領域とドレイン領域とに分断するように両端が
第１の分離領域１と接する状態に設けられている。In this case, the gate region 3 is of the P-type having the same conductivity type as the semiconductor substrate 8 and the N-type epitaxial element 15 is formed.
At both ends so as to divide the
It is provided in contact with the first isolation region 1.

【００４１】また、第２の分離領域２によって囲まれた
第２の島領域の主面上に形成された第１の絶縁膜１１上
には、比抵抗が１０8 〜１０10Ωｃｍ程度のノンドープ
多結晶シリコン層がＬＰＣＶＤ法によって抵抗素子（機
能素子）１２として形成してある。Further, it is surrounded by the second isolation region 2.
On the first insulating film 11 formed on the main surface of the second island region, a non-doped polycrystalline silicon layer having a specific resistance of about 10 8 to 10 10 Ωcm is formed by a resistive element (functional element) 12 by LPCVD. It is formed as

【００４２】さらに、チップ表面全面に約９０００Å厚
の第２の絶縁膜（層間絶縁膜）１３である酸化膜がＣＶ
Ｄ法によって形成してある。抵抗素子１２であるノンド
ープ多結晶シリコン層上とチップ周辺部を囲む第２の分
離領域２上の第２の絶縁膜１３を部分的にフォトエッチ
ングにより除去してコンタクト窓（空き領域）を形成
し、アルミ等の金属配線１４によってチップ周辺部を囲
む第２の分離領域２と抵抗素子１２とを接続している。Further, an oxide film as a second insulating film (interlayer insulating film) 13 having a thickness of about 9000 mm
It is formed by the D method. A second portion surrounding the non-doped polycrystalline silicon layer serving as the resistance element 12 and the periphery of the chip is provided.
The second insulating film 13 on the separation region 2 is partially removed by photoetching to form a contact window (vacant region), and the second separation region 2 surrounding the chip peripheral portion by a metal wiring 14 of aluminum or the like. The resistance element 12 is connected.

【００４３】なお、第２の分離領域２上は、全周にわた
って第２の絶縁膜１３が除去されてスクライブ用の空き
領域が形成されており、第２の分離領域２がウェハをチ
ップ状に分割する際のスクライブライン部と兼ねられて
いる。On the second isolation region 2, the second insulating film 13 is removed over the entire circumference to form a scribe free region, and the second isolation region 2 divides the wafer into chips. It is also used as a scribe line part when dividing.

【００４４】抵抗素子１２となるノンドープ多結晶シリ
コン層の抵抗パターンは、チップ周辺部を囲む第２の分
離領域２に金属配線１４によって接続された一端の共通
接続部１６から所望の抵抗値が得られるように抵抗パタ
ーンが引き延ばされて途中でＴ字形に２つに分岐されて
いる。分岐部１６Ｂから先の抵抗パターンの幅および長
さはほぼ等しくなっており、各他端にはボンディングパ
ッド６ａ，６ｂを形成するために、ボンディングパッド
６ａ，６ｂより大きい面積の幅広部１６Ｃ，１６Ｄが設
けられていて、この幅広部１６Ｃ，１６Ｄには、ボンデ
ィングパッド６ａ，６ｂ用の金属電極が設けられてい
る。また、Ｐ型半導体基板８の裏面には、アルミ等の金
属膜からなる裏面ゲート電極５が設けられており、この
裏面ゲート電極５の形成面は、高濃度となっている。こ
れによって、Ｐ型半導体基板８の表面のゲート電極用の
ボンディングパッドをなくしている。The resistance pattern of the non-doped polycrystalline silicon layer serving as the resistance element 12 corresponds to the second portion surrounding the chip peripheral portion.
The resistance pattern is extended so that a desired resistance value is obtained from the common connection portion 16 at one end connected to the remote region 2 by the metal wiring 14, and is branched into two in a T-shape on the way. The width and length of the resistance pattern ahead of the branch portion 16B are substantially equal, and the wide portions 16C, 16D having an area larger than the bonding pads 6a, 6b are formed at the other end to form the bonding pads 6a, 6b. The wide portions 16C and 16D are provided with metal electrodes for the bonding pads 6a and 6b. A back gate electrode 5 made of a metal film such as aluminum is provided on the back surface of the P-type semiconductor substrate 8, and the surface on which the back gate electrode 5 is formed has a high concentration. Thus, the bonding pad for the gate electrode on the surface of the P-type semiconductor substrate 8 is eliminated.

【００４５】第１の分離領域１内に形成される接合型電
界効果半導体素子のソース・ドレイン用引き出し配線４
ａ，４ｂと各々のボンディングパッド７ａ，７ｂおよび
抵抗素子１２における抵抗パターンの２つに分岐された
各他端のボンディングパッド６ａ，６ｂは、各々アルミ
等の金属で形成される。また、ボンディングパッド７
ａ，７ｂとボンディングパッド６ａ，６ｂは、第１の分
離領域１とチップ周辺部である第２の分離領域２の間の
第２の絶縁膜１３上において、チップ周辺部を囲む矩形
枠状の第２の分離領域２の４個のコーナー部の内側に各
々配置される。The source and drain draw-out wire of the junction field-effect semiconductor device formed on the first isolation region 1 4
The bonding pads 6a and 6b at the other ends of the a and 4b, the respective bonding pads 7a and 7b, and the resistance pattern of the resistance element 12, which are branched into two, are each formed of a metal such as aluminum. The bonding pad 7
a, 7b and the bonding pad 6a, 6b, in the second insulating film 13 between the second isolation region 2 is a first partial <br/> away region 1 and the chip peripheral portion, the periphery of the chip It is arranged inside each of the four corners of the surrounding rectangular frame-shaped second separation region 2.

【００４６】そして、抵抗素子１２の機能領域は、Ｐ型
半導体基板８の中央部付近に配置され、ボンディングパ
ッド６ａ，６ｂはＰ型半導体基板８の一辺の近傍に、共
通接続部１６を挟んで上記一辺の長さ方向に並んだ状態
に配置される。また、第１の分離領域１もＰ型半導体基
板８の中央部付近に配置され、ボンディングパッド７
ａ，７ｂはＰ型半導体基板８の反対側の一辺の近傍に、
その一辺の長さ方向に並んだ状態に配置される。The functional region of the resistance element 12 is arranged near the center of the P-type semiconductor substrate 8, and the bonding pads 6 a and 6 b are arranged near one side of the P-type semiconductor substrate 8 with the common connection portion 16 interposed therebetween. They are arranged in a state where they are arranged in the length direction of the one side. Further, the first isolation region 1 is also arranged near the center of the P-type semiconductor substrate 8 and the bonding pad 7
a and 7b are near one side on the opposite side of the P-type semiconductor substrate 8,
They are arranged side by side in the length direction of one side.

【００４７】この実施の形態の構成では、接合型電界効
果半導体素子のボンディングパッド７ａ，７ｂの直下に
第１の絶縁膜１１と第２の絶縁膜１３を合わせた約１．
５μｍの厚い絶縁膜があり、かつ絶縁膜１１，１３の直
下にＰ型半導体基板８と逆導電型のＮ型エピタキシャル
層１０があるためボンディングパッドおよびＰ型半導体
基板８間の配線容量は低減する。結果として、接合型電
界効果半導体素子の入力容量の低減に寄与する。In the structure of this embodiment, the first insulating film 11 and the second insulating film 13 are combined immediately below the bonding pads 7a and 7b of the junction type field effect semiconductor element.
Since a 5 μm thick insulating film is provided, and a P-type semiconductor substrate 8 and an N-type epitaxial layer 10 of the opposite conductivity type are provided immediately below the insulating films 11 and 13, the wiring capacitance between the bonding pad and the P-type semiconductor substrate 8 is reduced. . As a result, it contributes to the reduction of the input capacitance of the junction field effect semiconductor device.

【００４８】また、接合型電界効果半導体素子のＰＮ接
合面積も、第１の分離領域１およびゲート領域３と、接
合型電界効果半導体素子の機能領域内のＮ型エピタキシ
ャル層１５との接触面積のみであるので、最小面積です
み、この点でも、接合型電界効果半導体素子の入力容量
の低減に寄与する。The PN junction area of the junction field effect semiconductor device is also limited to the contact area between the first isolation region 1 and the gate region 3 and the N-type epitaxial layer 15 in the functional region of the junction field effect semiconductor device. Therefore, the minimum area is sufficient, and this also contributes to the reduction of the input capacitance of the junction field effect semiconductor device.

【００４９】また、ボンディングパッド７ａ，７ｂ，６
ａ，６ｂの直下にＰ型エピタキシャル層９とＮ型エピタ
キシャル層１０によるＰＮ接合を有しているので、ワイ
ヤボンディング時の衝撃に起因するリークを防ぐことが
できる。The bonding pads 7a, 7b, 6
Since the PN junction of the P-type epitaxial layer 9 and the N-type epitaxial layer 10 is provided immediately below a and 6b, it is possible to prevent leakage due to impact during wire bonding.

【００５０】さらに、抵抗素子１２用として２個のボン
ディングパッド６ａ，６ｂがあるため、プローブ針をあ
てることで、接合型電界効果半導体素子を通さずに抵抗
素子１２のみの抵抗値を容易に測定でき、なおかつ抵抗
素子１２の膜の不良解析も容易にできる。 Further, since there are two bonding pads 6a and 6b for the resistance element 12, the resistance value of only the resistance element 12 can be easily measured by applying a probe needle without passing through the junction type field effect semiconductor element. In addition, the failure analysis of the film of the resistance element 12 can be easily performed.

【００５１】以上のように本発明の半導体装置は、１つ
のＰ型半導体基板８上に入力容量の低い接合型電界効果
半導体素子と、高抵抗の抵抗素子１２とが一体形成され
た半導体チップからなり、接合型電界効果半導体素子を
囲む第１の分離領域１とチップ周辺の第２の分離領域２
の間のＰ型半導体基板８とＮ型エピタキシャル層１０上
に十分厚い絶縁膜１１，１３を介してボンディングパッ
ド６ａ，６ｂ，７ａ，７ｂと抵抗素子１２が形成され、
抵抗素子１２は金属配線１４で第２の分離領域２に接続
され第２の分離接続領域２からＰ型エピタキシャル層９
およびＰ型半導体基板８を介して第１の分離領域１に接
続されている半導体チップである。 As described above, the semiconductor device of the present invention comprises a semiconductor chip in which a junction type field effect semiconductor element having a low input capacitance and a high resistance element 12 are integrally formed on one P-type semiconductor substrate 8. A first isolation region 1 surrounding the junction field effect semiconductor device and a second isolation region 2 around the chip.
The bonding pads 6a, 6b, 7a, 7b and the resistive element 12 are formed on the P-type semiconductor substrate 8 and the N-type epitaxial layer 10 via insulating films 11 and 13 that are sufficiently thick.
The resistance element 12 is connected to the second isolation region 2 by a metal wiring 14 and is connected to the P-type epitaxial layer 9 from the second isolation connection region 2.
And a semiconductor chip connected to the first isolation region 1 via the P-type semiconductor substrate 8.

【００５２】[0052]

【発明の効果】本発明の請求項１記載の半導体装置によ
れば、逆導電型層を第１の分離領域で内側領域と外側領
域とに分離し、第１の分離領域によって囲まれた内側領
域である第１の島領域のみを接合型電界効果半導体素子
の形成領域とし、また、回路素子を接合型電界効果半導
体素子が形成されていない、第１の分離領域の外側領域
であって第２の分離領域に囲まれた第２の島領域の主面
上に形成された絶縁膜上に配置したので、接合型電界効
果半導体素子の入力容量を小さくできる。According to the semiconductor device of the first aspect of the present invention, the reverse conductivity type layer is separated into the inner region and the outer region by the first separation region, and the inner region surrounded by the first separation region is separated. Territory
Only the first island region, which is a region, is a region for forming the junction field effect semiconductor element, and the circuit element is a region outside the first isolation region where the junction field effect semiconductor element is not formed.
And a main surface of a second island region surrounded by the second isolation region
Since it is arranged on the insulating film formed thereon, the input capacitance of the junction field effect semiconductor device can be reduced.

【００５３】本発明の請求項２〜４記載の半導体装置に
よれば、請求項１と同様の効果を奏する。According to the semiconductor device of the second to fourth aspects of the present invention, the same effects as those of the first aspect can be obtained.

【００５４】本発明の請求項５記載の半導体装置によれ
ば、請求項１と同様の効果を奏する他、回路素子の機能
領域の共通接続部側と反対側が少なくとも２つ以上に分
岐され、分岐された機能領域の他端側の各々にボンディ
ングパッドが設けられているので、ボンディングパッド
を用いて回路素子の検査を単体の接合型半導体素子を経
由せずに行うことができ、回路素子の特性を確実にかつ
容易に測定することができ、また、分岐した複数の他端
の一部を使用するか、全部を使用するかによって、回路
素子の特性を容易に調整することができる。According to the semiconductor device of the fifth aspect of the present invention, in addition to the same effect as that of the first aspect, the side opposite to the common connection portion side of the functional region of the circuit element is branched into at least two branches. Since bonding pads are provided on each of the other end sides of the functional region, the inspection of the circuit element can be performed using the bonding pad without passing through a single junction type semiconductor element. Can be measured reliably and easily, and the characteristics of the circuit element can be easily adjusted depending on whether some or all of the branched other ends are used.

【００５５】本発明の請求項６，７記載の半導体装置に
よれば、請求項１の同様の効果を奏する。 According to the semiconductor device of the sixth and seventh aspects of the present invention, the same effect as that of the first aspect is obtained.

【００５６】本発明の請求項８，９記載の半導体装置に
よれば、請求項１と同様の効果を奏する。 According to the semiconductor device according to the eighth and ninth aspects of the present invention, the same effects as those of the first aspect can be obtained.

【００５７】本発明の請求項１０記載の半導体装置によ
れば、請求項１と同様の効果を奏する他、機能素子の製
造上の部分的特性を電界効果型半導体素子の影響を受け
ずに計測することができる。 According to the semiconductor device according to claim 1 0, wherein the [0057] present invention, in addition to the same effects as claim 1, the partial characteristics of the preparation of the functional element without being influenced by the field effect semiconductor device Can be measured.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の実施の形態の半導体装置の半導体チッ
プ表面を示す平面図である。FIG. 1 is a plan view showing a semiconductor chip surface of a semiconductor device according to an embodiment of the present invention.

【図２】図１のＡ−Ａ’線の断面図である。FIG. 2 is a sectional view taken along line A-A 'of FIG.

【図３】第１の絶縁膜の形状を示す平面図である。FIG. 3 is a plan view showing a shape of a first insulating film.

【図４】赤外線センサ回路の構成を示す回路図である。FIG. 4 is a circuit diagram showing a configuration of an infrared sensor circuit.

【図５】従来の半導体装置の半導体チップの断面図であ
る。FIG. 5 is a cross-sectional view of a semiconductor chip of a conventional semiconductor device.

【符号の説明】 １ 第１の分離領域 ２ 第２の分離領域 ３ ゲート領域 ４ａ，４ｂ ソース・ドレイン用引き出し配線 ５ 裏面ゲート電極 ６ａ，６ｂ ボンディングパッド ７ａ，７ｂ ボンディングパッド ８ Ｐ型半導体基板 ９ Ｐ型エピタキシャル層 １０ Ｎ型エピタキシャル層 １１ 第１の絶縁膜 １２ 抵抗素子 １３ 第２の絶縁膜 １４ 金属配線 １５ Ｎ型エピタキシャル層 １６Ａ 共通接続部 １６Ｂ 分岐部 １６Ｃ，１６Ｄ 幅広部 [Description of Signs] 1 First isolation region 2 Second isolation region 3 Gate region 4a, 4b Source / drain lead-out line 5 Back surface gate electrode 6a, 6b Bonding pad 7a, 7b Bonding pad 8 P-type semiconductor substrate 9 P -Type epitaxial layer 10 N-type epitaxial layer 11 First insulating film 12 Resistive element 13 Second insulating film 14 Metal wiring 15 N-type epitaxial layer 16A Common connection part 16B Branch part 16C, 16D Wide part

【手続補正２】[Procedure amendment 2]

【補正対象書類名】図面[Document name to be amended] Drawing

【補正対象項目名】図３[Correction target item name] Figure 3

【補正方法】変更[Correction method] Change

【補正内容】[Correction contents]

【図３】 FIG. 3

【手続補正３】[Procedure amendment 3]

【補正対象書類名】図面[Document name to be amended] Drawing

【補正対象項目名】図４[Correction target item name] Fig. 4

【補正方法】変更[Correction method] Change

【補正内容】[Correction contents]

【図４】 FIG. 4

【手続補正４】[Procedure amendment 4]

【補正対象書類名】図面[Document name to be amended] Drawing

【補正対象項目名】図５[Correction target item name] Fig. 5

【補正方法】変更[Correction method] Change

【補正内容】[Correction contents]

【図５】 FIG. 5

【手続補正５】[Procedure amendment 5]

【補正対象書類名】図面[Document name to be amended] Drawing

【補正対象項目名】図６[Correction target item name] Fig. 6

【補正方法】削除[Correction method] Deleted

【手続補正６】[Procedure amendment 6]

【補正対象書類名】図面[Document name to be amended] Drawing

【補正対象項目名】図７[Correction target item name] Fig. 7

【補正方法】削除[Correction method] Deleted

───────────────────────────────────────────────────── フロントページの続き (72)発明者 福本 信治 大阪府高槻市幸町１番１号 松下電子工業 株式会社内 (72)発明者 大橋 則子 大阪府高槻市幸町１番１号 松下電子工業 株式会社内 Ｆターム(参考） 4M106 AA04 AB15 AB16 AD01 AD04 AD24 CA10 5F044 AA01 EE02 5F102 FB06 GA17 GB01 GC02 GD04 GV03 HC01 HC05 HC15  ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Shinji Fukumoto 1-1, Yukicho, Takatsuki-shi, Osaka Matsushita Electronics Co., Ltd. (72) Noriko Ohashi 1-1-1, Yukicho, Takatsuki-shi, Osaka Matsushita Electronics F term (reference) 4M106 AA04 AB15 AB16 AD01 AD04 AD24 CA10 5F044 AA01 EE02 5F102 FB06 GA17 GB01 GC02 GD04 GV03 HC01 HC05 HC15

Claims (14)

【特許請求の範囲】[Claims] 【請求項１】 一導電型の半導体基板と、 この半導体基板上に形成された逆導電型層と、 前記逆導電型層を貫通して底部が前記半導体基板まで達
する状態に前記半導体基板の中央部付近に設けられて前
記逆導電型層を内側領域と外側領域とに分離する前記半
導体基板と同一導電型の内部分離領域と、 前記内部分離領域で囲まれて接合型電界効果半導体素子
のソース／ドレイン領域となる前記逆導電型層の内側領
域上に設けられた前記接合型電界効果半導体素子のゲー
ト領域と、 前記逆導電型層を貫通して底部が前記半導体基板まで達
する状態に前記半導体基板の端縁部に設けられた前記半
導体基板と同一導電型の外部接続領域と、 前記逆導電型層の外側領域上に設けられて前記外部接続
領域に接続された回路素子とを備えた半導体装置。A semiconductor substrate of one conductivity type; a reverse conductivity type layer formed on the semiconductor substrate; and a center of the semiconductor substrate in a state where a bottom portion reaches the semiconductor substrate through the reverse conductivity type layer. An internal isolation region of the same conductivity type as the semiconductor substrate, which is provided near the portion and separates the opposite conductivity type layer into an inner region and an outer region; A gate region of the junction field effect semiconductor element provided on an inner region of the opposite conductivity type layer serving as a drain / drain region; and a semiconductor having a bottom portion reaching the semiconductor substrate through the opposite conductivity type layer. A semiconductor, comprising: an external connection region of the same conductivity type as the semiconductor substrate provided at an edge of the substrate; and a circuit element provided on an outer region of the opposite conductivity type layer and connected to the external connection region. apparatus. 【請求項２】 半導体基板が矩形のチップ形状であっ
て、外部接続領域が前記半導体基板の周囲端部に矩形枠
状に設けられ、逆導電型層の外側領域上に少なくとも１
個以上のボンディングパッドが設けられたことを特徴と
する請求項１記載の半導体装置。2. The semiconductor substrate according to claim 1, wherein the semiconductor substrate has a rectangular chip shape, an external connection region is provided in a rectangular frame shape at a peripheral end of the semiconductor substrate, and at least one external connection region is provided on an outer region of the opposite conductivity type layer.
2. The semiconductor device according to claim 1, wherein at least one bonding pad is provided. 【請求項３】 ボンディングパッドとして、回路素子に
接続される少なくとも１個のボンディングパッドと、ソ
ース／ドレイン領域にそれぞれ接続される少なくとも２
個のボンディングパッドとがあり、各々のボンディング
パッドが逆導電型層の外側領域上の矩形枠状の外部接続
領域の各コーナー部の近傍位置に配置されたことを特徴
とする請求項２記載の半導体装置。3. At least one bonding pad connected to a circuit element and at least two bonding pads connected to source / drain regions, respectively, as bonding pads.
3. The bonding pad according to claim 2, wherein there are a plurality of bonding pads, and each bonding pad is arranged at a position near each corner of a rectangular frame-shaped external connection region on an outer region of the opposite conductivity type layer. Semiconductor device. 【請求項４】 回路素子が機能領域と、この機能領域の
一端に設けた共通接続部と、前記機能領域の他端に設け
たボンディングパッド部とからなり、前記共通接続部が
外部接続領域に接続されていることを特徴とする請求項
１記載の半導体装置。4. A circuit element comprising a function region, a common connection portion provided at one end of the function region, and a bonding pad portion provided at the other end of the function region, wherein the common connection portion is connected to an external connection region. The semiconductor device according to claim 1, wherein the semiconductor device is connected. 【請求項５】 回路素子の共通接続部とボンディングパ
ッド部とが半導体基板の端部側に設けられ、前記回路素
子の機能領域が半導体基板の内部側に設けられているこ
とを特徴とする請求項４記載の半導体装置。5. The semiconductor device according to claim 1, wherein a common connection portion and a bonding pad portion of the circuit element are provided on an end of the semiconductor substrate, and a functional region of the circuit element is provided on an inner side of the semiconductor substrate. Item 5. The semiconductor device according to item 4. 【請求項６】 回路素子の機能領域の共通接続部側と反
対側が少なくとも２つ以上に分岐され、前記分岐された
機能領域の他端側の各々にボンディングパッドが設けら
れていることを特徴とする請求項１または５記載の半導
体装置。6. The circuit device according to claim 1, wherein a side opposite to the common connection portion side of the functional region of the circuit element is branched into at least two or more, and a bonding pad is provided on each of the other end sides of the branched functional region. 6. The semiconductor device according to claim 1, wherein: 【請求項７】 ゲート領域が半導体基板と同一導電型で
あり、逆導電型層の内側領域上に前記逆導電型層の内側
領域をソース領域とドレイン領域とに分断するように両
端が内部分離領域と接する状態に設けられたことを特徴
とする請求項１記載の半導体装置。7. The gate region is of the same conductivity type as the semiconductor substrate, and both ends are internally separated on the inner region of the opposite conductivity type layer so as to divide the inner region of the opposite conductivity type layer into a source region and a drain region. 2. The semiconductor device according to claim 1, wherein the semiconductor device is provided in contact with the region. 【請求項８】 回路素子が薄膜抵抗であり、狭幅線状領
域を実質的な機能領域とし、少なくとも前記狭幅線状領
域の一端部にボンディングパッドの外形よりも大きい幅
広領域を有し、前記幅広領域上に前記ボンディングパッ
ド用の金属電極を設けたことを特徴とする請求項１記載
の半導体装置。8. The circuit element is a thin film resistor, the narrow linear region is a substantial functional region, and at least one end of the narrow linear region has a wide region larger than the outer shape of the bonding pad; 2. The semiconductor device according to claim 1, wherein a metal electrode for the bonding pad is provided on the wide area. 【請求項９】 回路素子が外部接続領域と内部分離領域
との間の逆導電型層上でそれと対応した配置形状の第１
の絶縁膜上に設けられたことを特徴とする請求項１記載
の半導体装置。9. The circuit element according to claim 1, wherein the circuit element is arranged on a layer of the opposite conductivity type between the external connection region and the internal isolation region and has a corresponding arrangement shape.
2. The semiconductor device according to claim 1, wherein said semiconductor device is provided on said insulating film. 【請求項１０】 回路素子が第１の絶縁膜より厚い第２
の絶縁膜で覆われ、前記第２の絶縁膜の開き領域を通し
て前記回路素子に接続される金属電極が設けられ、前記
金属電極を介して前記回路素子が外部接続領域と接続さ
れることを特徴とする請求項９記載の半導体装置。10. A circuit element according to claim 2, wherein said circuit element is thicker than said first insulating film.
And a metal electrode connected to the circuit element through an open area of the second insulating film, and the circuit element is connected to an external connection area via the metal electrode. 10. The semiconductor device according to claim 9, wherein: 【請求項１１】 内部分離領域上および逆導電型層の内
側領域上が第２の絶縁膜で保護され、外部接続領域がス
クライブライン部と兼ねられ、前記外部接続領域にスク
ライブ用の前記第２の絶縁膜の開き領域が設けられてい
ることを特徴とする請求項１０記載の半導体装置。11. The second insulating film protects the inner isolation region and the inner region of the opposite conductivity type layer, the external connection region also serves as a scribe line portion, and the scribe line is formed in the external connection region. 11. The semiconductor device according to claim 10, wherein an open region of said insulating film is provided. 【請求項１２】 半導体素子載置部を有したリードフレ
ームに前記半導体素子載置部から一体に導出されたゲー
ト用外部リードを設け、前記半導体素子載置部に一導電
型で下部に高濃度領域を設けた半導体基板を載置し、前
記半導体基板の外部接続領域を介して回路素子を前記ゲ
ート用外部リードに接続したことを特徴とする請求項１
記載の半導体装置。12. A lead frame having a semiconductor element mounting portion is provided with a gate external lead integrally led out from the semiconductor element mounting portion, and the semiconductor element mounting portion is of one conductivity type and has a high concentration underneath. 2. The semiconductor device according to claim 1, wherein a semiconductor substrate provided with a region is mounted, and a circuit element is connected to the external lead for gate via an external connection region of the semiconductor substrate.
13. The semiconductor device according to claim 1. 【請求項１３】 分岐された機能領域の他端側の各々の
少なくとも２個以上のボンディングパッド間を測定する
ことにより前記機能領域の製造上の部分的特性を計測可
能としたことを特徴とする請求項６記載の半導体装置。13. The manufacturing method according to claim 1, wherein a measurement is made between at least two or more bonding pads on each of the other end sides of the branched functional region to measure partial characteristics of the functional region in manufacturing. The semiconductor device according to claim 6. 【請求項１４】 矩形の半導体素子載置部と、この半導
体素子載置部から独立した状態で前記半導体素子載置部
のコーナー部付近から外方へ延出された外部リードと、
矩形のチップ形状を有し表面に一辺の近傍で前記一辺の
長さ方向に並んだ状態の２個以上のボンディングパッド
を有し、前記外部リードが延出された前記半導体素子載
置部のコーナー部に前記一辺が対向する状態に前記半導
体素子載置部に載置された半導体基板と、前記２個以上
のボンディングパッドと前記外部リードの基端部とを各
々接続するほぼ均等な長さの２本以上のワイヤとを備え
た半導体装置。14. A rectangular semiconductor device mounting portion, and an external lead extending outward from a vicinity of a corner of the semiconductor device mounting portion independently of the semiconductor device mounting portion.
A corner of the semiconductor element mounting portion having a rectangular chip shape, having two or more bonding pads on a surface thereof in the vicinity of one side and arranged in the length direction of the one side, wherein the external leads are extended; A semiconductor substrate mounted on the semiconductor element mounting portion in a state where the one side faces the portion, and a substantially equal length for connecting the two or more bonding pads and the base ends of the external leads, respectively. A semiconductor device comprising two or more wires.
JP10216679A 1998-07-31 1998-07-31 Semiconductor device Expired - Fee Related JP3012227B2 (en)

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JP10216679A JP3012227B2 (en) 1998-07-31 1998-07-31 Semiconductor device

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JP10216679A JP3012227B2 (en) 1998-07-31 1998-07-31 Semiconductor device

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JP11250699A Division JP2000082771A (en) 1999-09-03 1999-09-03 Semiconductor device

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2014155959A1 (en) * 2013-03-27 2017-02-16 パナソニックＩｐマネジメント株式会社 Power semiconductor element

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2014155959A1 (en) * 2013-03-27 2017-02-16 パナソニックＩｐマネジメント株式会社 Power semiconductor element

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