JP2000020576A - Power source optimizing automatic arrangement wiring method and its device using the same - Google Patents
Power source optimizing automatic arrangement wiring method and its device using the sameInfo
- Publication number
- JP2000020576A JP2000020576A JP10191634A JP19163498A JP2000020576A JP 2000020576 A JP2000020576 A JP 2000020576A JP 10191634 A JP10191634 A JP 10191634A JP 19163498 A JP19163498 A JP 19163498A JP 2000020576 A JP2000020576 A JP 2000020576A
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- cell
- wiring
- power supply
- voltage drop
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Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体集積回路に
おける電源最適化自動配置配線方法及びその方法を用い
た電源最適化自動配置配線装置に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power supply optimization automatic placement and routing method in a semiconductor integrated circuit and a power supply optimization automatic placement and routing apparatus using the method.
【０００２】[0002]
【従来の技術】図３は従来の複数の機能セルに対して自
動配置配線を実施する場合の電源強化を示した図であ
る。図３において、３０〜３５は配置配線される機能セ
ルで、３６は機能セル３０〜３５が配置されるセル列、
３７と３８は複数のセル列３６に電圧を供給する機能セ
ルの保有する標準の電源配線である。2. Description of the Related Art FIG. 3 is a diagram showing power supply enhancement in a case where a conventional automatic placement and routing is performed for a plurality of functional cells. In FIG. 3, reference numerals 30 to 35 denote functional cells to be arranged and wired, 36 denotes a cell column in which the functional cells 30 to 35 are arranged,
Reference numerals 37 and 38 denote standard power supply wires owned by functional cells that supply voltages to the plurality of cell columns 36.
【０００３】複数の機能セル３０〜３５に対して自動配
置配線を実施する場合には、回路の動作周波数及び想定
される配線容量より予め各セル列３６で消費される電流
量を予測し、セル列の幅３９を設計者が決定した上で、
自動配置配線されるセルの総消費電流量より、電源３７
と電源３８の配線では目的とする電圧が供給できない場
合には、補強電源４０（ＶＤＤ）と補強電源４１（ＶＳ
Ｓ）を予め設定した後に自動配置配線を行う。When performing automatic placement and routing for a plurality of functional cells 30 to 35, the amount of current consumed in each cell column 36 is predicted in advance from the operating frequency of the circuit and the assumed wiring capacity, and After the designer has decided the column width 39,
From the total current consumption of the cells to be automatically placed and routed, the power supply 37
When the target voltage cannot be supplied by the wiring of the power supply 38 and the power supply 38, the reinforcing power supply 40 (VDD) and the reinforcing power supply 41 (VS
After setting S) in advance, automatic placement and routing is performed.
【０００４】また、特開平８−２７２８３６号公報によ
れば、機能セルの仮配置情報より電源の強化を実施す
る。According to Japanese Patent Application Laid-Open No. Hei 8-272736, the power supply is strengthened based on the provisional arrangement information of the functional cells.
【０００５】[0005]
【発明が解決しようとする課題】しかしながら前述の図
３に示す自動配置配線では、設計者がセル列の電源補強
を自動配置配線の実行に先だって予め設定する必要があ
り、また自動配置配線装置は消費電流の値に関係なくセ
ル配置を行う。このため、消費電流が多い機能セルを集
中して同じセル列に配置する可能性があり、設計者は大
消費電流セルが同じセル列に配置された場合を想定し
て、セル列の幅及び電源補強を決定する必要がある。こ
の結果、実際に同じセル列に大消費電流の機能セルが配
置されない場合には、電源の余裕が過剰となり、半導体
集積回路の面積が増大し、半導体のコストが増加すると
いう課題を有していた。However, in the above-described automatic placement and routing shown in FIG. 3, it is necessary for a designer to set power supply reinforcement of a cell column in advance of execution of the automatic placement and routing. The cell arrangement is performed regardless of the value of the current consumption. For this reason, there is a possibility that functional cells having large current consumption may be concentrated and arranged in the same cell column, and the designer may assume that the large current consumption cells are arranged in the same cell column, and assume that the width and width of the cell column are large. Power reinforcement needs to be determined. As a result, when a functional cell with a large current consumption is not actually arranged in the same cell row, there is a problem that the margin of the power supply becomes excessive, the area of the semiconductor integrated circuit increases, and the cost of the semiconductor increases. Was.
【０００６】また、特開平８−２７２８３６号公報に記
載された電源強化方法によれば、機能セルに付加される
配線の容量に関係なく、配置情報のみでセル列の消費電
流を算出するために、回路の動作周波数や、大配線容量
を駆動するクロックバッファや、バスバッファなどの機
能セルの電流値は正確に評価できないため、補強電源の
過不足が発生するおそれがあり、その結果、半導体の動
作を保証できないという問題点を有していた。In addition, according to the power supply enhancement method described in Japanese Patent Application Laid-Open No. Hei 8-272736, the current consumption of a cell row is calculated only from the placement information regardless of the capacitance of the wiring added to the functional cell. However, since the operating frequency of the circuit and the current value of functional cells such as a clock buffer and a bus buffer for driving a large wiring capacity cannot be accurately evaluated, there is a possibility that excess or deficiency of the reinforcing power supply may occur, and as a result, There is a problem that operation cannot be guaranteed.
【０００７】本発明は、上記問題点を解決するもので、
自動配置配線後に、機能セルの動作周波数と、実際の機
能セルの出力容量より消費電流を算出し、各セル列ごと
に各機能セルの電圧降下値を基準にして、電源の配線幅
及びセル列の幅を最適にして、半導体の面積を最小化す
ることにより、半導体のコストダウンを可能とし、ま
た、半導体の内部回路の電源電圧降下による動作不良を
防止することを目的とする。The present invention solves the above problems,
After the automatic placement and routing, the current consumption is calculated from the operating frequency of the functional cell and the output capacitance of the actual functional cell, and the wiring width of the power supply and the cell column are determined for each cell column based on the voltage drop value of each functional cell. By optimizing the width of the semiconductor device and minimizing the area of the semiconductor, it is possible to reduce the cost of the semiconductor and to prevent the operation failure due to the power supply voltage drop of the internal circuit of the semiconductor.
【０００８】[0008]
【課題を解決するための手段】上記の課題を解決し目的
を達成するために、本発明の電源最適化自動配置配線方
法は、機能セルの単位動作周波数当たりの消費電流と、
機能セルの単位負荷容量当たりの消費電流と、機能セル
の動作周波数と、配線した各機能セルの出力端子の負荷
容量、及び設計者が予め設定した最大許容電圧降下値か
ら、電源の配線幅及びセル列の幅を最適化することを特
徴とする。SUMMARY OF THE INVENTION In order to solve the above-mentioned problems and achieve the object, a power supply optimization automatic placement and routing method according to the present invention comprises:
From the current consumption per unit load capacity of the functional cell, the operating frequency of the functional cell, the load capacity of the output terminal of each wired functional cell, and the maximum allowable voltage drop value preset by the designer, the wiring width of the power supply and It is characterized in that the width of the cell column is optimized.
【０００９】この方法によって、自動配置配線の結果よ
り、最適な電圧を各機能セルに供給することができるた
め、すべての機能セルの動作時の電圧降下を、当初目的
とした値の範囲以下にすることができ、半導体の内部電
圧降下による誤動作を防止し、レイアウトのサイズを最
小化することが可能となる。According to this method, the optimum voltage can be supplied to each functional cell based on the result of the automatic placement and routing, so that the voltage drop during the operation of all the functional cells falls within the range of the initially intended value. It is possible to prevent malfunction due to a semiconductor internal voltage drop and to minimize the layout size.
【００１０】[0010]
【発明の実施の形態】以下、本発明の実施の形態につい
て図面を参照しながら説明する。Embodiments of the present invention will be described below with reference to the drawings.
【００１１】図１は本発明の電源最適化自動配置配線装
置の構成を示すブロック図、図２はその電源強化手法の
フローチャートを示す。FIG. 1 is a block diagram showing the configuration of a power supply optimizing automatic placement and routing apparatus according to the present invention, and FIG. 2 is a flowchart showing a power supply enhancement method.
【００１２】本発明の方法を実施する電源最適化自動配
置配線装置は、図２のフローチャートに示す複数の機能
セルの接続情報からなる回路情報１を入力し保有する手
段２１と、機能セルライブラリ２を記憶する手段２２
と、回路の動作周波数３を記憶する手段２３と、最大許
容電圧降下値４を記憶する手段２４と、前記各手段２１
〜２４に入力された情報に基づいて、自動配置５及び自
動配線６，９を実施する手段２５と、各セル列の負荷容
量値に基づいて消費電流値を算出７する手段２６と、各
機能セルに供給される電源電圧が最大許容電圧降下値以
内となるように電源補強８を行う手段２７と、再自動配
置配線後の各機能セルの電圧降下値の許容値を満足して
いるか否かを確認１０する手段２８とを有する。The power supply optimizing automatic placement and routing apparatus for carrying out the method of the present invention comprises a means 21 for inputting and holding circuit information 1 comprising connection information of a plurality of function cells shown in the flowchart of FIG. 2, and a function cell library 2 Means 22 for storing
Means 23 for storing the operating frequency 3 of the circuit; means 24 for storing the maximum allowable voltage drop value 4;
A means 25 for performing the automatic placement 5 and the automatic wiring 6 and 9 based on the information input to the .about.24, a means 26 for calculating the current consumption value 7 based on the load capacitance value of each cell column, Means 27 for performing power supply reinforcement 8 so that the power supply voltage supplied to the cell is within the maximum allowable voltage drop value, and whether the allowable value of the voltage drop value of each functional cell after the re-automatic placement and routing is satisfied And means 28 for confirming 10.
【００１３】次に電源最適化自動配置配線方法とその装
置の動作を図２のフローチャートにより説明する。入力
保有手段２１からは複数の機能セルの接続情報からなる
回路情報１を入力し、記憶手段２２からの機能セルライ
ブラリ２を基に、自動配置配線の実施手段２５でもって
機能セルの自動配置５及びこの自動配置したセルの仮自
動配線６を実行する。仮自動配線６を実施したデータに
対して、各機能セルの負荷容量や、回路の動作周波数３
と配線の負荷容量値に基づいて、各セル列毎の消費電流
値の算出７を算出手段２６により行う。Next, the operation of the power supply optimization automatic placement and routing method and the apparatus will be described with reference to the flowchart of FIG. Circuit information 1 including connection information of a plurality of function cells is input from the input holding unit 21, and based on the function cell library 2 from the storage unit 22, the automatic placement and routing of the function cells 5 is performed by the automatic placement and routing execution unit 25. Then, the temporary automatic wiring 6 of the automatically arranged cells is executed. With respect to the data on which the tentative automatic wiring 6 has been performed, the load capacity of each functional cell and the operating frequency of the circuit 3
The calculation means 26 calculates the current consumption value for each cell column based on the load capacitance value of the wiring and the load value.
【００１４】消費電流値の計算は、The calculation of the current consumption value is as follows.
【００１５】[0015]
【数１】Irow ＝ ΣIff ＋ ΣItr で算出し、Iffはフリップフロップの電流を示し、Itrは
組み合わせ回路の電流を示す。それぞれの電流の算出
は、フリップフロップの動作電源電圧Ｖ時の入力クロッ
ク周波数をn(MHz)、単位周波数当たりの入力ロジックの
消費電流をIck(mA/MHz)、単位周波数当たりの内部ロジ
ック部の消費電流Iq(mA/MHz)、単位周波数及び単位負荷
容量当たりの出力部の消費電流をIt(mA/MHz)、フリップ
フロップの出力端子の負荷容量をCq(pF)とすれば、[Equation 1] Irow = ΣIff + ΣItr, where Iff indicates the current of the flip-flop and Itr indicates the current of the combinational circuit. Calculation of each current is as follows: the input clock frequency at the operating power supply voltage V of the flip-flop is n (MHz), the consumption current of the input logic per unit frequency is Ick (mA / MHz), and the internal logic unit per unit frequency is If the current consumption Iq (mA / MHz), the current consumption of the output unit per unit frequency and unit load capacity is It (mA / MHz), and the load capacity of the output terminal of the flip-flop is Cq (pF),
【００１６】[0016]
【数２】Iff ＝ (Ick × n) ＋ (Iq ＋ (It × Cq))×
n/2 (mA） で算出し、各々の機能セルの消費電流値は、機能セルラ
イブラリ２の記憶手段２２に保持されている。また同様
に、組み合わせ回路の消費電流は出力端子の負荷容量を
C(pF)、動作周波数をn(MHz)、動作電圧をV(v)とすれ
ば、[Equation 2] Iff = (Ick × n) + (Iq + (It × Cq)) ×
The current consumption value of each functional cell is calculated in n / 2 (mA), and is stored in the storage unit 22 of the functional cell library 2. Similarly, the current consumption of the combinational circuit depends on the load capacitance of the output terminal.
If C (pF), operating frequency is n (MHz), and operating voltage is V (v),
【００１７】[0017]
【数３】Ick ＝ CVn(mA) で算出し、各セル列の消費電流値の総和を求める。## EQU3 ## Calculated by Ick = CVn (mA), and the sum of the current consumption values of each cell column is obtained.
【００１８】各セル列の両側は、基幹電源に接続される
場合には、セル列の電源の幅をW(um)、配線のシート抵
抗をRΩとし、セルの入力端子からセル列端までの距離L
(um)より、セルの電圧降下値は、When both sides of each cell row are connected to the main power supply, the width of the power supply of the cell row is W (um), the sheet resistance of the wiring is RΩ, and the distance from the input terminal of the cell to the end of the cell row. Distance L
From (um), the voltage drop value of the cell is
【００１９】[0019]
【数４】Vdown ＝ (R/W × L) × Irow/2 で算出する。セルの最大許容電圧降下値４をVlimitとす
れば、各セル列の各セルにおいて、## EQU4 ## Calculated as Vdown = (R / W × L) × Irow / 2. Assuming that the maximum allowable voltage drop value 4 of a cell is Vlimit, in each cell of each cell row,
【００２０】[0020]
【数５】Vlimit ＞ Vdown となるように、各セル列単位で電源補強８を手段２７で
行う。配線の容量算出式及び配線のシート抵抗値は、機
能セルライブラリ２の入力保有手段２１にて保有する。The power supply reinforcement 8 is performed by the means 27 for each cell column so that Vlimit> Vdown. The wiring capacity calculation formula and the wiring sheet resistance value are held by the input holding unit 21 of the functional cell library 2.
【００２１】電源補強８の手段２７によって、セル列の
座標が変更されるため、自動配置配線実施手段２５でも
って再度自動配線９を実施し、配線完了後、変更された
配線によって、各機能セルの最大許容電圧降下値４が許
容値を満足しているかどうかを確認手段２８で確認し、
満足されていれば処理を完了し、満足しない場合には各
セルの消費電流値算出７に戻り、以降の処理を実施す
る。Since the coordinates of the cell row are changed by the means 27 of the power supply reinforcement 8, the automatic wiring 9 is performed again by the automatic arrangement and wiring execution means 25, and after the completion of the wiring, each of the functional cells is changed by the changed wiring. It is confirmed by the confirmation means 28 whether or not the maximum allowable voltage drop value 4 satisfies the allowable value.
If the condition is satisfied, the process is completed. If the condition is not satisfied, the process returns to the calculation of the current consumption value of each cell 7, and the subsequent processes are performed.
【００２２】以上のように、本実施の形態によれば、配
置配線後のデータを基に、電源の最適な補強を実施する
ことにより、最適な半導体集積回路の電源補強を実現す
ることができる。As described above, according to the present embodiment, the optimum power supply of the semiconductor integrated circuit can be realized by performing the optimum power supply reinforcement based on the data after the placement and routing. .
【００２３】[0023]
【発明の効果】以上説明したように、本発明は、半導体
集積回路の面積を最小化した上で、目的の電源電圧降下
値を満足することにより、論理シミュレーションや、タ
イミングシミュレーションでは確認することができな
い、半導体集積回路の電圧降下による動作不良を回避す
ることができる。また、従来レイアウト設計者が自動配
置配線を実施する前に、設計者の経験により電源補強を
マニュアルで実施していた作業を自動化でき、設計効率
を改善することにより、開発期間の短縮を実現できる。As described above, according to the present invention, by minimizing the area of the semiconductor integrated circuit and satisfying the target power supply voltage drop value, it can be confirmed by logic simulation and timing simulation. It is possible to avoid a malfunction that cannot be caused by a voltage drop of the semiconductor integrated circuit. In addition, before the layout designer performs the automatic placement and routing, the work of manually reinforcing the power supply can be automated based on the experience of the designer, and the design period can be shortened by improving the design efficiency. .
【図１】本発明の実施の形態における電源最適化自動配
置配線装置の構成を示すブロック図FIG. 1 is a block diagram showing a configuration of a power supply optimization automatic placement and routing apparatus according to an embodiment of the present invention.
【図２】本発明の実施の形態における電源最適化自動配
置配線方法を示す図１の電源補強を行う場合のフローチ
ャートFIG. 2 is a flowchart showing a power supply optimization automatic placement and routing method according to the embodiment of the present invention, in which power supply reinforcement is performed in FIG. 1;
【図３】従来の自動配置配線を実施する場合の電源強化
を示す図FIG. 3 is a diagram showing power supply enhancement when implementing conventional automatic placement and routing.
２１ 回路情報１の入力保有手段 ２２ 機能セルライブラリ２の記憶手段 ２３ 回路の動作周波数３の記憶手段 ２４ 最大許容電圧降下値４の記憶手段 ２５ 機能セルの自動配置配線５，６，９を実施する手
段 ２６ 各セル列の消費電流値の算出７する手段 ２７ 電源補強８を行う手段 ２８ 各セル列の電圧降下値の確認１０する手段21 Input information holding means for circuit information 22 Storage means for functional cell library 2 23 Storage means for operating frequency 3 of circuit 24 Storage means for maximum allowable voltage drop value 4 25 Automatic placement and wiring of functional cells 5, 6 and 9 Means 26 Calculation of current consumption value of each cell row 7 Means 27 Power supply reinforcement 8 Means 28 Confirmation of voltage drop value of each cell row 10
Claims (2)
情報を入力とし、機能セルライブラリを基に、機能セル
の自動配置及び自動配置した機能セルの仮自動配置配線
を実行する工程と、仮自動配置配線を実施したデータに
対して、各機能セルの負荷容量を算出し、回路の動作周
波数と配線の負荷容量に基づいて、各セル列毎の負荷容
量値に基づいて消費電流値を算出する工程と、前記消費
電流値算出工程で得られた算出電流値と各機能セルの最
大許容電圧降下値に基づいて各セル列単位で電源の補強
を行う工程と、前記電源補強工程によってセル列の座標
変更に伴う再自動配置配線工程と、前記再自動配置配線
工程後の各機能セルの電圧降下値の許容値を満足してい
るか否かを確認する工程とを含むことを特徴とする電源
最適化自動配置配線方法。A circuit for automatically arranging function cells and temporarily arranging and automatically arranging the automatically arranged function cells on the basis of a function cell library, based on input of circuit information including connection information of a plurality of function cells; Calculate the load capacity of each function cell for the data on which the automatic placement and routing has been performed, and calculate the current consumption value based on the load capacity value of each cell column based on the operating frequency of the circuit and the load capacity of the wiring. Performing power supply reinforcement in each cell column based on the calculated current value obtained in the consumed current value calculation step and the maximum allowable voltage drop value of each functional cell. Automatically re-arranging and wiring step associated with the coordinate change of step (a), and a step of confirming whether or not a permissible value of a voltage drop value of each functional cell after the re-alarm arrangement and wiring step is satisfied. Optimized automatic placement and routing Method.
情報を入力保有する手段と、機能セルライブラリを記憶
する手段と、回路の動作周波数を記憶する手段と、最大
許容電圧降下値を記憶する手段と、前記各手段に入力さ
れた各情報に基づいて、自動配置配線を実施する手段
と、各セル列の負荷容量値に基づいて消費電流値を算出
する手段と、各機能セルに供給される電源電圧が最大許
容電圧降下値以内となるように電源補強を行う手段と、
再自動配置配線後の各機能セルの電圧降下値の許容値を
満足しているか否かを確認する手段とを有することを特
徴とする電源最適化自動配置配線装置。2. A means for inputting and holding circuit information comprising connection information of a plurality of function cells, a means for storing a function cell library, a means for storing an operating frequency of a circuit, and a maximum allowable voltage drop value. Means, means for performing automatic placement and routing based on each information input to each means, means for calculating a current consumption value based on the load capacitance value of each cell column, and Means for reinforcing the power supply so that the power supply voltage is within the maximum allowable voltage drop value,
Means for confirming whether or not the allowable value of the voltage drop value of each functional cell after the re-automatic placement and routing is satisfied.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10191634A JP2000020576A (en) | 1998-07-07 | 1998-07-07 | Power source optimizing automatic arrangement wiring method and its device using the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10191634A JP2000020576A (en) | 1998-07-07 | 1998-07-07 | Power source optimizing automatic arrangement wiring method and its device using the same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2000020576A true JP2000020576A (en) | 2000-01-21 |
Family
ID=16277926
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10191634A Pending JP2000020576A (en) | 1998-07-07 | 1998-07-07 | Power source optimizing automatic arrangement wiring method and its device using the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2000020576A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6854094B2 (en) | 2001-12-07 | 2005-02-08 | Fujitsu Limited | Method and apparatus for laying out power supply wiring |
| US7539964B2 (en) * | 2006-03-20 | 2009-05-26 | Fujitsu Microelectronics Limited | Cell placement taking into account consumed current amount |
| CN101834164B (en) * | 2009-03-10 | 2011-11-16 | 奇景光电股份有限公司 | Power distribution system |
| CN116432600A (en) * | 2023-06-12 | 2023-07-14 | 北京智芯仿真科技有限公司 | Method and system for automatically optimizing power-ground network of integrated circuit |
-
1998
- 1998-07-07 JP JP10191634A patent/JP2000020576A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6854094B2 (en) | 2001-12-07 | 2005-02-08 | Fujitsu Limited | Method and apparatus for laying out power supply wiring |
| US7539964B2 (en) * | 2006-03-20 | 2009-05-26 | Fujitsu Microelectronics Limited | Cell placement taking into account consumed current amount |
| CN101834164B (en) * | 2009-03-10 | 2011-11-16 | 奇景光电股份有限公司 | Power distribution system |
| CN116432600A (en) * | 2023-06-12 | 2023-07-14 | 北京智芯仿真科技有限公司 | Method and system for automatically optimizing power-ground network of integrated circuit |
| CN116432600B (en) * | 2023-06-12 | 2023-08-25 | 北京智芯仿真科技有限公司 | Method and system for automatically optimizing power-ground network of integrated circuit |
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