JP2000012626A - Semiconductor device and its manufacture - Google Patents
Semiconductor device and its manufactureInfo
- Publication number
- JP2000012626A JP2000012626A JP17782898A JP17782898A JP2000012626A JP 2000012626 A JP2000012626 A JP 2000012626A JP 17782898 A JP17782898 A JP 17782898A JP 17782898 A JP17782898 A JP 17782898A JP 2000012626 A JP2000012626 A JP 2000012626A
- Authority
- JP
- Japan
- Prior art keywords
- bonding
- wiring layer
- semiconductor chip
- carrier film
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】この発明は、異方導電性フィ
ルム（以下、ＡＣＦ）を用いてキャリアフィルムと半導
体チップとの貼り合わせを行うと共に、配線層の端子部
とチップ電極パッドとの電気的接続を行う半導体装置及
びその製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to bonding a carrier film and a semiconductor chip using an anisotropic conductive film (hereinafter, ACF), and electrically connecting a terminal portion of a wiring layer to a chip electrode pad. The present invention relates to a semiconductor device for connection and a method for manufacturing the same.
【０００２】[0002]
【従来の技術】従来においては、図３に示すように、通
常半導体チップ９のチップ電極パッド１０上に金等の金
属バンプ１７をあらかじめ形成し、キャリアフィルム１
と半導体チップ９とをＡＣＦ４を介して支持台１５及び
平コレット１６等の加圧構成部品で一様に加熱、加圧す
ることにより接合を行うという手法が採用されている。2. Description of the Related Art Conventionally, as shown in FIG. 3, a metal bump 17 made of gold or the like is usually formed on a chip electrode pad 10 of a semiconductor chip 9 in advance.
The semiconductor chip 9 and the semiconductor chip 9 are joined by uniformly heating and pressurizing them with pressurizing components such as the support base 15 and the flat collet 16 via the ACF 4.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、この手
法では、半導体チップ９の全面にあるすべての電極パッ
ド１０と配線層３の端子部（図示せず）との電気接合を
確実に行うために、平コレット１６等の加圧構成部品の
押圧面と半導体チップ９の上面との平行度に数μｍ程度
の精度が要求される。従って、安定して均一な接合を行
うためには、接合装置の押圧面の機械的なメンテナンス
が随時要求され、接合装置の生産性を上げることは非常
に困難であった。However, in this method, all the electrode pads 10 on the entire surface of the semiconductor chip 9 and the terminal portions (not shown) of the wiring layer 3 must be electrically connected. The parallelism between the pressing surface of the pressing component such as the flat collet 16 and the upper surface of the semiconductor chip 9 is required to have an accuracy of about several μm. Therefore, in order to perform stable and uniform joining, mechanical maintenance of the pressing surface of the joining device is required as needed, and it has been extremely difficult to increase the productivity of the joining device.
【０００４】また、この手法では一様に加熱、加圧する
ことにより接合を行うので、導電粒子４ａによる端子部
以外の領域でのチップ回路と配線層３のショートを防ぐ
ために、半導体チップ９のチップ電極パッド１０に数十
μｍ高さの金属バンプ１７を形成する必要があり、製造
コストを上げる要因になっていた。In this method, the bonding is performed by uniformly applying heat and pressure. Therefore, in order to prevent a short circuit between the chip circuit and the wiring layer 3 in a region other than the terminal portion due to the conductive particles 4a, the chip of the semiconductor chip 9 is formed. It is necessary to form a metal bump 17 having a height of several tens of μm on the electrode pad 10, which has been a factor of increasing the manufacturing cost.
【０００５】この発明は、上記の事情に鑑みてなされた
もので、その主な目的の一つは、平行度調整を行う必要
がなく、接合装置の生産性を向上させることのできる半
導体装置及びその製造方法を提供することにある。The present invention has been made in view of the above circumstances, and one of its main objects is to provide a semiconductor device and a semiconductor device which do not need to adjust the parallelism and which can improve the productivity of a bonding apparatus. It is to provide a manufacturing method thereof.
【０００６】また、この発明の他の目的は、製造コスト
を上げる要因となる金属バンプを成形する必要のない半
導体装置及びその製造方法を提供することにある。Another object of the present invention is to provide a semiconductor device which does not need to form a metal bump which causes an increase in manufacturing cost, and a method of manufacturing the same.
【０００７】[0007]
【課題を解決するための手段】この発明の半導体装置及
びその製造方法では、上記課題を解決するため、以下の
手段を採用した。すなわち、請求項１記載の半導体装置
及びその製造方法によれば、半導体チップと、該半導体
チップに配設された複数のチップ電極パッドと、導電粒
子を包含する異方導電性フィルムと、配線層に形成され
た複数の端子部と、該配線層が形成されたキャリアフィ
ルムと、を順次重畳させて電路が形成される半導体装置
において、前記キャリアフィルムには、前記端子部の形
成された位置に対応させて複数のスルーホールが形成さ
れていることを特徴とする。In order to solve the above-mentioned problems, the following means have been adopted in the semiconductor device and the method of manufacturing the same according to the present invention. That is, according to the semiconductor device and the method of manufacturing the same according to claim 1, a semiconductor chip, a plurality of chip electrode pads provided on the semiconductor chip, an anisotropic conductive film containing conductive particles, and a wiring layer In a semiconductor device in which an electric path is formed by sequentially superposing a plurality of terminal portions formed on a substrate and a carrier film on which the wiring layer is formed, the carrier film has a position in which the terminal portion is formed. A plurality of through holes are formed correspondingly.
【０００８】請求項２記載の半導体装置の製造方法によ
れば、半導体チップのチップ電極パッドが配設されてい
る表面に異方導電性フィルムを載置し、貼り合わせる工
程と、前記異方導電性フィルムの表面にキャリアフィル
ムの配線層側を載置し、前記異方導電性フィルムのバイ
ンダを介して仮接着される工程と、キャリアフィルムに
形成されたスルーホールから挿入されるボンディングツ
ールの超音波併合熱圧着によって、配線層に形成された
端子部を押し込み変形させ、配線層の端子部と半導体チ
ップのチップ電極パッドとの間に導電粒子を挟み込んで
電気的接合を行う工程と、前記バインダが完全に硬化す
る温度に加熱し、貼り合わせを完了する工程と、を有す
ることを特徴とする。According to the method of manufacturing a semiconductor device of the present invention, a step of mounting and bonding an anisotropic conductive film on a surface of a semiconductor chip on which chip electrode pads are provided; Placing the wiring layer side of the carrier film on the surface of the conductive film and temporarily bonding the same via a binder of the anisotropic conductive film; and a step of superposing a bonding tool inserted from a through hole formed in the carrier film. A step of pushing and deforming a terminal portion formed on the wiring layer by sound wave merged thermocompression bonding, and performing electrical bonding by sandwiching conductive particles between the terminal portion of the wiring layer and the chip electrode pad of the semiconductor chip; and Is heated to a temperature at which is completely cured to complete the bonding.
【０００９】請求項３記載の半導体装置の製造方法によ
れば、キャリアフィルムの配線層側に異方導電性フィル
ムを載置し、貼り合わせる工程と、半導体チップのチッ
プ電極パッドが配設されている表面に前記工程で得られ
た製品の異方導電性フィルム側を載置し、前記異方導電
性フィルムのバインダを介して仮接着される工程と、キ
ャリアフィルムに形成されたスルーホールから挿入され
るボンディングツールの超音波併合熱圧着によって、配
線層に形成された端子部を押し込み変形させ、配線層の
端子部と半導体チップのチップ電極パッドとの間に導電
粒子を挟み込んで電気的接合を行う工程と、前記バイン
ダが完全に硬化する温度に加熱し、貼り合わせを完了す
る工程と、を有することを特徴とする。According to a third aspect of the present invention, there is provided a method of mounting a semiconductor film on a wiring layer side of a carrier film and bonding the anisotropic conductive film, and providing a chip electrode pad of a semiconductor chip. Placing the anisotropically conductive film side of the product obtained in the above step on the surface which is in the above step, and temporarily bonding the same through a binder of the above anisotropically conductive film, and inserting the through hole formed in the carrier film. The terminals formed on the wiring layer are pushed and deformed by the ultrasonic bonding and thermocompression bonding of the bonding tool, and the conductive particles are sandwiched between the terminal parts of the wiring layer and the chip electrode pads of the semiconductor chip for electrical connection. And a step of heating the binder to a temperature at which the binder is completely cured to complete the bonding.
【００１０】[0010]
【発明の実施の形態】以下、この発明の実施の形態を、
図面に基づいて説明する。図１（ａ）は、この発明の一
実施の形態としての半導体装置の平面図、図１（ｂ）
は、図１（ａ）のＡ−Ａ’矢視線断面図を示す。DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described.
This will be described with reference to the drawings. FIG. 1A is a plan view of a semiconductor device according to an embodiment of the present invention, and FIG.
1 shows a cross-sectional view taken along the line AA ′ of FIG.
【００１１】この半導体装置１００は、半導体チップ９
と、キャリアフィルム１とを主な要素として構成されて
いる。キャリアフィルム１は、ポリイミド系樹脂による
有機絶縁フィルム２と、この有機絶縁フィルム２上に同
等の金属泊をエッチング等の加工でパターン形成した配
線層３とからなる。配線層３には、半導体チップ９のチ
ップ電極パッド１０と接続される複数の端子部３ａが形
成されている。有機絶縁フィルム２には、端子部３ａの
形成された位置に対応させて複数のスルーホール７，１
２がレーザ加工またはエッチングにより形成されてい
る。また、スルーホール７にはメッキ等による金属物質
６が充填され、配線層３と外部との電気接続をするため
のバンプ電極５に接続されている。The semiconductor device 100 includes a semiconductor chip 9
And the carrier film 1 as main elements. The carrier film 1 is composed of an organic insulating film 2 made of a polyimide resin, and a wiring layer 3 in which an equivalent metal layer is formed on the organic insulating film 2 by patterning such as etching. A plurality of terminal portions 3 a connected to the chip electrode pads 10 of the semiconductor chip 9 are formed on the wiring layer 3. The organic insulating film 2 has a plurality of through holes 7, 1 corresponding to the positions where the terminal portions 3a are formed.
2 is formed by laser processing or etching. The through hole 7 is filled with a metal material 6 by plating or the like, and is connected to the bump electrode 5 for making an electrical connection between the wiring layer 3 and the outside.
【００１２】一方、半導体チップ９には、キャリアフィ
ルム１と貼り合わせる面に複数のチップ電極パッド１０
が配設されており、そのチップ電極パッド１０を除く領
域には、パッシベーション膜１１が形成されている。半
導体チップ９とキャリアフィルム１とは、ＡＣＦ４の接
着性樹脂からなるバインダ４ｂで接着されており、その
外周部は、封止樹脂１３で封止されている。On the other hand, the semiconductor chip 9 has a plurality of chip electrode pads 10 on the surface to be bonded to the carrier film 1.
Is provided, and a passivation film 11 is formed in a region excluding the chip electrode pad 10. The semiconductor chip 9 and the carrier film 1 are bonded with a binder 4b made of an adhesive resin of ACF4, and the outer peripheral portion is sealed with a sealing resin 13.
【００１３】また、チップ電極パッド１０と配線層３の
端子部３ａとの電気接続は、ＡＣＦ４の導電粒子４ａを
介して行われる。すなわち、チップ電極パッド１０が配
設された半導体チップ９と、導電粒子４ａを包含するＡ
ＣＦ４と、配線層３に形成された複数の端子部３ａと、
この配線層３が設けられたキャリアフィルム１とが重畳
されることによって、チップ電極パッド１０、導電粒子
４ａ、端子部３ａにより、電路が形成される。The electrical connection between the chip electrode pad 10 and the terminal portion 3a of the wiring layer 3 is made via the conductive particles 4a of the ACF 4. That is, the semiconductor chip 9 on which the chip electrode pads 10 are provided and the semiconductor chip 9 including the conductive particles 4a.
CF4, a plurality of terminal portions 3a formed on the wiring layer 3,
When the carrier film 1 on which the wiring layer 3 is provided is overlapped, an electric path is formed by the chip electrode pads 10, the conductive particles 4a, and the terminal portions 3a.
【００１４】図２は本構造を得るための製造方法を示し
ている。第１の実施形態として、まず、図２（ａ）のよ
うに、ダイシング済みの半導体チップ９のチップ電極パ
ッド１０が配設されている面にＡＣＦ４を載せ、加熱し
ながら押圧することにより半導体チップ９とＡＣＦ４と
を貼り合わせる。FIG. 2 shows a manufacturing method for obtaining this structure. As a first embodiment, first, as shown in FIG. 2A, the ACF4 is placed on the surface of the diced semiconductor chip 9 on which the chip electrode pads 10 are provided, and pressed while heating. 9 and ACF4 are bonded together.
【００１５】次に、図２（ｃ）のように、ＡＣＦ４の表
面にキャリアフィルム１の配線層３側を載せ、半導体チ
ップ９とキャリアフィルム１とに設けられた認識マーク
を使って、半導体チップ９とキャリアフィルム１とを高
精度に位置決めし、加熱しながら押圧することによりＡ
ＣＦ４のバインダ４ｂを介して半導体チップ９とキャリ
アフィルム１とを仮接着する。このとき、次の工程でボ
ンディングすることができるように、バインダ４ｂが完
全に硬化しない温度範囲で接着を行う。Next, as shown in FIG. 2 (c), the wiring layer 3 side of the carrier film 1 is placed on the surface of the ACF 4, and the semiconductor chip 9 and the recognition mark provided on the carrier film 1 are used. 9 and the carrier film 1 are positioned with high precision, and are pressed while heating.
The semiconductor chip 9 and the carrier film 1 are temporarily bonded via the binder 4b of CF4. At this time, bonding is performed in a temperature range where the binder 4b is not completely cured so that bonding can be performed in the next step.
【００１６】そして、図２（ｄ）のように、キャリアフ
ィルム１に形成されたスルーホール１２からボンディン
グツール１４を挿入し、、直接配線層３の端子部３ａを
一つ一つボンディングツール１４で超音波併合熱圧着す
ることにより端子部３ａを押し込み変形させ、ＡＣＦ４
の導電粒子４ａを挟み込んで配線層３の端子部３ａと半
導体チップ９のチップ電極パッド１０とを接合し、電気
導通させる。Then, as shown in FIG. 2D, a bonding tool 14 is inserted through a through hole 12 formed in the carrier film 1, and the terminal portions 3a of the direct wiring layer 3 are directly connected one by one with the bonding tool 14. The terminal portion 3a is pushed and deformed by ultrasonic combined thermocompression bonding, and the ACF 4
The terminal portions 3a of the wiring layer 3 and the chip electrode pads 10 of the semiconductor chip 9 are joined to each other with the conductive particles 4a interposed therebetween, thereby providing electrical conduction.
【００１７】最後に、図２（ｅ）のように、この発明の
半導体装置１００をＡＣＦ４のバインダ４ｂが硬化する
温度に加熱し、半導体チップ９とキャリアフィルム１と
の貼り合わせを完了する。Finally, as shown in FIG. 2E, the semiconductor device 100 of the present invention is heated to a temperature at which the binder 4b of the ACF 4 is cured, and the bonding of the semiconductor chip 9 and the carrier film 1 is completed.
【００１８】また、第２の実施形態として、図２（ｂ）
に示すように、まず初めにキャリアフィルム１の配線層
３側にＡＣＦ４を載せ、加熱しながら押圧することによ
りキャリアフィルム１とＡＣＦ４とを貼り合わせる。FIG. 2B shows a second embodiment.
As shown in (1), first, the ACF 4 is placed on the wiring layer 3 side of the carrier film 1, and the carrier film 1 and the ACF 4 are bonded by pressing while heating.
【００１９】そして、図２（ｃ）同様、半導体チップ９
のチップ電極パッド１０が配設されている表面に前記工
程で得られた製品のＡＣＦ４を載せ、ＡＣＦ４のバイン
ダ４ｂを介して仮接着し、以下前記第１の実施形態と同
様の工程を順次行い、半導体チップ９とキャリアフィル
ム１との貼り合わせを完了する。Then, similarly to FIG. 2C, the semiconductor chip 9
The ACF4 of the product obtained in the above step is placed on the surface on which the chip electrode pads 10 are provided, and temporarily bonded via a binder 4b of the ACF4, and the same steps as those in the first embodiment are sequentially performed. Then, the bonding of the semiconductor chip 9 and the carrier film 1 is completed.
【００２０】以上説明した上記の半導体装置及びその製
造方法によれば、次のような効果が得られる。まず、キ
ャリアフィルム１にあけられたスルーホール１２から、
直接配線層３の端子部３ａを一つ一つボンディングツー
ル１４で超音波併合熱圧着することができるので、押圧
面と半導体チップ９の上面との平行度調整を行う必要が
なく、接合装置の生産性を向上させることができる。According to the above-described semiconductor device and its manufacturing method, the following effects can be obtained. First, from the through hole 12 opened in the carrier film 1,
Since the terminal portions 3a of the direct wiring layer 3 can be bonded by ultrasonic bonding and thermocompression bonding one by one with the bonding tool 14, it is not necessary to adjust the parallelism between the pressing surface and the upper surface of the semiconductor chip 9, and the bonding device can be used. Productivity can be improved.
【００２１】また、配線層端子部３ａ以外の領域を電気
接続のために加圧することがないので、ＡＣＦ４の導電
粒子４ａによる端子部３ａ以外の領域でのショ−トの心
配がないため、金属バンプを形成する必要がなく、製造
コストを低減することができる。Further, since the area other than the wiring layer terminal section 3a is not pressurized for electrical connection, there is no fear of short-circuiting in the area other than the terminal section 3a due to the conductive particles 4a of the ACF 4, so that metal There is no need to form bumps, and manufacturing costs can be reduced.
【００２２】[0022]
【発明の効果】この発明の半導体装置及びその製造方法
によれば、有機絶縁フィルムに複数のスルーホールが形
成されているので、平行度調整を行う必要がなく、接合
装置の生産性を向上させることのできるという優れた効
果を得ることができる。According to the semiconductor device and the method of manufacturing the same of the present invention, since a plurality of through holes are formed in the organic insulating film, it is not necessary to adjust the parallelism, and the productivity of the joining device is improved. The excellent effect that it can be obtained can be obtained.
【００２３】また、有機絶縁フィルムに形成されたスル
ーホールから挿入されるボンディングツールの超音波併
合熱圧着によって、配線層に形成された端子部を押し込
み変形させ、配線層の端子部と半導体チップのチップ電
極パッドとの間に導電粒子を挟み込んで電気的接合を行
う段階を有するので、製造コストを上げる要因となる金
属バンプを形成する必要がなく、製造コストを削減でき
るという優れた効果を得ることができる。Also, the terminal portion formed in the wiring layer is pushed and deformed by ultrasonic bonding thermocompression of a bonding tool inserted from a through hole formed in the organic insulating film, so that the terminal portion of the wiring layer and the semiconductor chip are connected to each other. Since there is a step in which conductive particles are sandwiched between the chip electrode pads and electrical bonding is performed, there is no need to form metal bumps which increase manufacturing costs, and an excellent effect of reducing manufacturing costs can be obtained. Can be.
【図１】 この発明の一実施の形態を示す図であって、
（ａ）は平面図、（ｂ）はＡ−Ａ’矢視線断面図であ
る。FIG. 1 is a diagram showing an embodiment of the present invention,
(A) is a plan view, and (b) is a cross-sectional view taken along line AA '.
【図２】 この発明の一実施の形態を示す図であって、
（ａ）は半導体チップとＡＣＦとを貼り合わせる段階を
示す断面図、（ｂ）は他の実施の形態として最初にキャ
リアフィルムとＡＣＦとを貼り合わせる段階を示す断面
図、（ｃ）は半導体チップとキャリアフィルムとを高精
度に位置決めし、仮接着する段階を示す断面図、（ｄ）
は端子部を一つ一つボンディングツールで超音波併合熱
圧着する段階を示す断面図、（ｅ）はバインダが硬化す
る温度に加熱し、半導体チップとキャリアフィルムとの
貼り合わせを完了する段階を示す断面図である。FIG. 2 is a diagram showing an embodiment of the present invention,
(A) is a cross-sectional view showing a step of bonding a semiconductor chip and an ACF, (b) is a cross-sectional view showing a step of first bonding a carrier film and an ACF as another embodiment, and (c) is a semiconductor chip. Sectional view showing the step of positioning the carrier film and the carrier film with high precision and temporarily bonding them, (d)
FIG. 4 is a cross-sectional view showing the step of ultrasonically bonding and thermocompression bonding the terminal portions one by one with a bonding tool. FIG. FIG.
【図３】 従来の半導体装置を接合装置で接合する場合
の断面図である。FIG. 3 is a cross-sectional view when a conventional semiconductor device is joined by a joining device.
１ キャリアフィルム ３ 配線層 ３ａ 端子部 ４ 異方導電性フィルム（ＡＣＦ） ４ａ 導電粒子 ４ｂ バインダ ７ スルーホール ９ 半導体チップ １０ チップ電極パッド １２ スルーホール １４ ボンディングツール １００ 半導体装置 DESCRIPTION OF SYMBOLS 1 Carrier film 3 Wiring layer 3a Terminal part 4 Anisotropic conductive film (ACF) 4a Conductive particle 4b Binder 7 Through hole 9 Semiconductor chip 10 Chip electrode pad 12 Through hole 14 Bonding tool 100 Semiconductor device
Claims (3)
と、 導電粒子を包含する異方導電性フィルムと、 配線層に形成された複数の端子部と、 該配線層が形成されたキャリアフィルムと、を順次重畳
させて電路が形成される半導体装置において、 前記キャリアフィルムには、前記端子部の形成された位
置に対応させて複数のスルーホールが形成されているこ
とを特徴とする半導体装置。1. A semiconductor chip, a plurality of chip electrode pads provided on the semiconductor chip, an anisotropic conductive film containing conductive particles, a plurality of terminal portions formed on a wiring layer, and the wiring In a semiconductor device in which an electric circuit is formed by sequentially superimposing a carrier film on which a layer is formed, a plurality of through holes are formed in the carrier film corresponding to positions where the terminal portions are formed. A semiconductor device characterized by the above-mentioned.
されている表面に異方導電性フィルムを載置し、貼り合
わせる工程と、 前記異方導電性フィルムの表面にキャリアフィルムの配
線層側を載置し、前記異方導電性フィルムのバインダを
介して仮接着される工程と、 キャリアフィルムに形成されたスルーホールから挿入さ
れるボンディングツールの超音波併合熱圧着によって、
配線層に形成された端子部を押し込み変形させ、配線層
の端子部と半導体チップのチップ電極パッドとの間に導
電粒子を挟み込んで電気的接合を行う工程と、 前記バインダが完全に硬化する温度に加熱し、貼り合わ
せを完了する工程と、を有することを特徴とする半導体
装置の製造方法。2. A step of placing and bonding an anisotropic conductive film on a surface of a semiconductor chip on which chip electrode pads are provided, and applying a wiring layer side of a carrier film on the surface of the anisotropic conductive film. Placed and temporarily bonded via a binder of the anisotropic conductive film, by ultrasonic bonding thermocompression bonding of a bonding tool inserted from a through hole formed in the carrier film,
A step of pressing and deforming the terminal portion formed on the wiring layer and sandwiching conductive particles between the terminal portion of the wiring layer and the chip electrode pad of the semiconductor chip, and a temperature at which the binder is completely cured. And a step of completing bonding by heating the semiconductor device.
性フィルムを載置し、貼り合わせる工程と、 半導体チップのチップ電極パッドが配設されている表面
に前記工程で得られた製品の異方導電性フィルム側を載
置し、前記異方導電性フィルムのバインダを介して仮接
着される工程と、 キャリアフィルムに形成されたスルーホールから挿入さ
れるボンディングツールの超音波併合熱圧着によって、
配線層に形成された端子部を押し込み変形させ、配線層
の端子部と半導体チップのチップ電極パッドとの間に導
電粒子を挟み込んで電気的接合を行う工程と、 前記バインダが完全に硬化する温度に加熱し、貼り合わ
せを完了する工程と、を有することを特徴とする半導体
装置の製造方法。3. A step of placing and bonding an anisotropic conductive film on the wiring layer side of a carrier film, and a step of attaching a product obtained in said step to a surface of a semiconductor chip on which chip electrode pads are provided. The step of placing the conductive film side and temporarily bonding via a binder of the anisotropic conductive film, and ultrasonic bonding thermocompression bonding of a bonding tool inserted from a through hole formed in the carrier film,
A step of pressing and deforming the terminal portion formed on the wiring layer and sandwiching conductive particles between the terminal portion of the wiring layer and the chip electrode pad of the semiconductor chip, and a temperature at which the binder is completely cured. And a step of completing bonding by heating the semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17782898A JP2000012626A (en) | 1998-06-24 | 1998-06-24 | Semiconductor device and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17782898A JP2000012626A (en) | 1998-06-24 | 1998-06-24 | Semiconductor device and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2000012626A true JP2000012626A (en) | 2000-01-14 |
Family
ID=16037827
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17782898A Pending JP2000012626A (en) | 1998-06-24 | 1998-06-24 | Semiconductor device and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2000012626A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2007036994A1 (en) * | 2005-09-28 | 2007-04-05 | Spansion Llc | Semiconductor device, its fabrication method, and film fabrication method |
-
1998
- 1998-06-24 JP JP17782898A patent/JP2000012626A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2007036994A1 (en) * | 2005-09-28 | 2007-04-05 | Spansion Llc | Semiconductor device, its fabrication method, and film fabrication method |
| US7683473B2 (en) | 2005-09-28 | 2010-03-23 | Spansion Llc | Semiconductor device, fabrication method therefor, and film fabrication method |
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