Classifications

• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C8/00—Arrangements for selecting an address in a digital store
  • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
  • G11C16/06—Auxiliary circuits, e.g. for writing into memory
  • G11C16/08—Address circuits; Decoders; Word-line control circuits
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C2216/00—Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
  • G11C2216/12—Reading and writing aspects of erasable programmable read-only memories
  • G11C2216/22—Nonvolatile memory in which reading can be carried out from one memory bank or array whilst a word or sector in another bank or array is being erased or programmed simultaneously

Landscapes

• Engineering & Computer Science (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Read Only Memory (AREA)
• Semiconductor Memories (AREA)

Priority Applications (2)

Applications Claiming Priority (1)

Publications (2)

Family

ID=11455753

Family Applications (1)

Country Status (2)

Families Citing this family (11)

Family Cites Families (5)

• 2001
  • 2001-08-30 IT IT2001RM000524A patent/ITRM20010524A1/it unknown
• 2002
  • 2002-08-29 US US10/231,449 patent/US6697284B2/en not_active Expired - Lifetime

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