ITRM20010524A1 - Struttura a schiera di memoria flash. - Google Patents
Struttura a schiera di memoria flash.Info
- Publication number
- ITRM20010524A1 ITRM20010524A1 IT2001RM000524A ITRM20010524A ITRM20010524A1 IT RM20010524 A1 ITRM20010524 A1 IT RM20010524A1 IT 2001RM000524 A IT2001RM000524 A IT 2001RM000524A IT RM20010524 A ITRM20010524 A IT RM20010524A IT RM20010524 A1 ITRM20010524 A1 IT RM20010524A1
- Authority
- IT
- Italy
- Prior art keywords
- flash memory
- table structure
- memory table
- flash
- memory
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2216/00—Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
- G11C2216/12—Reading and writing aspects of erasable programmable read-only memories
- G11C2216/22—Nonvolatile memory in which reading can be carried out from one memory bank or array whilst a word or sector in another bank or array is being erased or programmed simultaneously
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Read Only Memory (AREA)
- Semiconductor Memories (AREA)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
IT2001RM000524A ITRM20010524A1 (it) | 2001-08-30 | 2001-08-30 | Struttura a schiera di memoria flash. |
US10/231,449 US6697284B2 (en) | 2001-08-30 | 2002-08-29 | Flash memory array structure |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
IT2001RM000524A ITRM20010524A1 (it) | 2001-08-30 | 2001-08-30 | Struttura a schiera di memoria flash. |
Publications (2)
Publication Number | Publication Date |
---|---|
ITRM20010524A0 ITRM20010524A0 (it) | 2001-08-30 |
ITRM20010524A1 true ITRM20010524A1 (it) | 2003-02-28 |
Family
ID=11455753
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
IT2001RM000524A ITRM20010524A1 (it) | 2001-08-30 | 2001-08-30 | Struttura a schiera di memoria flash. |
Country Status (2)
Country | Link |
---|---|
US (1) | US6697284B2 (it) |
IT (1) | ITRM20010524A1 (it) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
ITRM20010516A1 (it) | 2001-08-29 | 2003-02-28 | Micron Technology Inc | Architettura a schiera di memorie flash. |
US7210002B2 (en) * | 2003-11-19 | 2007-04-24 | Qualcomm Incorporated | System and method for operating dual bank read-while-write flash |
US7263027B2 (en) * | 2004-10-14 | 2007-08-28 | Broadcom Corporation | Integrated circuit chip having non-volatile on-chip memories for providing programmable functions and features |
US7268023B2 (en) * | 2005-05-05 | 2007-09-11 | Micron Technology, Inc. | Method of forming a pseudo SOI substrate and semiconductor devices |
US20100287217A1 (en) * | 2009-04-08 | 2010-11-11 | Google Inc. | Host control of background garbage collection in a data storage device |
US8566508B2 (en) * | 2009-04-08 | 2013-10-22 | Google Inc. | RAID configuration in a flash memory data storage device |
US8447918B2 (en) * | 2009-04-08 | 2013-05-21 | Google Inc. | Garbage collection for failure prediction and repartitioning |
US20100262979A1 (en) * | 2009-04-08 | 2010-10-14 | Google Inc. | Circular command queues for communication between a host and a data storage device |
KR101997623B1 (ko) * | 2013-02-26 | 2019-07-09 | 삼성전자주식회사 | 메모리 장치 및 그것을 포함하는 메모리 시스템 |
JP6122478B1 (ja) * | 2015-10-22 | 2017-04-26 | ウィンボンド エレクトロニクス コーポレーション | 不揮発性半導体記憶装置 |
US11335402B2 (en) * | 2018-12-19 | 2022-05-17 | Micron Technology, Inc. | Systems and techniques for accessing multiple memory cells concurrently |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5384745A (en) | 1992-04-27 | 1995-01-24 | Mitsubishi Denki Kabushiki Kaisha | Synchronous semiconductor memory device |
JP3346827B2 (ja) | 1993-05-25 | 2002-11-18 | 三菱電機株式会社 | 同期型半導体記憶装置 |
JPH09288888A (ja) * | 1996-04-22 | 1997-11-04 | Mitsubishi Electric Corp | 半導体記憶装置 |
KR100313503B1 (ko) * | 1999-02-12 | 2001-11-07 | 김영환 | 멀티-뱅크 메모리 어레이를 갖는 반도체 메모리 장치 |
US6459645B2 (en) * | 1999-09-30 | 2002-10-01 | Intel Corporation | VPX bank architecture |
-
2001
- 2001-08-30 IT IT2001RM000524A patent/ITRM20010524A1/it unknown
-
2002
- 2002-08-29 US US10/231,449 patent/US6697284B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
ITRM20010524A0 (it) | 2001-08-30 |
US20030058689A1 (en) | 2003-03-27 |
US6697284B2 (en) | 2004-02-24 |
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