DE60233624D1 - Speicheranordnung - Google Patents

Speicheranordnung

Info

Publication number
DE60233624D1
DE60233624D1 DE60233624T DE60233624T DE60233624D1 DE 60233624 D1 DE60233624 D1 DE 60233624D1 DE 60233624 T DE60233624 T DE 60233624T DE 60233624 T DE60233624 T DE 60233624T DE 60233624 D1 DE60233624 D1 DE 60233624D1
Authority
DE
Germany
Prior art keywords
memory array
array
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE60233624T
Other languages
English (en)
Inventor
Tetsuya Uemura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Application granted granted Critical
Publication of DE60233624D1 publication Critical patent/DE60233624D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/36Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using diodes, e.g. as threshold elements, i.e. diodes assuming a stable ON-stage when driven above their threshold (S- or N-characteristic)
    • G11C11/38Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using diodes, e.g. as threshold elements, i.e. diodes assuming a stable ON-stage when driven above their threshold (S- or N-characteristic) using tunnel diodes
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/36Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using diodes, e.g. as threshold elements, i.e. diodes assuming a stable ON-stage when driven above their threshold (S- or N-characteristic)
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2211/00Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/561Multilevel memory cell aspects
    • G11C2211/5614Multilevel memory cell comprising negative resistance, quantum tunneling or resonance tunneling elements

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Semiconductor Memories (AREA)
  • Static Random-Access Memory (AREA)
DE60233624T 2001-08-06 2002-07-18 Speicheranordnung Expired - Fee Related DE60233624D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001237285A JP2003051184A (ja) 2001-08-06 2001-08-06 メモリ装置

Publications (1)

Publication Number Publication Date
DE60233624D1 true DE60233624D1 (de) 2009-10-22

Family

ID=19068392

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60233624T Expired - Fee Related DE60233624D1 (de) 2001-08-06 2002-07-18 Speicheranordnung

Country Status (8)

Country Link
US (1) US6765822B2 (de)
EP (1) EP1288960B1 (de)
JP (1) JP2003051184A (de)
KR (1) KR100497072B1 (de)
CN (1) CN1307646C (de)
DE (1) DE60233624D1 (de)
HK (1) HK1054275B (de)
TW (1) TW552679B (de)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7095659B2 (en) * 2002-06-28 2006-08-22 Progressant Technologies, Inc. Variable voltage supply bias and methods for negative differential resistance (NDR) based memory device
JP4079910B2 (ja) * 2004-05-28 2008-04-23 富士通株式会社 強誘電体メモリ
US20060049464A1 (en) 2004-09-03 2006-03-09 Rao G R Mohan Semiconductor devices with graded dopant regions
KR101108418B1 (ko) * 2004-12-22 2012-01-30 엘지디스플레이 주식회사 와이어 고정수단을 구비하는 액정표시장치
FR2890483A1 (fr) * 2005-09-08 2007-03-09 St Microelectronics Sa Cellule memoire volatile remanente
KR100668347B1 (ko) * 2005-10-13 2007-01-12 삼성전자주식회사 금속-절연체 천이막 저항체를 포함하는 반도체 메모리 소자
US7508701B1 (en) * 2006-11-29 2009-03-24 The Board Of Trustees Of The Leland Stanford Junior University Negative differential resistance devices and approaches therefor
WO2009002748A1 (en) * 2007-06-22 2008-12-31 Nantero, Inc. Two-terminal nanotube devices including a nanotube bridge and methods of making same
US8194435B2 (en) * 2009-12-09 2012-06-05 Yen-Wei Hsu Memory Device
US11984163B2 (en) 2013-03-15 2024-05-14 Hefei Reliance Memory Limited Processing unit with fast read speed memory device
US9230641B2 (en) * 2013-03-15 2016-01-05 Rambus Inc. Fast read speed memory device
KR101512245B1 (ko) * 2013-12-04 2015-04-16 한국과학기술원 부성 미분 저항 소자 기반 가변 반사형 증폭기 회로
WO2015138731A1 (en) * 2014-03-12 2015-09-17 QuTel, Inc. Compact memory structure including tunneling diode
EP3167486A4 (de) * 2014-07-08 2018-07-11 Intel Corporation Speicher auf basis von negativem differentiellem widerstand

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0661454A (ja) 1992-08-10 1994-03-04 Hitachi Ltd 半導体集積回路装置
JP3224306B2 (ja) 1992-09-04 2001-10-29 富士通株式会社 半導体メモリ装置
JPH06112438A (ja) 1992-09-25 1994-04-22 Fujitsu Ltd 記憶装置、その情報読出し方法、情報書込み方法および記憶装置の製造方法
JPH0778945A (ja) 1993-09-08 1995-03-20 Fujitsu Ltd 負性抵抗ダイオードメモリ
US5535156A (en) * 1994-05-05 1996-07-09 California Institute Of Technology Transistorless, multistable current-mode memory cells and memory arrays and methods of reading and writing to the same
US5684737A (en) * 1995-12-08 1997-11-04 The Regents Of The University Of California SRAM cell utilizing bistable diode having GeSi structure therein
EP0817199B1 (de) * 1996-07-01 2002-11-27 Texas Instruments Incorporated Verbesserungen betreffend elektronische Schaltungen
US5883829A (en) * 1997-06-27 1999-03-16 Texas Instruments Incorporated Memory cell having negative differential resistance devices
JP3475851B2 (ja) 1999-04-28 2003-12-10 日本電気株式会社 フリップフロップ回路

Also Published As

Publication number Publication date
JP2003051184A (ja) 2003-02-21
US6765822B2 (en) 2004-07-20
HK1054275A1 (en) 2003-11-21
CN1402256A (zh) 2003-03-12
EP1288960A1 (de) 2003-03-05
CN1307646C (zh) 2007-03-28
EP1288960B1 (de) 2009-09-09
US20030026126A1 (en) 2003-02-06
TW552679B (en) 2003-09-11
KR100497072B1 (ko) 2005-06-23
HK1054275B (zh) 2007-07-20
KR20030014594A (ko) 2003-02-19

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee