ITMI20080017A1 - Sistemi di memoria e schede di memoria che utilizzano un blocco cattivo a causa di un guasto di programmazione al suo interno in modalita' di cella a singolo livello e metodi di azionamento dei medesimi. - Google Patents

Sistemi di memoria e schede di memoria che utilizzano un blocco cattivo a causa di un guasto di programmazione al suo interno in modalita' di cella a singolo livello e metodi di azionamento dei medesimi.

Info

Publication number
ITMI20080017A1
ITMI20080017A1 IT000017A ITMI20080017A ITMI20080017A1 IT MI20080017 A1 ITMI20080017 A1 IT MI20080017A1 IT 000017 A IT000017 A IT 000017A IT MI20080017 A ITMI20080017 A IT MI20080017A IT MI20080017 A1 ITMI20080017 A1 IT MI20080017A1
Authority
IT
Italy
Prior art keywords
interior
same
level cell
bad block
memory
Prior art date
Application number
IT000017A
Other languages
English (en)
Inventor
Bong-Ryeol Lee
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of ITMI20080017A1 publication Critical patent/ITMI20080017A1/it

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/564—Miscellaneous aspects
    • G11C2211/5641—Multilevel memory having cells with different number of storage levels

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Read Only Memory (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
IT000017A 2007-01-31 2008-01-08 Sistemi di memoria e schede di memoria che utilizzano un blocco cattivo a causa di un guasto di programmazione al suo interno in modalita' di cella a singolo livello e metodi di azionamento dei medesimi. ITMI20080017A1 (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020070010155A KR100823170B1 (ko) 2007-01-31 2007-01-31 배드 블록을 싱글 레벨 셀 모드로 사용하는 메모리 시스템및 메모리 카드

Publications (1)

Publication Number Publication Date
ITMI20080017A1 true ITMI20080017A1 (it) 2008-08-01

Family

ID=39571847

Family Applications (1)

Application Number Title Priority Date Filing Date
IT000017A ITMI20080017A1 (it) 2007-01-31 2008-01-08 Sistemi di memoria e schede di memoria che utilizzano un blocco cattivo a causa di un guasto di programmazione al suo interno in modalita' di cella a singolo livello e metodi di azionamento dei medesimi.

Country Status (3)

Country Link
US (1) US7505338B2 (it)
KR (1) KR100823170B1 (it)
IT (1) ITMI20080017A1 (it)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8259497B2 (en) 2007-08-06 2012-09-04 Apple Inc. Programming schemes for multi-level analog memory cells
US8891298B2 (en) * 2011-07-19 2014-11-18 Greenthread, Llc Lifetime mixed level non-volatile memory system
KR101515098B1 (ko) 2008-11-20 2015-04-24 삼성전자주식회사 플래시 메모리 장치 및 이의 독출 방법
KR101005120B1 (ko) * 2009-02-04 2011-01-04 주식회사 하이닉스반도체 불휘발성 메모리 소자의 프로그램 방법
JP5204069B2 (ja) * 2009-09-18 2013-06-05 株式会社東芝 不揮発性半導体記憶装置
US9165677B2 (en) * 2011-05-17 2015-10-20 Maxlinear, Inc. Method and apparatus for memory fault tolerance
US8797813B2 (en) 2011-05-17 2014-08-05 Maxlinear, Inc. Method and apparatus for memory power and/or area reduction
US10379971B2 (en) 2012-01-31 2019-08-13 Hewlett Packard Enterprise Development Lp Single and double chip space
CN104081373B (zh) * 2012-01-31 2016-09-21 惠普发展公司，有限责任合伙企业 单芯片和双芯片备援
KR101989018B1 (ko) * 2012-06-25 2019-06-13 에스케이하이닉스 주식회사 데이터 저장 장치의 동작 방법
KR20180062513A (ko) * 2016-11-30 2018-06-11 에스케이하이닉스 주식회사 반도체 장치, 그를 포함하는 반도체 시스템 및 그 반도체 시스템의 구동 방법
KR20180087494A (ko) * 2017-01-23 2018-08-02 에스케이하이닉스 주식회사 메모리 장치, 메모리 시스템 및 메모리 시스템의 동작 방법
KR102316532B1 (ko) * 2021-05-24 2021-10-22 한양대학교 산학협력단 플래시 메모리에서의 런타임 배드 블록 관리 방법

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
ATE225961T1 (de) * 1996-08-16 2002-10-15 Tokyo Electron Device Ltd Halbleiterspeicheranordnung mit fehlerdetektion und -korrektur
US6574746B1 (en) 1999-07-02 2003-06-03 Sun Microsystems, Inc. System and method for improving multi-bit error protection in computer memory systems
KR100391154B1 (ko) 2001-05-14 2003-07-12 삼성전자주식회사 불휘발성 반도체 메모리 장치의 프로그램 방법 및 장치
JP4260434B2 (ja) * 2002-07-16 2009-04-30 富士通マイクロエレクトロニクス株式会社 不揮発性半導体メモリ及びその動作方法
KR101050623B1 (ko) * 2004-04-28 2011-07-19 삼성전자주식회사 Ｎａｎｄ 플래시 메모리 블록의 오류 복구 방법
US7313649B2 (en) * 2004-04-28 2007-12-25 Matsushita Electric Industrial Co., Ltd. Flash memory and program verify method for flash memory
KR100572328B1 (ko) * 2004-07-16 2006-04-18 삼성전자주식회사 배드 블록 관리부를 포함하는 플래시 메모리 시스템
KR100680479B1 (ko) 2005-04-11 2007-02-08 주식회사 하이닉스반도체 비휘발성 메모리 장치의 프로그램 검증 방법
KR101080912B1 (ko) 2005-04-11 2011-11-09 주식회사 하이닉스반도체 멀티 레벨 셀을 갖는 비휘발성 메모리 장치의 프로그램방법
KR100732628B1 (ko) * 2005-07-28 2007-06-27 삼성전자주식회사 멀티-비트 데이터 및 싱글-비트 데이터를 저장하는 플래시메모리 장치

Also Published As

Publication number Publication date
US20080181015A1 (en) 2008-07-31
US7505338B2 (en) 2009-03-17
KR100823170B1 (ko) 2008-04-21

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