ITMI20021098A1 - Struttura integrata atta a realizzare all'interno di una sacca dielettricamente isolata un componente mos - Google Patents

Struttura integrata atta a realizzare all'interno di una sacca dielettricamente isolata un componente mos

Info

Publication number
ITMI20021098A1
ITMI20021098A1 IT2002MI001098A ITMI20021098A ITMI20021098A1 IT MI20021098 A1 ITMI20021098 A1 IT MI20021098A1 IT 2002MI001098 A IT2002MI001098 A IT 2002MI001098A IT MI20021098 A ITMI20021098 A IT MI20021098A IT MI20021098 A1 ITMI20021098 A1 IT MI20021098A1
Authority
IT
Italy
Prior art keywords
create
integrated structure
component inside
insulated bag
dielectrically insulated
Prior art date
Application number
IT2002MI001098A
Other languages
English (en)
Inventor
Salvatore Leonardi
Original Assignee
St Microelectronics Srl
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by St Microelectronics Srl filed Critical St Microelectronics Srl
Priority to IT2002MI001098A priority Critical patent/ITMI20021098A1/it
Publication of ITMI20021098A0 publication Critical patent/ITMI20021098A0/it
Priority to US10/442,646 priority patent/US6900504B2/en
Publication of ITMI20021098A1 publication Critical patent/ITMI20021098A1/it

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78612Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing the kink- or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76283Lateral isolation by refilling of trenches with dielectric material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692Surface layout
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107Substrate region of field-effect devices
    • H01L29/1075Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H01L29/1087Substrate region of field-effect devices of field-effect transistors with insulated gate characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)
IT2002MI001098A 2002-05-22 2002-05-22 Struttura integrata atta a realizzare all'interno di una sacca dielettricamente isolata un componente mos ITMI20021098A1 (it)

Priority Applications (2)

Application Number Priority Date Filing Date Title
IT2002MI001098A ITMI20021098A1 (it) 2002-05-22 2002-05-22 Struttura integrata atta a realizzare all'interno di una sacca dielettricamente isolata un componente mos
US10/442,646 US6900504B2 (en) 2002-05-22 2003-05-21 Integrated structure effective to form a MOS component in a dielectrically insulated well

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT2002MI001098A ITMI20021098A1 (it) 2002-05-22 2002-05-22 Struttura integrata atta a realizzare all'interno di una sacca dielettricamente isolata un componente mos

Publications (2)

Publication Number Publication Date
ITMI20021098A0 ITMI20021098A0 (it) 2002-05-22
ITMI20021098A1 true ITMI20021098A1 (it) 2003-11-24

Family

ID=11449951

Family Applications (1)

Application Number Title Priority Date Filing Date
IT2002MI001098A ITMI20021098A1 (it) 2002-05-22 2002-05-22 Struttura integrata atta a realizzare all'interno di una sacca dielettricamente isolata un componente mos

Country Status (2)

Country Link
US (1) US6900504B2 (it)
IT (1) ITMI20021098A1 (it)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1696485A1 (en) * 2005-02-24 2006-08-30 STMicroelectronics S.r.l. Process for manufacturing semiconductor devices in a SOI substrate with alignment marks
DE102006027504A1 (de) * 2006-06-14 2007-12-27 X-Fab Semiconductor Foundries Ag Randabschlussstruktur von MOS-Leistungstransistoren hoher Spannungen
EP1873822A1 (en) * 2006-06-27 2008-01-02 STMicroelectronics S.r.l. Front-rear contacts of electronics devices with induced defects to increase conductivity thereof
US9960251B2 (en) 2015-03-19 2018-05-01 Nxp Usa, Inc. ESD protection structure and method of fabrication thereof
US10037986B2 (en) * 2015-03-19 2018-07-31 Nxp Usa, Inc. ESD protection structure and method of fabrication thereof

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6268630B1 (en) * 1999-03-16 2001-07-31 Sandia Corporation Silicon-on-insulator field effect transistor with improved body ties for rad-hard applications
JP4231612B2 (ja) * 2000-04-26 2009-03-04 株式会社ルネサステクノロジ 半導体集積回路
US6455902B1 (en) * 2000-12-06 2002-09-24 International Business Machines Corporation BiCMOS ESD circuit with subcollector/trench-isolated body mosfet for mixed signal analog/digital RF applications

Also Published As

Publication number Publication date
US6900504B2 (en) 2005-05-31
ITMI20021098A0 (it) 2002-05-22
US20040021169A1 (en) 2004-02-05

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