IT1295910B1 - Circuito di lettura per memorie non volatili - Google Patents

Circuito di lettura per memorie non volatili

Info

Publication number
IT1295910B1
IT1295910B1 IT97MI002458A ITMI972458A IT1295910B1 IT 1295910 B1 IT1295910 B1 IT 1295910B1 IT 97MI002458 A IT97MI002458 A IT 97MI002458A IT MI972458 A ITMI972458 A IT MI972458A IT 1295910 B1 IT1295910 B1 IT 1295910B1
Authority
IT
Italy
Prior art keywords
reading circuit
volatile memories
memories
volatile
reading
Prior art date
Application number
IT97MI002458A
Other languages
English (en)
Inventor
Placa Michele La
Original Assignee
Sgs Thomson Microelectronics
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sgs Thomson Microelectronics filed Critical Sgs Thomson Microelectronics
Priority to IT97MI002458A priority Critical patent/IT1295910B1/it
Priority to US09/182,843 priority patent/US6097633A/en
Publication of ITMI972458A1 publication Critical patent/ITMI972458A1/it
Application granted granted Critical
Publication of IT1295910B1 publication Critical patent/IT1295910B1/it

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/062—Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G11C16/28—Sensing or reading circuits; Data output circuits using differential sensing or reference cells, e.g. dummy cells
IT97MI002458A 1997-10-31 1997-10-31 Circuito di lettura per memorie non volatili IT1295910B1 (it)

Priority Applications (2)

Application Number Priority Date Filing Date Title
IT97MI002458A IT1295910B1 (it) 1997-10-31 1997-10-31 Circuito di lettura per memorie non volatili
US09/182,843 US6097633A (en) 1997-10-31 1998-10-29 Read circuit for non-volatile memories

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT97MI002458A IT1295910B1 (it) 1997-10-31 1997-10-31 Circuito di lettura per memorie non volatili

Publications (2)

Publication Number Publication Date
ITMI972458A1 ITMI972458A1 (it) 1999-05-01
IT1295910B1 true IT1295910B1 (it) 1999-05-28

Family

ID=11378145

Family Applications (1)

Application Number Title Priority Date Filing Date
IT97MI002458A IT1295910B1 (it) 1997-10-31 1997-10-31 Circuito di lettura per memorie non volatili

Country Status (2)

Country Link
US (1) US6097633A (it)
IT (1) IT1295910B1 (it)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3886669B2 (ja) * 1999-06-10 2007-02-28 株式会社東芝 半導体記憶装置
TW514923B (en) * 1999-07-13 2002-12-21 Sanyo Electric Co Semiconductor memory device
US6744671B2 (en) * 2000-12-29 2004-06-01 Intel Corporation Kicker for non-volatile memory drain bias
US6477086B2 (en) 2000-12-29 2002-11-05 Intel Corporation Local sensing of non-volatile memory
US6570789B2 (en) 2000-12-29 2003-05-27 Intel Corporation Load for non-volatile memory drain bias
US6535423B2 (en) 2000-12-29 2003-03-18 Intel Corporation Drain bias for non-volatile memory
US6456540B1 (en) 2001-01-30 2002-09-24 Intel Corporation Method and apparatus for gating a global column select line with address transition detection
KR100382734B1 (ko) * 2001-02-26 2003-05-09 삼성전자주식회사 전류소모가 작고 ｄｃ전류가 작은 반도체 메모리장치의입출력라인 감지증폭기
US6906951B2 (en) * 2001-06-14 2005-06-14 Multi Level Memory Technology Bit line reference circuits for binary and multiple-bit-per-cell memories
JP4049604B2 (ja) * 2002-04-03 2008-02-20 株式会社ルネサステクノロジ 薄膜磁性体記憶装置
ITTO20030121A1 (it) * 2003-02-18 2004-08-19 St Microelectronics Srl Amplificatore di lettura di celle di memoria non volatili a
CA2473370C (en) * 2003-07-10 2007-04-10 Providence Health System-Oregon, An Oregon Non Profit Corporation Method for decreasing bioprosthetic implant failure
US7312641B2 (en) * 2004-12-28 2007-12-25 Spansion Llc Sense amplifiers with high voltage swing
CN101208754B (zh) 2005-06-28 2011-02-02 斯班逊有限公司 半导体器件及其控制方法
WO2007017926A1 (ja) * 2005-08-08 2007-02-15 Spansion Llc 半導体装置およびその制御方法
US7876611B2 (en) * 2008-08-08 2011-01-25 Sandisk Corporation Compensating for coupling during read operations in non-volatile storage

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5396467A (en) * 1994-03-30 1995-03-07 United Microelectronics Corp. Sense amplifier
DE69621323T2 (de) * 1995-02-10 2002-09-05 Micron Technology Inc Schneller leseverstärker für einen flash-speicher
EP0740307B1 (en) * 1995-04-28 2001-12-12 STMicroelectronics S.r.l. Sense amplifier circuit for semiconductor memory devices
JP2800740B2 (ja) * 1995-09-28 1998-09-21 日本電気株式会社 半導体記憶装置
DE69626099T2 (de) * 1996-03-29 2003-11-27 St Microelectronics Srl Leseverstärker mit Verstärkungsmodulation, insbesondere für Speicheranordnungen
DE69630024D1 (de) * 1996-06-18 2003-10-23 St Microelectronics Srl Nichtflüchtiger Speicher mit Einzelzellenreferenzsignalgeneratorschaltung zum Auslesen von Speicherzellen

Also Published As

Publication number Publication date
US6097633A (en) 2000-08-01
ITMI972458A1 (it) 1999-05-01

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Legal Events

Date Code Title Description
0001 Granted