IN165798B - - Google Patents

Info

Publication number
IN165798B
IN165798B IN647/CAL/86A IN647CA1986A IN165798B IN 165798 B IN165798 B IN 165798B IN 647CA1986 A IN647CA1986 A IN 647CA1986A IN 165798 B IN165798 B IN 165798B
Authority
IN
India
Prior art keywords
memory
data signal
counter
data
accepting
Prior art date
Application number
IN647/CAL/86A
Inventor
Karl-Heinz Michels-Krohn
Josef Untergruber
Angela Untergruber
Original Assignee
Siemens Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Ag filed Critical Siemens Ag
Publication of IN165798B publication Critical patent/IN165798B/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/42—Loop networks
    • H04L12/427—Loop networks with decentralised control
    • H04L12/433—Loop networks with decentralised control with asynchronous transmission, e.g. token ring, register insertion

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Small-Scale Networks (AREA)
  • Communication Control (AREA)
  • Arrangements For Transmission Of Measured Signals (AREA)
  • Exchange Systems With Centralized Control (AREA)
  • Emergency Protection Circuit Devices (AREA)
  • Selective Calling Equipment (AREA)

Abstract

A data transmission system has a number of control devices connected via a transmission loop. Each control device includes signal processing circuitry which compiles data signals to be transmitted in the form of a data signal block. The signal processing circuitry is followed by a transmit buffer, which includes a write/read memory. A prepared data signal block can be accepted into this memory. A counter is connected to the memory which continuously addresses the memory for accepting a data signal block, and for emission thereof to the loop upon the appearance of a transmit authorization signal. The write/read memory is followed by a register. In addition to memory locations for accepting a data signal word, this register additionally includes memory locations for auxiliary information to be attached to the individual data signal words. The auxiliary information is derived from counter readings of the counter.
IN647/CAL/86A 1985-09-11 1986-08-26 IN165798B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE3532442 1985-09-11

Publications (1)

Publication Number Publication Date
IN165798B true IN165798B (en) 1990-01-13

Family

ID=6280693

Family Applications (1)

Application Number Title Priority Date Filing Date
IN647/CAL/86A IN165798B (en) 1985-09-11 1986-08-26

Country Status (13)

Country Link
US (1) US4700020A (en)
EP (1) EP0214475B1 (en)
JP (1) JPS6261497A (en)
AT (1) ATE64803T1 (en)
AU (1) AU590794B2 (en)
BR (1) BR8604335A (en)
CA (1) CA1267232A (en)
DE (1) DE3679948D1 (en)
ES (1) ES2002315A6 (en)
GR (1) GR862299B (en)
IN (1) IN165798B (en)
PT (1) PT83340B (en)
ZA (1) ZA866883B (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0214476B1 (en) * 1985-09-11 1991-06-26 Siemens Aktiengesellschaft Method and circuit arrangement for the transmission of data signals between two control devices within a loop system
US6192438B1 (en) * 1998-09-18 2001-02-20 Lg Information & Communications, Ltd. U-interface matching circuit and method
DE10343172B4 (en) * 2003-09-18 2016-02-11 Robert Bosch Gmbh Data link having means for checking data integrity

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS607812B2 (en) * 1977-07-11 1985-02-27 富士電機株式会社 Data buffering device
US4292623A (en) * 1979-06-29 1981-09-29 International Business Machines Corporation Port logic for a communication bus system
US4340776A (en) * 1980-10-29 1982-07-20 Siemens Corporation Modular telecommunication system
DE3136586A1 (en) * 1981-09-15 1983-03-31 Siemens AG, 1000 Berlin und 8000 München Method and circuit arrangement for transmitting signals between any control devices of a clock-controlled highway system which is operated as a function of direction
JPS60132441A (en) * 1983-12-21 1985-07-15 Hitachi Ltd Data transmission method
EP0150084B1 (en) * 1984-01-03 1991-05-29 Texas Instruments Incorporated Architecture for intelligent control of data communication adapters

Also Published As

Publication number Publication date
AU6253486A (en) 1987-03-12
ES2002315A6 (en) 1988-08-01
EP0214475B1 (en) 1991-06-26
EP0214475A1 (en) 1987-03-18
US4700020A (en) 1987-10-13
ATE64803T1 (en) 1991-07-15
CA1267232A (en) 1990-03-27
AU590794B2 (en) 1989-11-16
DE3679948D1 (en) 1991-08-01
PT83340A (en) 1986-10-01
BR8604335A (en) 1987-05-12
PT83340B (en) 1992-10-30
ZA866883B (en) 1987-04-29
GR862299B (en) 1987-01-31
JPS6261497A (en) 1987-03-18

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