IN157319B - - Google Patents
Info
- Publication number
- IN157319B IN157319B IN591/CAL/82A IN591CA1982A IN157319B IN 157319 B IN157319 B IN 157319B IN 591CA1982 A IN591CA1982 A IN 591CA1982A IN 157319 B IN157319 B IN 157319B
- Authority
- IN
- India
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0286—Programmable, customizable or modifiable circuits
- H05K1/0287—Programmable, customizable or modifiable circuits having an universal lay-out, e.g. pad or land grid patterns or mesh patterns
- H05K1/0289—Programmable, customizable or modifiable circuits having an universal lay-out, e.g. pad or land grid patterns or mesh patterns having a matrix lay-out, i.e. having selectively interconnectable sets of X-conductors and Y-conductors in different planes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US22558181A | 1981-01-16 | 1981-01-16 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| IN157319B true IN157319B (zh) | 1986-03-01 |
Family
ID=22845439
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| IN591/CAL/82A IN157319B (zh) | 1981-01-16 | 1982-05-22 |
Country Status (5)
| Country | Link |
|---|---|
| EP (1) | EP0069762B1 (zh) |
| JP (1) | JPS58500096A (zh) |
| DE (1) | DE3176991D1 (zh) |
| IN (1) | IN157319B (zh) |
| WO (1) | WO1982002640A1 (zh) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6050940A (ja) * | 1983-08-31 | 1985-03-22 | Toshiba Corp | 半導体集積回路 |
| US4920454A (en) * | 1983-09-15 | 1990-04-24 | Mosaic Systems, Inc. | Wafer scale package system and header and method of manufacture thereof |
| JPS60502234A (ja) * | 1983-09-15 | 1985-12-19 | モザイク・システムズ・インコ−ポレ−テッド | ウエハ |
| WO1985003804A1 (en) * | 1984-02-21 | 1985-08-29 | Mosaic Systems, Inc. | Wafer scale package system and header and method of manufacture thereof |
| US4571451A (en) * | 1984-06-04 | 1986-02-18 | International Business Machines Corporation | Method for routing electrical connections and resulting product |
| US5055973A (en) * | 1990-01-17 | 1991-10-08 | Aptix Corporation | Custom tooled printed circuit board |
| EP0518701A3 (en) * | 1991-06-14 | 1993-04-21 | Aptix Corporation | Field programmable circuit module |
| US5959466A (en) | 1997-01-31 | 1999-09-28 | Actel Corporation | Field programmable gate array with mask programmed input and output buffers |
| US6150837A (en) | 1997-02-28 | 2000-11-21 | Actel Corporation | Enhanced field programmable gate array |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3312871A (en) * | 1964-12-23 | 1967-04-04 | Ibm | Interconnection arrangement for integrated circuits |
| US3377513A (en) * | 1966-05-02 | 1968-04-09 | North American Rockwell | Integrated circuit diode matrix |
| US3500148A (en) * | 1968-08-28 | 1970-03-10 | Bell Telephone Labor Inc | Multipurpose integrated circuit arrangement |
| US3679941A (en) * | 1969-09-22 | 1972-07-25 | Gen Electric | Composite integrated circuits including semiconductor chips mounted on a common substrate with connections made through a dielectric encapsulator |
| GB1412107A (en) * | 1971-12-18 | 1975-10-29 | Marconi Co Ltd | Semi-conductor memory device arrangements |
| US4234888A (en) * | 1973-07-26 | 1980-11-18 | Hughes Aircraft Company | Multi-level large scale complex integrated circuit having functional interconnected circuit routed to master patterns |
| US4203123A (en) * | 1977-12-12 | 1980-05-13 | Burroughs Corporation | Thin film memory device employing amorphous semiconductor materials |
| US4240094A (en) * | 1978-03-20 | 1980-12-16 | Harris Corporation | Laser-configured logic array |
| US4295149A (en) * | 1978-12-29 | 1981-10-13 | International Business Machines Corporation | Master image chip organization technique or method |
-
1981
- 1981-12-22 WO PCT/US1981/001725 patent/WO1982002640A1/en active IP Right Grant
- 1981-12-22 JP JP50051882A patent/JPS58500096A/ja active Pending
- 1981-12-22 EP EP19820900481 patent/EP0069762B1/en not_active Expired
- 1981-12-22 DE DE8282900481T patent/DE3176991D1/de not_active Expired
-
1982
- 1982-05-22 IN IN591/CAL/82A patent/IN157319B/en unknown
Also Published As
| Publication number | Publication date |
|---|---|
| EP0069762A4 (en) | 1985-07-01 |
| EP0069762B1 (en) | 1989-02-08 |
| JPS58500096A (ja) | 1983-01-13 |
| DE3176991D1 (en) | 1989-03-16 |
| WO1982002640A1 (en) | 1982-08-05 |
| EP0069762A1 (en) | 1983-01-19 |