ID20659A - Arsitektur kemampuan cache - Google Patents
Arsitektur kemampuan cacheInfo
- Publication number
- ID20659A ID20659A IDP981206A ID981206A ID20659A ID 20659 A ID20659 A ID 20659A ID P981206 A IDP981206 A ID P981206A ID 981206 A ID981206 A ID 981206A ID 20659 A ID20659 A ID 20659A
- Authority
- ID
- Indonesia
- Prior art keywords
- cache
- architecture
- ability
- architecture ability
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4286—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a handshaking protocol, e.g. RS232C link
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
- G06F12/0873—Mapping of cache memory to specific storage devices or parts thereof
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0674—Disk device
- G06F3/0676—Magnetic disk device
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0012—High speed serial bus, e.g. IEEE P1394
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Human Computer Interaction (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US5845297P | 1997-09-08 | 1997-09-08 | |
EP97115527A EP0901077A1 (en) | 1997-09-08 | 1997-09-08 | Cache enabling architecture |
Publications (1)
Publication Number | Publication Date |
---|---|
ID20659A true ID20659A (id) | 1999-02-11 |
Family
ID=26145768
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
IDP981206A ID20659A (id) | 1997-09-08 | 1998-09-08 | Arsitektur kemampuan cache |
Country Status (7)
Country | Link |
---|---|
JP (1) | JPH11167469A (id) |
KR (1) | KR100580933B1 (id) |
CN (1) | CN1119749C (id) |
HK (1) | HK1017115A1 (id) |
ID (1) | ID20659A (id) |
MY (1) | MY118599A (id) |
SG (1) | SG70114A1 (id) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101403982B (zh) | 2008-11-03 | 2011-07-20 | 华为技术有限公司 | 一种多核处理器的任务分配方法和*** |
-
1998
- 1998-08-19 JP JP10247716A patent/JPH11167469A/ja active Pending
- 1998-08-20 SG SG1998003160A patent/SG70114A1/en unknown
- 1998-09-02 KR KR1019980036131A patent/KR100580933B1/ko not_active IP Right Cessation
- 1998-09-04 CN CN98118871A patent/CN1119749C/zh not_active Expired - Fee Related
- 1998-09-07 MY MYPI98004072A patent/MY118599A/en unknown
- 1998-09-08 ID IDP981206A patent/ID20659A/id unknown
-
1999
- 1999-05-17 HK HK99102170A patent/HK1017115A1/xx not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR19990029463A (ko) | 1999-04-26 |
JPH11167469A (ja) | 1999-06-22 |
CN1119749C (zh) | 2003-08-27 |
CN1211008A (zh) | 1999-03-17 |
MY118599A (en) | 2004-12-31 |
KR100580933B1 (ko) | 2006-10-24 |
HK1017115A1 (en) | 1999-11-12 |
SG70114A1 (en) | 2000-01-25 |
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