ID20659A - Arsitektur kemampuan cache - Google Patents

Arsitektur kemampuan cache

Info

Publication number
ID20659A
ID20659A IDP981206A ID981206A ID20659A ID 20659 A ID20659 A ID 20659A ID P981206 A IDP981206 A ID P981206A ID 981206 A ID981206 A ID 981206A ID 20659 A ID20659 A ID 20659A
Authority
ID
Indonesia
Prior art keywords
cache
architecture
ability
architecture ability
Prior art date
Application number
IDP981206A
Other languages
English (en)
Inventor
Xavier Lebegue
Rainer Schweer
Original Assignee
Thomson Brandt Gmbh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from EP97115527A external-priority patent/EP0901077A1/en
Application filed by Thomson Brandt Gmbh filed Critical Thomson Brandt Gmbh
Publication of ID20659A publication Critical patent/ID20659A/id

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/42Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4286Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a handshaking protocol, e.g. RS232C link
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0866Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
    • G06F12/0873Mapping of cache memory to specific storage devices or parts thereof
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0668Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671In-line storage system
    • G06F3/0673Single storage device
    • G06F3/0674Disk device
    • G06F3/0676Magnetic disk device
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0012High speed serial bus, e.g. IEEE P1394

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
IDP981206A 1997-09-08 1998-09-08 Arsitektur kemampuan cache ID20659A (id)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US5845297P 1997-09-08 1997-09-08
EP97115527A EP0901077A1 (en) 1997-09-08 1997-09-08 Cache enabling architecture

Publications (1)

Publication Number Publication Date
ID20659A true ID20659A (id) 1999-02-11

Family

ID=26145768

Family Applications (1)

Application Number Title Priority Date Filing Date
IDP981206A ID20659A (id) 1997-09-08 1998-09-08 Arsitektur kemampuan cache

Country Status (7)

Country Link
JP (1) JPH11167469A (id)
KR (1) KR100580933B1 (id)
CN (1) CN1119749C (id)
HK (1) HK1017115A1 (id)
ID (1) ID20659A (id)
MY (1) MY118599A (id)
SG (1) SG70114A1 (id)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101403982B (zh) 2008-11-03 2011-07-20 华为技术有限公司 一种多核处理器的任务分配方法和***

Also Published As

Publication number Publication date
KR19990029463A (ko) 1999-04-26
JPH11167469A (ja) 1999-06-22
CN1119749C (zh) 2003-08-27
CN1211008A (zh) 1999-03-17
MY118599A (en) 2004-12-31
KR100580933B1 (ko) 2006-10-24
HK1017115A1 (en) 1999-11-12
SG70114A1 (en) 2000-01-25

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