HK1115937A1 - High current semiconductor power device soic package - Google Patents
High current semiconductor power device soic packageInfo
- Publication number
- HK1115937A1 HK1115937A1 HK08111809A HK08111809A HK1115937A1 HK 1115937 A1 HK1115937 A1 HK 1115937A1 HK 08111809 A HK08111809 A HK 08111809A HK 08111809 A HK08111809 A HK 08111809A HK 1115937 A1 HK1115937 A1 HK 1115937A1
- Authority
- HK
- Hong Kong
- Prior art keywords
- lead frame
- power device
- high current
- semiconductor power
- current semiconductor
- Prior art date
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
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- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
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- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
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- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Abstract
The invention discloses a small form factor integrated circuit package for a high current semiconductor power device. The package includes a lead frame which is relatively thick and made of a single specification material with a thickness greater than 8mil. The lead frame has a plurality of lead frame and a first lead frame area, wherein, the first lead frame area includes a chip soldering thereon, a lead linking area arranged on the same surface with the top surface of the chip, a aluminum-made large-diameter linking conducting wire connected to the leads, and a resin body which comes from at least one part of a sealing chip, a linking conducting wire and the lead frame.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/544,453 US7759775B2 (en) | 2004-07-20 | 2006-10-06 | High current semiconductor power device SOIC package |
Publications (1)
Publication Number | Publication Date |
---|---|
HK1115937A1 true HK1115937A1 (en) | 2008-12-12 |
Family
ID=39422986
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
HK08111809A HK1115937A1 (en) | 2006-10-06 | 2008-10-27 | High current semiconductor power device soic package |
Country Status (3)
Country | Link |
---|---|
CN (2) | CN101794760B (en) |
HK (1) | HK1115937A1 (en) |
TW (1) | TWI350582B (en) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9041170B2 (en) * | 2013-04-02 | 2015-05-26 | Infineon Technologies Austria Ag | Multi-level semiconductor package |
JP6325975B2 (en) * | 2014-12-19 | 2018-05-16 | 新光電気工業株式会社 | Lead frame, semiconductor device |
DE102015101674B4 (en) | 2015-02-05 | 2021-04-29 | Infineon Technologies Austria Ag | Semiconductor chip housing with contact pins on short side edges |
US10325878B2 (en) * | 2016-06-30 | 2019-06-18 | Kulicke And Soffa Industries, Inc. | Methods for generating wire loop profiles for wire loops, and methods for checking for adequate clearance between adjacent wire loops |
CN109727943A (en) * | 2019-02-27 | 2019-05-07 | 无锡新洁能股份有限公司 | A kind of package structure of semiconductor device and its manufacturing method with low thermal resistance |
CN110164832A (en) * | 2019-05-31 | 2019-08-23 | 无锡电基集成科技有限公司 | High-current semiconductor power device |
CN110164831A (en) * | 2019-05-31 | 2019-08-23 | 无锡电基集成科技有限公司 | Conducive to the high-current semiconductor power device and its manufacturing method of welding |
CN215266282U (en) * | 2021-04-14 | 2021-12-21 | 苏州汇川技术有限公司 | Packaging structure of power semiconductor device |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6114750A (en) * | 1996-10-01 | 2000-09-05 | International Rectifier Corp. | Surface mount TO-220 package and process for the manufacture thereof |
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2007
- 2007-09-12 CN CN2010101165164A patent/CN101794760B/en active Active
- 2007-09-12 CN CN2007101474382A patent/CN101174602B/en active Active
- 2007-09-19 TW TW096135002A patent/TWI350582B/en active
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2008
- 2008-10-27 HK HK08111809A patent/HK1115937A1/en unknown
Also Published As
Publication number | Publication date |
---|---|
TWI350582B (en) | 2011-10-11 |
CN101174602B (en) | 2011-10-05 |
CN101174602A (en) | 2008-05-07 |
CN101794760B (en) | 2012-05-23 |
CN101794760A (en) | 2010-08-04 |
TW200818438A (en) | 2008-04-16 |
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