CN109727943A - A kind of package structure of semiconductor device and its manufacturing method with low thermal resistance - Google Patents
A kind of package structure of semiconductor device and its manufacturing method with low thermal resistance Download PDFInfo
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- CN109727943A CN109727943A CN201910146013.2A CN201910146013A CN109727943A CN 109727943 A CN109727943 A CN 109727943A CN 201910146013 A CN201910146013 A CN 201910146013A CN 109727943 A CN109727943 A CN 109727943A
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- potting resin
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- bonding region
- thermal resistance
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 101
- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 239000011347 resin Substances 0.000 claims abstract description 65
- 229920005989 resin Polymers 0.000 claims abstract description 65
- 238000004382 potting Methods 0.000 claims abstract description 61
- 239000002184 metal Substances 0.000 claims abstract description 21
- 229910052751 metal Inorganic materials 0.000 claims abstract description 21
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 claims abstract description 8
- 150000002739 metals Chemical class 0.000 claims abstract description 3
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 claims description 41
- 239000011521 glass Substances 0.000 claims description 28
- 230000005611 electricity Effects 0.000 claims description 18
- 238000001816 cooling Methods 0.000 claims description 13
- 238000005520 cutting process Methods 0.000 claims description 6
- 238000012360 testing method Methods 0.000 claims description 6
- 238000012545 processing Methods 0.000 claims description 5
- 238000004806 packaging method and process Methods 0.000 claims description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 3
- 238000007747 plating Methods 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims 2
- 239000010931 gold Substances 0.000 claims 2
- 229910052737 gold Inorganic materials 0.000 claims 2
- 239000004020 conductor Substances 0.000 claims 1
- 239000004744 fabric Substances 0.000 claims 1
- 238000005538 encapsulation Methods 0.000 abstract description 26
- 230000017525 heat dissipation Effects 0.000 abstract description 8
- 238000010586 diagram Methods 0.000 description 13
- 238000000034 method Methods 0.000 description 5
- 238000012856 packing Methods 0.000 description 4
- 230000001052 transient effect Effects 0.000 description 3
- 238000003466 welding Methods 0.000 description 3
- 238000005452 bending Methods 0.000 description 2
- 238000013461 design Methods 0.000 description 1
- JEIPFZHSYJVQDO-UHFFFAOYSA-N iron(III) oxide Inorganic materials O=[Fe]O[Fe]=O JEIPFZHSYJVQDO-UHFFFAOYSA-N 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/4901—Structure
- H01L2224/4903—Connectors having different sizes, e.g. different diameters
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The invention belongs to technical field of semiconductor encapsulation, a kind of package structure of semiconductor device with low thermal resistance, including semiconductor chip, lead frame and potting resin, lead frame includes metab and pin, the semiconductor chip back side is welded on metab, potting resin lid seals on a semiconductor die, exposed portion pin and part metals pedestal, the pin of exposing is folded upward at extension, and pin end is plane, plane and potting resin surface are in same plane or angle o, and pin end is welded in PCB circuit board；Surface curvature of the pin of encapsulating structure of the present invention to potting resin, pin is directly welded in PCB circuit board, and potting resin is contacted with PCB circuit board, and metab heat dissipation is connect with radiator upwardly, it can effectively be radiated by metab and radiator, the thermal resistance of semiconductor devices in the electronic device is significantly reduced, the temperature rise of device, the device reliability and electronic apparatus system reliability of raising are reduced.
Description
Technical field
The present invention relates to package structure of semiconductor device and preparation method thereof, especially a kind of semiconductor with low thermal resistance
Device encapsulation structure and its manufacturing method belong to semiconductor device packaging technique field.
Background technique
Semiconductor devices is finally used in PCB circuit board, passes through the route design and semiconductor devices on circuit board
The configuration connection of equal electronic components, can form complete circuit framework, to provide function required for electronic equipment.Semiconductor device
Whether reliably whether connection determines the function of electronic equipment normally between part and circuit board.
Currently, usually having through-hole type and two kinds of patch type between conventional semiconductors power device and circuit board.Through-hole type connects
It connects as shown in Figure 1, in process of production, through-hole type connection needs human weld, and welding efficiency is low, at high cost, and welding process
In often semiconductor devices is caused to damage since manual operation is improper, cause production yield low.And paster type encapsulation
Semiconductor devices be easier to realize electronic equipment mass automatic production, therefore, more and more semiconductor devices use
Patch type is attached with circuit board.For semiconductor power device, using typical paster type encapsulation (such as TO-252,
TO-263 encapsulation) semiconductor power device when directly carrying out electrology characteristic connection with circuit board, the metab of chip (company
Connect MOSFET drain electrode) it needs to weld on circuit boards, the metab for needing high current to flow through chip gets to entire electronics
In route, packaged resistance is increased, as shown in Figure 2.But since semiconductor power device is own power in system work
Very big, other than connecting with the necessary electrology characteristic of circuit board, the heat dissipation characteristics and heat sink conception of semiconductor devices are also very big
The normal use of device is affected in degree.Using the semiconductor power device of the packing forms such as traditional TO-252, TO-263,
Heat dissipation path on circuit board includes two: 1, heat is ultimately conducted in environment by chip by potting resin, radiator；2,
Heat is ultimately conducted in environment by chip by metab, PCB circuit board, radiator.Then, potting resin and PCB electricity
The thermal resistance of road plate is all very big, causes semiconductor power device heat that cannot effectively radiate, and device temperature increases, vulnerable.
In addition to this, the metab area of traditional TO-252, TO-263 encapsulation is smaller, and thermal capacitance is smaller, and chip is caused to exist
Higher temperature overshot is had under transient high power state, causes device vulnerable.
Therefore the packing forms of a kind of low thermal resistance, high heat capacity are needed, to meet system requirements.
Summary of the invention
The present invention, which is directed to after conventional package between semiconductor power device and circuit board, connects existing problems, provides one
Kind there is the package structure of semiconductor device and its manufacturing method of low thermal resistance, the pin of the encapsulating structure is to the surface of potting resin
Bending, enables pin to be directly welded in PCB circuit board, and potting resin is contacted with PCB circuit board, and metab radiates
It is connect with radiator upwardly, can effectively be radiated by metab with radiator in this way, significantly reduce semiconductor devices and exist
Thermal resistance in electronic equipment reduces the temperature rise of device, the device reliability and electronic apparatus system reliability of raising.
To realize the above technical purpose, the technical scheme is that a kind of semiconductor packages with low thermal resistance
Structure, including semiconductor chip, lead frame and potting resin, which is characterized in that the lead frame include metab and
The back side of the pin connecting with the metab, the semiconductor chip is welded on metab, the potting resin lid
It is enclosed in the semiconductor core on piece, exposed portion pin and part metals pedestal, the pin of exposing is folded upward at extension, and pin
End is plane, and the plane and potting resin surface are in same plane, and the pin end is welded in PCB circuit board.
Further, the metab includes the area slide glass Ji Dao and frame body area, the semiconductor chip back side weldering
It connects in the area slide glass Ji Dao, the semiconductor chip front is connect by metal lead wire with bonding region, the bonding region and pin
Connection.
Further, the potting resin lid is enclosed on the area slide glass Ji Dao, bonding region and metal lead wire, exposes frame body
Area and part pin.
Further, the back side of the metab is radiating surface, and the radiating surface is connect by felt pad with cooling fin；
The lower section of the PCB circuit board is equipped with cooling fin.
Further, the semiconductor chip includes MOSFET chip, igbt chip or diode.
Further, for MOSFET chip, the back side of the MOSFET chip is drain electrode, and front is equipped with grid and source
Pole, electricity is connected between grid and the first bonding region, and electricity is connected between source electrode and the second bonding region, and drain electrode passes through slide glass Ji Dao
Area is connected with second pin electricity；For igbt chip, the back side of the igbt chip is collector, and front is equipped with grid and hair
Emitter-base bandgap grading, electricity is connected between grid and the first bonding region, and electricity is connected between emitter and the second bonding region, and collector passes through load
Chip base island area is connected with second pin electricity；For diode, the front of the diode is anode, and the back side is cathode, anode
Electricity is connected between the second bonding region, and cathode is connected by the area slide glass Ji Dao with second pin electricity.
Further, first bonding region is connect with the first pin, and the second bonding region is connect with third pin, and second draws
Foot is arranged between the first pin and third pin.
Further, the angle θ is 0 ~ 8 degree.
Further, the lead frame include TO-220 lead frame, TO-247 lead frame, TO-3P lead frame,
TO-251 lead frame, TO-262 lead frame.
In order to further realize the above technical purpose, the present invention also proposes a kind of semiconductor packages with low thermal resistance
The production method of structure, which comprises the steps of:
A. multiple semiconductor chips and row lead wire frame are chosen, the row lead wire frame includes multiple connection arrangements arranged side by side
Lead frame；
B., the back side of the semiconductor chip is successively mounted on to the slide glass base of each lead frame in the row lead wire frame
Island area；
C. the semiconductor chip front electrode is bonded by metal lead wire with corresponding bonding region；
D. the row lead wire frame for being welded with semiconductor chip is subjected to plastic packaging and encapsulating with potting resin, exposes lead frame
Frame body area and part pin；
E. the row lead wire frame after encapsulating is subjected to hot setting；
F. the redundancy potting resin that do not encapsulated in region on the row lead wire frame is removed；
G. the lead frame for not encapsulating region on the row lead wire frame is carried out tin plating；
H. the row lead wire frame is subjected to rib cutting processing, the frame connection part between cutting removal lead frame is formed more
Device cell after a independent encapsulating；
I. pin is extended to potting resin surface curvature, so that pin end and potting resin surface are in same plane；
J. the test of specified parameter is carried out to above-mentioned every independent device cell, and to the device for meeting test specification requirement
Laser typewriting is carried out on its potting resin surface；
K. the pin of the device cell after encapsulating is welded in PCB circuit board.
Further, which is characterized in that in the step d, the pin includes first be electrically connected with the first bonding region
Pin, the third pin being electrically connected with the second bonding region and the second pin between the first pin, third pin, the encapsulation
The top of semiconductor chip, metal lead wire, bonding region and second pin above the resin package area slide glass Ji Dao.
Compared with conventional semiconductor devices encapsulating structure, the invention has the following advantages that
1) compared with traditional through-hole type packaged type, when the present invention is connect with PCB circuit board, through-hole welding is not needed, is only needed
Pin end plane is welded on pcb board, production yield high-efficient, at low cost is high；
2) it compared with conventional patch formula packaged type, when the present invention is connect with PCB circuit board, does not need the metab of chip
It is welded on pcb board, on the one hand upward by metab, while passing through felt pad and cooling fin in the radiating surface in the area slide glass Ji Dao
The pin end plane of bending, is on the other hand welded on pcb board by connection, while connecing cooling fin below pcb board；Therefore, originally
Heat dissipation path of the invention semiconductor devices in PCB circuit board includes: 1, heat by semiconductor chip by potting resin, PCB
Circuit board, cooling fin are ultimately conducted in environment；2, heat passes through metab, felt pad, radiator most by semiconductor chip
Conduction is into environment eventually；Since metab and felt pad thermal resistance are very low, the 2nd article of heat dissipation path becomes the main heat sink of device
Path, and there is extremely low thermal resistance, the thermal resistance of semiconductor devices in the electronic device is significantly reduced, the temperature of device is reduced
It rises, the device reliability and electronic apparatus system reliability of raising；
3) metab of the present invention has biggish area and volume, has bigger thermal capacitance, makes device in transient high power state
Under do not have apparent temperature overshot, improve the reliability of device；
4) lead frame of the invention is applicable to the conventional packages lead such as TO-220, TO-247, TO-3P, TO-262, TO-251
Frame without being opened again to lead frame, and may be implemented conllinear with the producing line of above-mentioned packing forms, increase work without additional
Skill complexity and processing cost have many advantages, such as that production cost is low, easy to use, have high cost performance.
Detailed description of the invention
Fig. 1 is that tradition TO-220 encapsulates the structural relation schematic diagram connecting with PCB circuit board.
Fig. 2 is that tradition TO-263 encapsulates the structural relation schematic diagram connecting with PCB circuit board.
Fig. 3 is the semiconductor device structure schematic diagram of 1 TO-220 of embodiment encapsulation.
Fig. 4 is the semiconductor devices three-dimensional perspective that embodiment 1 is packaged with MOSFET chip.
Fig. 5 a is the overlooking structure diagram that embodiment 1 is packaged with MOSFET chip.
Fig. 5 b is the overlooking structure diagram that embodiment 1 is packaged with IGBT and diode chip for backlight unit.
Fig. 6 is the side structure schematic view after the encapsulation of embodiment 1.
Fig. 7 is the structural relation schematic diagram that the semiconductor chip after the encapsulation of embodiment 1 is connect with PCB circuit board.
Fig. 8 is the semiconductor device structure schematic diagram of 2 TO-227 of embodiment encapsulation.
Fig. 9 is the semiconductor device structure schematic diagram of 3 TO-3P of embodiment encapsulation.
Figure 10 is the semiconductor device structure schematic diagram of 4 TO-251 of embodiment encapsulation.
Figure 11 is the semiconductor device structure schematic diagram of 5 TO-262 of embodiment encapsulation.
Figure 12 is the semiconductor device structure schematic diagram of 6 TO-220 of embodiment encapsulation.
Figure 13 is the semiconductor device structure schematic diagram of 7 TO-247 of embodiment encapsulation.
Figure 14 is the semiconductor device structure schematic diagram of 8 TO-3P of embodiment encapsulation.
Detailed description of the invention: 1- semiconductor chip, 2- metab, the area 21- slide glass Ji Dao, 22- frame body area, 3- encapsulation tree
Rouge, 4- pin, 5-PCB circuit board, 6- bonding region, 7- felt pad, 8- cooling fin.
Specific embodiment
Below with reference to specific drawings and examples, the invention will be further described.
The present invention is not limited to the following embodiments and the accompanying drawings, and each figure of institute's reference is to be able to this hair in the following description
Bright content is understood and is synoptically indicated to shape, size and positional relationship.That is, the present invention is not limited to each figures
Shape, size shown in illustrating and positional relationship.
Embodiment 1: it uses and encapsulates identical lead frame with traditional TO-220；
As shown in Fig. 3, Fig. 4 and Fig. 6, a kind of package structure of semiconductor device with low thermal resistance, including semiconductor chip 1, draw
Wire frame and potting resin 3, the lead frame includes metab 2 and the pin 4 that connect with the metab 2, described
Metab 2 includes the area slide glass Ji Dao 21 and frame body area 22, and 1 back side of semiconductor chip is welded on the area slide glass Ji Dao 21
On, 1 front of semiconductor chip is connect by metal lead wire with bonding region 6, and the bonding region 6 is connect with pin 4, the envelope
The dress lid of resin 3 is enclosed in the area slide glass Ji Dao 21, and package semiconductor chip 1, bonding region 6 and metal lead wire expose frame body area
22 and part pin 4, the pin 4 of exposing is bent to 3 surface direction of potting resin to be extended, and 4 end of pin is plane, described flat
Face and 3 surface of potting resin are in same plane or angle o with 3 surface of potting resin, and the angle θ is 0 ~ 8 degree, convenient and PCB circuit
Plate 5 is welded；
As shown in fig. 7,4 end of pin is welded in PCB circuit board 5,21 back side of the area slide glass Ji Dao of the metab 2
For radiating surface, the radiating surface is connect by felt pad 7 with cooling fin 8；The lower section of the PCB circuit board 5 is equipped with cooling fin 8；
In the present embodiment 1, as shown in Figure 5 a, the semiconductor chip 1 is MOSFET chip, and the grid of MOSFET chip front side is logical
It crosses metal lead wire to be electrically connected with the first bonding region, source electrode is electrically connected by metal lead wire with the second bonding region, the first bonding region, the
Two bonding regions are connect with the first pin, third pin respectively, and the drain electrode at the back side is connect by the area slide glass Ji Dao with second pin；Such as
Shown in Fig. 5 b, the semiconductor chip 1 includes two on the right side of being welded on the igbt chip in 21 left side of the area slide glass Ji Dao and being welded on
Pole pipe, the positive grid of igbt chip are electrically connected by metal lead wire with the first bonding region, and emitter passes through metal lead wire and the
The electrical connection of two bonding regions, the first bonding region, the second bonding region are connect with the first pin, third pin respectively, the collector at the back side
It is connect by the area slide glass Ji Dao with second pin；The positive anode of diode is electrically connected by metal lead wire with the second bonding region,
Second bonding region is connect with third pin, and the cathode at the back side is connect by the area slide glass Ji Dao with second pin；
Embodiment 2: it uses and encapsulates identical lead frame with traditional TO-247；
As shown in figure 8, same as Example 1, on the semiconductor devices after the encapsulation, three pins are to potting resin 3
Surface curvature, and pin end and 3 surface of potting resin are in same plane or angle o with 3 surface of potting resin, it is convenient with
PCB circuit board 5 is welded；
Embodiment 3: it uses and encapsulates identical lead frame with traditional TO-3P；
As shown in figure 9, same as Example 1, on the semiconductor devices after the encapsulation, three pins are to potting resin 3
Surface curvature, and pin end and 3 surface of potting resin are in same plane or angle o with 3 surface of potting resin, it is convenient with
PCB circuit board 5 is welded；
Embodiment 4: it uses and encapsulates identical lead frame with traditional TO-251；
As shown in Figure 10, same as Example 1, on the semiconductor devices after the encapsulation, three pins are to potting resin 3
Surface curvature, and pin end and 3 surface of potting resin are in same plane or angle o with 3 surface of potting resin, it is convenient with
PCB circuit board 5 is welded；
Embodiment 5: it uses and encapsulates identical lead frame with traditional TO-262；
As shown in figure 11, same as Example 1, on the semiconductor devices after the encapsulation, three pins are to potting resin 3
Surface curvature, and pin end and 3 surface of potting resin are in same plane or angle o with 3 surface of potting resin, it is convenient with
PCB circuit board 5 is welded；
Embodiment 6: it uses and encapsulates identical lead frame with traditional TO-220；
As shown in figure 12, same as Example 1, on the semiconductor devices after the encapsulation, three pins are to potting resin 3
Surface curvature, and pin end and 3 surface of potting resin are in same plane or angle o with 3 surface of potting resin, it is convenient with
PCB circuit board 5 is welded；
Embodiment 7: it uses and encapsulates identical lead frame with traditional TO-247；
As shown in figure 13, same as Example 1, on the semiconductor devices after the encapsulation, three pins are to potting resin 3
Surface curvature, and pin end and 3 surface of potting resin are in same plane or angle o with 3 surface of potting resin, it is convenient with
PCB circuit board 5 is welded；
Embodiment 8: it uses and encapsulates identical lead frame with traditional TO-3P；The frame body area of the lead frame is non-porous
Hole.
As shown in figure 14, same as Example 1, on the semiconductor devices after the encapsulation, three pins are to encapsulation
The surface curvature of resin 3, and pin end and 3 surface of potting resin are in same plane or angle o with 3 surface of potting resin,
It is convenient to be welded with PCB circuit board 5；
2 ~ embodiment of embodiment 13 is same as Example 1, and 4 end of pin is welded in PCB circuit board 5, the metab 2
21 back side of the area slide glass Ji Dao be radiating surface, the metab 2 is connect by felt pad 7 with cooling fin 8；The PCB circuit
The lower section of plate 5 is equipped with cooling fin 8；
The production method of package structure of semiconductor device of one of the embodiment as above with low thermal resistance, includes the following steps:
A. multiple semiconductor chips 1 and row lead wire frame are chosen, the row lead wire frame includes multiple connection arrangements arranged side by side
Lead frame；
B., the back side of the semiconductor chip 1 is successively mounted on to the slide glass of each lead frame in the row lead wire frame
The area Ji Dao 21；
C. 1 front electrode of semiconductor chip is bonded by metal lead wire with corresponding bonding region 6；
D. the row lead wire frame for being welded with semiconductor chip 1 is subjected to plastic packaging and encapsulating with potting resin, exposes lead frame
Frame body area 22 and part pin 4；
The pin 4 include the first pin being electrically connected with the first bonding region, the third pin being electrically connected with the second bonding region and
Second pin between the first pin, third pin, the potting resin 3 wrap up the semiconductor core above the area slide glass Ji Dao 21
The top of piece 1, metal lead wire, bonding region 6 and second pin;
E. the row lead wire frame after encapsulating is subjected to hot setting；
F. the redundancy potting resin that do not encapsulated in region on the row lead wire frame is removed, i.e., flash is removed；
G. the lead frame for not encapsulating region on the row lead wire frame is carried out tin plating；
H. the row lead wire frame is subjected to rib cutting processing, the frame connection part between cutting removal lead frame is formed more
Device cell after a independent encapsulating；
I. pin 4 is extended to 3 surface curvature of potting resin, so that 4 end of pin and 3 surface of potting resin are in same flat
Face；
J. the test of specified parameter is carried out to above-mentioned every independent device cell, and to the device for meeting test specification requirement
Laser typewriting is carried out on its potting resin surface；
K. the pin 4 of the device cell after encapsulating is welded in PCB circuit board 5.
When the present invention is connect with PCB circuit board 5, the end of pin 4 and PCB circuit board 5 are welded, 3 surface of potting resin with
PCB circuit board 5 directly contacts, and the heat dissipation of the area slide glass Ji Dao 21 of metab 2 is connect with radiator 8 upwardly；At this point, semiconductor
The heat dissipation path of device includes: that 1, heat is ultimately conducted to by semiconductor chip by potting resin, PCB circuit board, cooling fin
In environment；2, heat is ultimately conducted in environment by semiconductor chip by metab, felt pad, radiator；Due to metal
Pedestal and felt pad thermal resistance are very low, and the 2nd article of heat dissipation path becomes the main heat sink path of device, and has extremely low thermal resistance,
The thermal resistance of semiconductor devices in the electronic device is significantly reduced, the temperature rise of device, the device reliability and electricity of raising are reduced
Sub- device systems reliability；Electronics is more easily satisfied in connection between semiconductor power device of the invention, with PCB circuit board 5
The demand of equipment mass automatic production.
Metab 2 of the present invention has biggish area and volume, has bigger thermal capacitance, makes device in transient high power shape
Apparent temperature overshot is not had under state, improves the reliability of device.
The conventional packages lead frames such as the present invention compatible TO-220, TO-247, TO-3P, TO-262, TO-251, without weight
Newly lead frame is opened, and may be implemented it is conllinear with the producing line of above-mentioned packing forms, without additional process complexity and
Processing cost has many advantages, such as that production cost is low, easy to use, has high cost performance.
The present invention and its embodiments have been described above, description is not limiting, it is shown in the drawings also only
It is one of embodiments of the present invention, actual structure is not limited to this.All in all if the ordinary skill people of this field
Member is enlightened by it, without departing from the spirit of the invention, is not inventively designed similar to the technical solution
Frame mode and embodiment, be within the scope of protection of the invention.
Claims (10)
1. a kind of package structure of semiconductor device with low thermal resistance, including semiconductor chip (1), lead frame and potting resin
(3), which is characterized in that the lead frame includes metab (2) and the pin (4) connecting with the metab (2), institute
The back side for stating semiconductor chip (1) is welded on metab (2), and potting resin (3) lid is enclosed in the semiconductor chip
(1) on, exposed portion pin (4) and part metals pedestal (2), the pin (4) of exposing are folded upward at extension, and pin (4) end
End is plane, and the plane and potting resin (3) surface are in same plane or angle o with potting resin (3) surface, described to draw
Foot (4) end is welded on PCB circuit board (5).
2. a kind of package structure of semiconductor device with low thermal resistance according to claim 1, which is characterized in that the gold
Belonging to pedestal (2) includes the area slide glass Ji Dao (21) and frame body area (22), and semiconductor chip (1) back side is welded on slide glass base
In island area (21), the semiconductor chip (1) front is connect by metal lead wire with bonding region (6), the bonding region (6) with draw
Foot (4) connection.
3. a kind of package structure of semiconductor device with low thermal resistance according to claim 2, which is characterized in that the envelope
Dress resin (3) lid is enclosed on the area slide glass Ji Dao (21), bonding region (6) and metal lead wire, exposes frame body area (22) and part
Pin (4).
4. a kind of package structure of semiconductor device with low thermal resistance according to claim 1, which is characterized in that the gold
The back side for belonging to pedestal (2) is radiating surface, and the radiating surface is connect by felt pad (7) with cooling fin (8)；The PCB circuit board
(5) lower section is equipped with cooling fin (8).
5. a kind of package structure of semiconductor device with low thermal resistance according to claim 1, which is characterized in that described half
Conductor chip includes MOSFET chip, igbt chip or diode.
6. a kind of package structure of semiconductor device with low thermal resistance according to claim 5, which is characterized in that for
MOSFET chip, the back side of the MOSFET chip are drain electrode, and front is equipped with grid and source electrode, between grid and the first bonding region
Electricity is connected, and electricity is connected between source electrode and the second bonding region, and drain electrode is connected by the area slide glass Ji Dao with second pin electricity；It is right
In igbt chip, the back side of the igbt chip is collector, and front is equipped with grid and emitter, grid and the first bonding region it
Between electricity be connected, electricity is connected between emitter and the second bonding region, and collector passes through the area slide glass Ji Dao and second pin electricity
It is connected；For diode, the front of the diode is anode, and the back side is cathode, electricity phase between anode and the second bonding region
Even, cathode is connected by the area slide glass Ji Dao with second pin electricity；First bonding region is connect with the first pin, the second bonding
Area is connect with third pin, and second pin is arranged between the first pin and third pin.
7. a kind of package structure of semiconductor device with low thermal resistance according to claim 1, which is characterized in that the θ
Angle is 0 ~ 8 degree.
8. a kind of package structure of semiconductor device with low thermal resistance according to claim 1, which is characterized in that described to draw
Wire frame includes that TO-220 lead frame, TO-247 lead frame, TO-3P lead frame, TO-251 lead frame, TO-262 draw
Wire frame.
9. a kind of production method of the package structure of semiconductor device with low thermal resistance, which comprises the steps of:
A. multiple semiconductor chips (1) and row lead wire frame are chosen, the row lead wire frame includes multiple connection rows arranged side by side
The lead frame of cloth；
B., the back side of the semiconductor chip (1) is successively mounted on to the load of each lead frame in the row lead wire frame
Chip base island area (21)；
C. the semiconductor chip (1) front electrode is bonded by metal lead wire with corresponding bonding region (6)；
D. the row lead wire frame that semiconductor chip (1) will be welded with carries out plastic packaging and encapsulating with potting resin, exposes lead frame
The frame body area (22) of frame and part pin (4)；
E. the row lead wire frame after encapsulating is subjected to hot setting；
F. the redundancy potting resin that do not encapsulated in region on the row lead wire frame is removed；
G. the lead frame for not encapsulating region on the row lead wire frame is carried out tin plating；
H. the row lead wire frame is subjected to rib cutting processing, the frame connection part between cutting removal lead frame is formed more
Device cell after a independent encapsulating；
I. pin (4) is extended to potting resin (3) surface curvature, so that at pin (4) end and potting resin (3) surface
In same plane；
J. the test of specified parameter is carried out to above-mentioned every independent device cell, and to the device for meeting test specification requirement
Laser typewriting is carried out on its potting resin surface；
K. the pin (4) of the device cell after encapsulating is welded on PCB circuit board (5).
10. a kind of production method of package structure of semiconductor device with low thermal resistance according to claim 9, feature
It is, in the step d, the pin (4) includes the first pin being electrically connected with the first bonding region, is electrically connected with the second bonding region
The third pin connect and the second pin between the first pin, third pin, the potting resin (3) wrap up the area slide glass Ji Dao
(21) above semiconductor chip (1), metal lead wire, bonding region (6) and second pin top.
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| CN116169113A (en) * | 2023-04-21 | 2023-05-26 | 江苏芯德半导体科技有限公司 | QFN packaging structure capable of reducing heat conduction to PCB and preparation method thereof |
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