GB896413A - Improvements relating to serial adding circuits - Google Patents

Abstract

896,413. Circuits employing bi-stable magnetic elements. ELECTRIC & MUSICAL INDUSTRIES Ltd. Aug. 21, 1958 [Aug. 21, 1957], No. 26338/57. Class 40 (9). [Also in Group XIX] A serial binary adder for inputs at A and B and providing a sum output at 31 (Fig. 1), comprises three magnetic cores 1, 2 and 3 acting as threshold 3, 1 and 2 gates respectively and each having three input windings energized by the A and B inputs and the carry signal on C, the output pulse from core 3 on resetting by a pulse at 20 being lengthened by the RC network 22b, 23b so that the " carry " collector current of transistor T3 will continue into the next denominational input at A and B. By arranging the effects of currents in windings 27 and 28 due to resetting of cores 2 and 3 to cancel out, so that core 25 is set after the end of the reset pulse through 29, 16, 17 and 18 if core 1, or core 2 only, was previously set, the correct sum output is read out of core 25 at the next re-set pulse. Fig. 3 shows a simplified arrangement in which the necessary cancellation of outputs from the gate cores 2 and 3 is effected by connection of the output windings 13, 14 and 15 in series with 14 and 15 in opposition, the sum output being obtained at 40 without the use of an intermediate core; the carry signal is derived from a second output winding 15a on core 3. The gating action of the cores is obtained by the use of appropriate windings, using the notation that a " 1 " winding provides a field just sufficient to set the core, a " ¢ " winding a field of half that strength, and a " - ¢ " winding a field of similar strength but in the reverse direction, then windings 4-9 are all " ¢ "; 19 is a "-¢" bias winding, and 10-12 are " 1 " windings (windings 16-18 and 29 are all capable of resetting their cores whatever the inputs). Specification 893,355 is referred to.