GB8806864D0 - Inter-processor interface - Google Patents
Inter-processor interfaceInfo
- Publication number
- GB8806864D0 GB8806864D0 GB888806864A GB8806864A GB8806864D0 GB 8806864 D0 GB8806864 D0 GB 8806864D0 GB 888806864 A GB888806864 A GB 888806864A GB 8806864 A GB8806864 A GB 8806864A GB 8806864 D0 GB8806864 D0 GB 8806864D0
- Authority
- GB
- United Kingdom
- Prior art keywords
- inter
- processor interface
- processor
- interface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3877—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor
- G06F9/3879—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor for non-native instruction execution, e.g. executing a command; for Java instruction set
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
- G06F15/8053—Vector processors
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- Multi Processors (AREA)
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB8806864A GB2217064A (en) | 1988-03-23 | 1988-03-23 | Interfacing asynchronous processors |
EP19890302829 EP0340901A3 (en) | 1988-03-23 | 1989-03-22 | Access system for dual port memory |
JP1069396A JPH0235559A (en) | 1988-03-23 | 1989-03-23 | Double buffering subsystem |
US07/925,238 US5329630A (en) | 1988-03-23 | 1992-07-31 | System and method using double-buffer preview mode |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB8806864A GB2217064A (en) | 1988-03-23 | 1988-03-23 | Interfacing asynchronous processors |
Publications (2)
Publication Number | Publication Date |
---|---|
GB8806864D0 true GB8806864D0 (en) | 1988-04-27 |
GB2217064A GB2217064A (en) | 1989-10-18 |
Family
ID=10633929
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB8806864A Withdrawn GB2217064A (en) | 1988-03-23 | 1988-03-23 | Interfacing asynchronous processors |
Country Status (1)
Country | Link |
---|---|
GB (1) | GB2217064A (en) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FI105727B (en) | 1997-05-15 | 2000-09-29 | Nokia Networks Oy | Method and arrangement for connecting the processor to an ASIC |
GR1005968B (en) * | 2006-09-21 | 2008-07-04 | Μιχαηλ Φωτιου Δοσης | Generalized communication method between circuits of hierarchic co-processors of special purpose. |
FR3052576B1 (en) * | 2016-06-14 | 2018-07-13 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | ASYNCHRONOUS PROCESSOR CORE AND COMMUNICATOR SENSOR NODE MICROCONTROLLER COMPRISING SUCH A PROCESSOR CORE |
EP4123969A1 (en) | 2021-07-19 | 2023-01-25 | Ratier-Figeac SAS | Rescheduling mechanism for asynchronous devices |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3676860A (en) * | 1970-12-28 | 1972-07-11 | Ibm | Interactive tie-breaking system |
US3988716A (en) * | 1974-08-05 | 1976-10-26 | Nasa | Computer interface system |
US4445197A (en) * | 1981-10-27 | 1984-04-24 | International Business Machines Corporation | Weak synchronization and scheduling among concurrent asynchronous processors |
US4594657A (en) * | 1983-04-22 | 1986-06-10 | Motorola, Inc. | Semaphore for memory shared by two asynchronous microcomputers |
US4709326A (en) * | 1984-06-29 | 1987-11-24 | International Business Machines Corporation | General locking/synchronization facility with canonical states and mapping of processors |
-
1988
- 1988-03-23 GB GB8806864A patent/GB2217064A/en not_active Withdrawn
Also Published As
Publication number | Publication date |
---|---|
GB2217064A (en) | 1989-10-18 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |