GR1005968B - Generalized communication method between circuits of hierarchic co-processors of special purpose. - Google Patents
Generalized communication method between circuits of hierarchic co-processors of special purpose.Info
- Publication number
- GR1005968B GR1005968B GR20060100529A GR20060100529A GR1005968B GR 1005968 B GR1005968 B GR 1005968B GR 20060100529 A GR20060100529 A GR 20060100529A GR 20060100529 A GR20060100529 A GR 20060100529A GR 1005968 B GR1005968 B GR 1005968B
- Authority
- GR
- Greece
- Prior art keywords
- master
- slave
- processor
- hierarchic
- processors
- Prior art date
Links
- 238000000034 method Methods 0.000 title abstract 3
- 230000001360 synchronised effect Effects 0.000 abstract 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3877—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Multi Processors (AREA)
- Communication Control (AREA)
Abstract
The generalized communication method between circuits of hierarchic coprocessors of special purpose consists of the hierarchy of a total of co-processors that implement a specific application, of their operation mode and of synchronization to computer environment and of a generalized protocol of synchronous hand-shaking between the master processor and the slave co-processor. The difference between the master and the slave, as regards the proposed communication methodology, is based on the factthat the master controls the start of the execution of the slave and the slave responds to the processing order by the master. The slave executes the processing, according to the algorithm that implements and notifies the master for the completion of the execution of its algorithm. Subsequently, the master reads the results of processing and notifies the slave thereof. After that, the slave co-processor is `liberated` by the master`s control, until its services are required again by the controlling environment (e. g. the master itself).
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GR20060100529A GR1005968B (en) | 2006-09-21 | 2006-09-21 | Generalized communication method between circuits of hierarchic co-processors of special purpose. |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GR20060100529A GR1005968B (en) | 2006-09-21 | 2006-09-21 | Generalized communication method between circuits of hierarchic co-processors of special purpose. |
Publications (2)
Publication Number | Publication Date |
---|---|
GR20060100529A GR20060100529A (en) | 2008-04-15 |
GR1005968B true GR1005968B (en) | 2008-07-04 |
Family
ID=39078715
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GR20060100529A GR1005968B (en) | 2006-09-21 | 2006-09-21 | Generalized communication method between circuits of hierarchic co-processors of special purpose. |
Country Status (1)
Country | Link |
---|---|
GR (1) | GR1005968B (en) |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2217064A (en) * | 1988-03-23 | 1989-10-18 | Benchmark Technologies | Interfacing asynchronous processors |
US5923893A (en) * | 1997-09-05 | 1999-07-13 | Motorola, Inc. | Method and apparatus for interfacing a processor to a coprocessor |
EP1071990B1 (en) * | 1998-02-19 | 2002-05-22 | Infineon Technologies AG | Device for the hierarchical and distributed control of programmable modules in highly integrated systems |
-
2006
- 2006-09-21 GR GR20060100529A patent/GR1005968B/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
GR20060100529A (en) | 2008-04-15 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PG | Patent granted | ||
ML | Lapse due to non-payment of fees |
Effective date: 20170411 |