GB846267A - Improvements relating to electrical stages for performing logical functions - Google Patents

Abstract

846,267. Logical gating circuits. FERRANTI Ltd. June 24, 1957 [June 28, 1956; Dec. 11, 1956], Nos. 19986/56 and 37761/57. Class 40(6). A logical circuit comprises a summing transformer having a number of primary windings and one secondary winding a clock pulse generator being connected to a capacitor connected to the secondary winding so that the charge is modified during each period only if the secondary current during that period is of a predetermined sense and value. The output of the capacitor is connected to a stabilized amplifier which conducts during each output period only if the charge has been modified to the predetermined extent during the preceding period, the secondary winding being D.C. restored during each output period. Fig. 1 shows a logical stage in which primary current pulses in windings 11, 12, 13 during each input period defined by pulse trains 26, 29 Fig. 2, applied to terminals 26, 29 respectively are comcombined to produce their alegbraic sum in secondary winding 14. If during any input period this sum exceeds a predetermined value diode 16 passes current to modify the charge in capacitor 25 to a limit fixed by diode 27 and its associated bias source. Diode 27 absorbs surplus current in secondary 14 and prevents pentode 18 from conducting during any input period. At the start of the following output period the rise in voltage of waveform 26 causes pentode 18 to conduct only if the charge on capacitor 25 has been modified during the preceding period to the predertermined limit. The current by resistor 21 which during the input period only flowed in diode 22 is switched to pentode 18 and causes load 20 to be energized by a standard current pulse. The sloping top of waveform 26, Fig. 2, maintains the charge on capacitor 25 constant during each output period so that the grid voltage of amplifier tube 18 is held steady during each output period. The fall of voltage of tube 18 during each output period of waveform 29, Fig. 2, cuts off diode 28 to permit d.c restoration of transformer 10 during that period. Capacitor 25 is discharged by resistor 24 and damping resistor 15 ensures that the magnetization energy of the transformer 10 is dissipated and the logical function of the stage determined solely by the manner in which the primaries 11-13 are pulse energized, the biases and waveform applied to the stage remain the same in each case. To enable the stage to act as a three entry "AND" gate the three input pulses if occurring in the same input period are all applied positively to one only of the primaries each of the others carrying a negative pulse during each input period. If only one primary 12 or 13 carries a negative pulse the gate becomes a "two out of three gate" opening after each input period during which primary 11 carried any two of its positive pulses. If each primary winding is arranged to carry when required an OR gate is provided. If one primary winding carries a positive pulse during each input period and one of the other windings a negative pulse during an appropriate input period an "inhibit" gate is provided. In a modification shown in Fig. 3 the stabilized amplifier is provided by a PNP transistor 118 the associated diodes then being connected in the reverse sense. Fig. 5 shows a modification in which the slower response attributable to the greater interelectrode capacitance of a transistor over a discharge tube is much reduced by the insertion in the amplifier of an emitter follower stage 118.