GB787956A - Improvements in or relating to pulse signal delay circuits - Google Patents

Abstract

787,956. Pulse delaying circuits. CINEMA-TELEVISION, Ltd. Nov. 18, 1955 [Oct. 21, 1954], No. 30335/54. Class 40 (6). Apparatus for delaying each of a succession of pulses in a train by a predetermined delay comprises deriving control signals from the commencement and termination of each applied pulse, generating a delay pulse of duration equal to the required delay in response to each of said control signals and deriving a further control signal from the termination of each of the delay pulses in response to which the required delayed pulse train is generated. Fig. 1 shows a block schematic of an apparatus in which the input pulse train at 1 is applied to a device 2 from which control signals are generated at the commencement and termination of each applied pulse, this may for example comprise a differentiating circuit followed by diodes connected in opposed plurality. The control signals are applied to circuits 3, 4 which are triggered to generate pulses of duration equal to the required delay. These pulses are applied to circuits 5, 6 from which further control signals are produced coincident in time with the termination of the applied pulses and these control signals are applied to bistable trigger circuits 7 to generate an output pulse which is initiated by a signal from 5 and terminated by a signal from 6, thus a pulse train is produced at output 8 which is identical with that at input 1 but delayed by a predetermined period. Fig. 2 shows a modification in which an input pulse train, Fig. 3, A, is applied at terminal 10 to a cathode coupled pair of discharge tubes 11, 12. The output from the anodes of which are applied to the control grid of respective flip-flop circuits comprising cathode coupled tubes 21, 22 and 21A, 22A, respectively. The couplings from the anodes of tubes 11, 12 comprise differentiating circuits so that signals, Figs. 3, B, C, are produced at the control grids of tubes 21, 21A respectively. The flip-flop circuits generate output pulses, Figs. 3, D, E, of the required delay time, these are further differentiated and applied to cathode coupled amplifiers 31, 32, 31A, 32A respectively which are arranged to amplify only the negative going spikes, Figs. 3, F, G, which are coincident with the trailing edge of the pulses, Figs. 3, D, E. The output from tubes 32, 32A are combined in a further cathode coupled tube pair 39, 40 to generate the waveform, Fig. 3, H, at the anode of tube 40. This is applied to the bistable trigger circuit comprising cathode coupled tubes 49, 52, to generate an output pulse train at 61, Fig. 3, J, which is identical with the input pulse train, Fig. 3, A, but delayed by a time period equal to the duration of the pulses generated by the flip-flop circuits 21, 22, 21A, 22A, respectively. The amplitude of the output pulse train may be made identical with that of the input train by the use of a gain control circuit using a control signal derived from the input pulse train and applied for example to the amplifier stages.