GB1224921A - A cascaded coder - Google Patents

Abstract

1,224,921. Analogue/digital converters. FUJITSU Ltd. 27 May, 1968 [27 May, 1967; 21 Aug., 1967], No. 25343/68. Heading G4H. A coder for pulse amplitude modulated signals comprising a plurality of series connected stages 111, 121 .. 191 (Fig. 3), each including a source of bias voltage which may modify the input signal before it is fed to the next stage includes pulse-shaping circuits 112, 122 . . . 182 between some of the stages. In the embodiment described in which a reflected binary output pulse train at terminal 199 is obtained via delays 113, 123 ... 183, each pulseshaping circuit includes a sampling circuit receiving a source of timing pulses and a holding circuit. Each coder stage includes a comparator which determines the polarity of the input signal and delivers the bit of the digital signal associated with the stage, a rectifier which delivers a negative output, a positive source of bias voltage and an amplifier with a gain of approximately two. Preferably the amplifier which may include a resonant circuit is chosen to have a gain of more than two for low frequencies to reduce the time interval taken for the amplifier output to reach its ideal value. The input to the amplifier may also consist of the original input pulse together with a pulse obtained by attenuating and delaying this pulse (Fig. 13, not shown).