GB2527007A

GB2527007A - Signal processing device

Info

Publication number: GB2527007A
Application number: GB1517671.2A
Authority: GB
Inventors: Yasunori Ido
Original assignee: Mitsubishi Electric Corp
Current assignee: Mitsubishi Electric Corp
Priority date: 2013-03-29
Filing date: 2013-03-29
Publication date: 2015-12-09
Anticipated expiration: 2033-03-29
Also published as: HK1212777A1; JPWO2014155706A1; GB201517671D0; KR20150134405A; WO2014155706A1; GB2527007B; CN105102991A; CN105102991B; JP5972450B2; KR101795199B1

Abstract

A 1 PPS signal reception unit (101) receives a 1 PPS signal, a clock generation unit (102) generates a clock signal, and a clock deviation measurement unit (103) measures a clock deviation that is the frequency deviation of the clock signal from the 1 PPS signal. A deviation measurement value storage unit (301) stores a plurality of clock deviation measurement values acquired from a plurality of measurements by the clock deviation measurement unit. A clock deviation value generation unit (302) compares the most recent of the plurality of clock deviation measurement values stored in the deviation measurement value storage unit (301) with the other clock deviation measurement values and outputs the most recent clock deviation measurement value to the sampling period counting unit (105) if the most recent clock deviation measurement value matches with the other clock deviation measurement values or outputs one clock deviation measurement value from among the other clock deviation measurement values to the sampling period counting unit (105) if the most recent clock deviation measurement value does not match with the other clock deviation measurement values.

Description

SPECIFICATION

Title of Invention: SIGNAL PROCESSING DEVICE

Technical Field

[0001] The present invention relates to a technology for time synchronization control, in particular, to a technology for time synchronization control in a device that collects electricity amounts of a power transmission line and a bus bar,

Background Art

[0002] There is a protective control system in which electricity amounts (voltage values, current values) of a power transmission line and a bus bar are collected at a plurality of points, and when a malfunction is detected from these electricity amounts, a power system is immediately shut off to prevent spreading of an accident.

In this protective control system, in order to reduce phase shift in the collected electricity amounts, a signal which is synchronized among the collection points is required as the basis for collecting the electricity amounts.

In a recent protective relay device, a plurality of data collection devices (to be also referred to as MUs (Merging Units) hereinafter) are connected to one arithmetic device (to be also referred to as an lED (Intelligent Electronic Device) hereinafter) through a local area network (process bus).

Each MU achieves timing synchronization based on a synchronization signal (IPPS (I Pulse Per Second) signal), thereby making data sampling timing and a time stamp value coincide with one another among the MUs.

Citation List Patent Literature [0003] Patent Literature 1: JP 2001-305177 A

Summary of Invention

Technical Problem [0004] The IPPS signal is received at intervals of one second.

S For this reason, each MU is required to include a highly accurate crystal oscillator (frequency deviation: a few ppm over or under) in a clock generation circuit to generate a highly accurate clock with a small frequency deviation, so as to contain misalignment in sampling timing among the MUs within a few microseconds over or under in one second.

Therefore, there is a problem that a low-cost general-purpose oscillator circuit (with a frequency deviation accuracy of approximately +50 ppm) generally being used in a digital circuit cannot be used, leading to an increase in cost.

[0005] The present invention has been made to solve the above problem, and primarily aims to achieve highly accurate synchronization control even when a general-purpose oscillator circuit with a frequency deviation of approximately +50 ppm is used.

Solution to Problem [0006] A signal processing device according to the present invention includes a 1PPS signal receiving unit to receive a]PPS ( Pulse Per Second) signal; a clock generating unit to generate a clock signal having a clock period which is minuscule compared with one second; a clock deviation measuring unit to receive as input the PPS signal from the IPPS signal receiving unit, receive as input the clock signal from the clock signal generating unit, aM each time the tPPS signal is received as input, measure a clock deviation which is a frequency deviation of the clock signal with respect to the 1PPS signal; a deviation measurement value holding unit to hold a plurality of clock deviation measurement values obtained by a plurality of measurements in the clock deviation measuring unit; and a deviation measurement value selecting unit to compare a latest clock deviation measurement value with other clock deviation measurement values among the plurality of clock deviation measurement values being held in the deviation measurement value holding unit, output the latest clock deviation measurement value to an output destination when the latest clock deviation measurement value coincides with the other clock deviation measurement values within an allowable range which is predetermined, and output one clock deviation measurement value among the other clock deviation measurement values to the output destination when the latest clock deviation measurement value does not coincide with the other clock deviation measurement values within the allowable range.

Advantageous Effects of Invention [0007] According to the present invention, by using a clock deviation between the 1PPS signal and a clock signal having a clock period which is minuscule compared with one second, highly accurate synchronization control can be performed even when a general-purpose oscillator circuit with a frequency deviation of approximately 50 ppm is used.

A plurality of clock deviation measurement values are held, aM when the latest clock deviation measurement value does not coincide with the other clock deviation measurement values, another clock deviation value is selected instead of the latest clock deviation measurement value. Thus, even when a malfunction occurs in the reception of the IPPS signal, the malfunction will not affect the generation of a sampling signal.

Brief Description of Drawings

[0008] Fig. lisa diagram illustrating an example of the configuration of a data collection device according to a first embodiment; Fig. 2 is a diagram illustrating an example of the operation of the data collection device according to the first embodiment; Fig. 3 is a diagram illustrating an example of the configuration of a data collection device according to a second embodiment; Fig. 4 is a diagram illustrating an example of the operation of the data collection device according to the second embodiment; Fig. S is a diagram illustrating a configuration which is a basis for the data collection devices according to the first and second embodiments; Fig. 6 is a diagram for describing the principle of operation of the data collection devices according to the first and second embodiments; Fig. 7 is a diagram for describing the principle of operation of the data collection devices according to the first and second embodiments; is Fig. 8 is a diagram for describing the principle of operation of the data collection devices according to the first and second embodiments; and Fig. 9 is a diagram illustrating an example of the hardware configuration of the data collection devices according to the first and second embodiments.

Description of Embodiments

[0009] First Embodiment This embodiment describes a data collection device (MU) that calculates a correction value of a counter to decide a period for sampling an electricity amount (sampling signal generating counter) in accordance with a clock deviation measurement value.

This enables highly accurate synchronization even when a general-purpose oscillator circuit with a frequency deviation of approximat&y +50 ppm is used.

The data collection device according to this embodiment holds a plurality of cloclc deviation measurement values. If the latest cloclc deviation measurement value coincides with the immediately preceding clock deviation measurement value, the data S collection device selects the latest clock deviation measurement value. If the latest clock deviation measurement value does not coincide with the immediately preceding clock deviation measurement value, the data collection device selects the immediately preceding clock deviation value instead of the latest clock deviation measurement value.

Therefore, even when a malfunction such as a disruption of a IPPS signal occurs, the malfunction will not affect the generation of a sampling signal.

[00 to] Fig. t illustrates an example of the configuration of a data collection device according to this embodiment.

The data collection device 100 corresponds to an example of a signal processing device.

The data collection device 100 according to this embodiment includes, as main features, a deviation measurement value holding unit 301 to hold a plurality of clock deviation measurement values and a clock deviation value generating unit 302 to select a clock deviation measurement value to be output to a sampling period counting unit of a later stage, out of the plurality of clock deviation measurement values being held in the deviation measurement value holding unit 301.

[001]] For ease of understanding, the principle of operation of the data collection device 00 according to this embodiment will be described first, using a data collection device having a configuration not including the deviation measurement value holding unit 301 and the clock deviation value generating unit 302.

[0012] Fig. 5 illustrates the configuration of a data collection device 150 which corresponds to the data collection device 100 according to this embodiment excluding the deviation measurement value holding unit 301 arid the clock deviation value generating unit 302.

[0013] The data collection device 150 receives the I PPS signal, and transmits data indicating a measured electricity amount to an arithmetic device 200.

The arithmetic device 200 which is an lIED detects a malfunction in a power system, and shuts down the system to contain spreading of an accident.

The I PPS signal may be transmitted from the arithmetic device 200 or from another device having a GPS (Global Positioning System) receiver, [0014] In the data collection device 150, a 1PPS signal receiving unit 101 receives the 1PPS signal.

[0015] A clock generating unit 102 generates an operating clock signal (to be referred to simply as a clock signal hereinafter) of the data collection device 150.

A clock period of the clock signal is minuscule compared with one second.

[0016] A clock deviation measuring unit 103 measures a clock deviation which is a frequency deviation of the clock signal of the data collection device 150 from a period of the IPPS signal.

[0017] A deviation measurement value holding unit 104 holds a clock deviation measurement value measured by the clock deviation measuring unit 103.

Unlike the deviation measurement value holding unit 301 of Fig, 1, the deviation measurement value holding unit 104 holds only one clock deviation measurement value, [0018] The sampling period counting unit 105 counts time intervals at which the electricity amount is sampled, The sampling period counting unit 105 receives as input the I PPS signal from the 1PPS signal receiving unit 101, and receives as input the clock signal from the clock generating unit 102. When the IPPS signal is received as input, the sampling period counting unit 105 starts counting in accordance with the clock period of the clock signal. After counting to a full count value, the sampling period counting unit 105 starts counting from a start count value.

The sampling period counting unit 105 corresponds to an example of a counter.

[00t9] A sampling signal generating unit 106 generates a sampling timing signal (to be also referred to as a sampling signal) which is a pulse indicating sampling timing, using the count value of the sampling period counting unit 105, [0020] An electricity amount measuring unit 107 measures the electricity amount of the power system at the timing of the pulse (sampling signal) generated by the sampling signal generating unit 106.

[0021] A data generating unit 108 converts the electricity amount measured by the electricity amount measuring unit 107 into digital data in a communication frame format which can be transmitted to a local area network (process bus).

[0022] A communication unit 109 transmits the digital data generated by the data generating unit 108 to the arithmetic device 200 through the local area network (process bus).

[0023] An example of the operation of the data collection device 150 will now be described.

[0024] The I PPS signal is input to the data collection device 150 from the arithmetic device 200 using transmission means such as an optical fiber cable or an electric signal cable.

The 1PPS signal is a pulse signal indicating a period of one second in absolute time and having a very small frequency error of a few ppm or less.

The 1PPS signal is received by the IPPS signal receiving unit 101, and is distributed to the clock deviation measuring unit 103 and the sampling period counting unit 105.

[0025] In the clock generating unit 102, the clock signal of the data collection device 150 is generated, and is distributed to the clock deviation measuring unit 103 and the sampling period counting unit 105.

In the clock deviation measuring unit 103, a clock deviation is measured, which is misalignment between the reception timing of the IPPS signal and one second counted based on the clock signal of the data collection device 150, and a measurement result is held in the deviation measurement value holding unit 104.

[0026] The sampling period counting unit 105 is a counter which counts up or counts down based on the clock signal generated by the clock generating unit 102.

[0027] The upper limit value of the count value (full count value) for generating the sampling period is decided so as to coincide with the accuracy of the IPPS signal, based on the clock deviation measurement value being held in the deviation measurement value holding unit 104.

For example, when the frequency of an alternating current of the power system is 50 Hz and the number of sampling times per period of the alternating current is 80 times, the sampling period is 250 microseconds.

When the accuracy of the 1PPS signal is 0 ppm, 250 microseconds coincide with 20000 times of counting with an 80-MHz counter.

When the frequency deviation of the clock signal is -50 ppm, 20000 times of counting results in 250.0125 microseconds, so that the sampling period becomes longer by 12,5 nanoseconds, Accordingly, when the clock deviation measurement value being held in the deviation measurement value holding unit 104 is -50 ppm, the duration of the sampling period is made to coincide with 250 microseconds (duration with 0 ppm) by setting the count upper limit value of the 80-MHz counter to 19999 times.

[0028] The sampling signal generating unit 106 generates the sampling timing signal to be provided to the electricity amount measuring unit 107, using the count value generated by the sampling period counting unit 105.

Upon receiving the sampling timing signal generated by the sampling signal generating unit 106, the electricity amount measuring unit 107 measures the electricity amount (current, voltage) of the power system.

The digital data generating unit 108 arranges the electricity amount measured by the sampling signal generating unit 106 into a communication frame format which can be transmitted by the communication unit 109 so as to transmit the electricity amount to the arithmetic device 200.

The communication unit 109 transmits the communication frame generated by the digital data generating unit 108 to the arithmetic device 200.

[0029] With reference to Fig. 6, the operation of the clock deviation measuring unit 103, the deviation measurement value holding unit 104, and the sampling period counting unit 105 will now be described.

[0030] Upon receiving the IPPS signal, the clock deviation measuring unit 103 starts generating a 10-millisecond period pulse which is counted based on the clock signal.

At the time when the 10-millisecond pulse count value being counted based on the 0-millisecond period pulse has reached 99, the clock deviation measuring unit 103 causes a clock deviation measuring counter which counts based on the clock signal to start counting.

After the counting is started, the clock deviation measuring unit 103 causes the clock deviation measuring counter to stop the counting when the 1PPS signal is received.

[00311 By subtracting an ideal count value for 10 milliseconds (count value with a cloclc deviation of 0 ppm) from the count value of the clock deviation measuring counter, it is possible to obtain a clock frequency deviation accumulation amount of the clock signal in an interval between each reception of the 1PPS signal (for example, a period of time corresponding to a rectangle indicated by a reference sign 500 in Fig. 6).

The deviation accumulation amount (clock deviation measurement value) obtained by the clock deviation measuring unit 103 is held in the deviation measurement value holding unit 104.

[0032] With reference to Fig. 7, the operation of the clock deviation measuring unit 103 will be described in more detail.

[0033] When the 1PPS signal is input to the clock deviation measuring unit 103, a 10-millisecond counter which counts in accordance with the clock period of the clock signal starts operating.

For example, when the clock signal is 80 Tvll-Iz, counting is performed in units of 12.5 nanoseconds, so that 10 milliseconds are reached when the count is 800000.

When the count of the counter reaches 800000 in the 99th time of counting 10 milliseconds, one second according to the measurement of the clock signal of the data collection device 150 has passed.

A gap between this one second which is counted based on the clock signal and the reception timing of the IPPS signal is the clock deviation measurement value.

In Fig. 6, the 1PPS signal is received when the count of the 10-millisecond counter is 798400. Thus, the counting by the clock signal is behind by 20 microseconds ((800000-798400) x 12.5 nanoseconds) in one second, and this value is the clock deviation measurement value.

With the operation as described above, the clock deviation measuring unit 103 measures the clock deviation which is a discrepancy time per second of the clock signal with respect to the I PPS signal, and stores the clock deviation measurement value in the deviation measurement value holding unit 104.

When the counting of one second by the clock signal is behind the IPPS signal by 20 microseconds, the sampling signal is output only 3999 times in one second, resulting in a failure to output the sampling signal with the period of 250 microseconds, as illustrated in Fig. 8.

Therefore, it is necessary to change the upper limit value (hill count value) of the sampling period counter to compensate for 20 microseconds.

[0034] The sampling period counting unit 105 has a built-in sampling signal generating counter, as illustrated in Fig. 6.

The sampling period counting unit 105 calculates a deviation accumulation amount (clock deviation measurement value) per sampling period, using the deviation accumulation amount (clock deviation measurement value) in one second being held in the deviation measurement value holding unit 104.

For example, when the sampling period is 250 microseconds as described above, the sampling signal generating counter performs sampling 4000 times in one second. Thus, the sampling period counting unit 105 obtains the deviation accumulation amount (clock deviation measurement value) per sampling period by dividing the deviation accumulation amount (clock deviation measurement value) in one second being held in the deviation measurement value holding unit 104 by 4000.

The sampling period counting unit 105 adds or subtracts the calculated deviation accumulation amount to or from an ideal value for the sampling period count (count value with a clock deviation of 0 ppm), and sets this value as the upper limit value (full count value) of the sampling signal generating counter.

In Fig. 6, a reference sign 600 indicates the upper limit value of the sampling signal generating counter.

The sampling signal generating unit 106 monitors the count value of the sampling signal generating counter, and enables the sampling timing signal to the electricity amount measuring unit 107 at the timing when the count value reaches 0 (start count value).

The value indicated by the reference sign 600 may be different for each sampling, If the deviation accumulation amount (clock deviation measurement value) in one second is not divisible by the number of sampling times or is smaller than one, fine adjustment can be made by changing the upper limit value of the sampling signal generating counter for each sampling. In three samplings, for example, the value of the reference sign 600 may be set to the ideal value (count value with a clock deviation of 0 ppm) for one sampling, and to a value smaller by 2 than the ideal value for the other two samplings, In this case, an adjustment of 4 clocks is made in three samplings, so that an adjustment of 1.33 cloclcs per sampling can be made.

[0035] In this way, the data processing device 150 illustrated in Fig. 5 measures the deviation amount of the clock signal with respect to the 1PPS signal, and decides the count upper limit value of the sampling period counting unit 105 using a measurement result, so as to make the duration of the sampling period coincide with the ideal duration (duration with 0 ppm), [0036] Next, it will be described that with the data collection device 100 of Fig. t it is possible to avoid the generation of an incorrect sampling period using an incorrect clock deviation measurement value when a reception malfunction occurs, such as a temporary in I., disruption in the input of the 1PPS signal.

[0037] The configuration of Fig. 1 differs from the configuration of Fig. Sin that the deviation measurement value holding unit 104 is replaced by the deviation measurement value holding unit 301 and the clock deviation value generating unit 302 is added in S Fig. 1.

The components other than the deviation measurement value holding unit 301 and the clock deviation value generating unit 302 are substantially the same as those illustrated in Fig, 5.

[0038] The deviation measurement value holding unit 30] holds a plurality of clock deviation measurement values which are measured in the clock deviation measuring unit 103.

That is, the deviation measurement value holding unit 30] holds a plurality of clock deviation measurement values which are obtained by a plurality of measurements by the clock deviation measuring unit 103, [0039] The clock deviation value generating unit 302 compares the plurality of clock deviation measurement values in the deviation measurement value holding unit 30t, and selects a clock deviation measurement value to be output to the sampling period counting unit 105 being an output destination, out of the plurality of clock deviation measurement values.

The clock deviation value generating unit 302 corresponds to an example of a deviation measurement value selecting unit, [0040] With reference to Fig, 2, an example of the operation of the data collection device 100 will now be described.

[004t] The deviation measurement value holding unit 301 has a plurality of holding units (memory areas), and stores the latest clock deviation measurement value in a holding unit 1, the second-latest clock deviation measurement value in a holding unit 2, and the third-latest clock deviation measurement value in a holding unit 3.

The deviation amount of the clock signal with respect to the]PPS signal varies with environmental factors such as, for example, a difference in day and night temperatures, but does not change in a short period of time such as a few seconds.

For this reason, the three clock deviation measurement values in the deviation measurement value holding unit 301 are expected to coincide with one another.

[0042] The clock deviation value generating unit 302 compares the plurality of clock deviation measurement values in the deviation measurement value holding unit 301. If the latest clock deviation measurement value coincides with the other clock deviation measurement values, the clock deviation value generating unit 302 determines that the latest clock deviation measurement value is proper, and selects the latest clock deviation measurement value as the value to be output to the sampling period counting unit 105.

If the latest clock deviation measurement value does not coincide with the other clock deviation measurement values, the clock deviation value generating unit 302 recognizes that a malfunction such as a disruption of the 1PPS signal has occurred, and maintains the current value without updating the clock deviation measurement value.

That is, the clock deviation value generating unit 302 selects the clock deviation measurement value being held in the holding unit 2 as the value to be output to the sampling period counting unit 105.

Then, the clock deviation value generating unit 302 outputs the selected clock deviation measurement value to the sampling period counting unit 105.

[0043] With this arrangement, even when a malfunction occurs in the reception of the 1PPS signal, the malfunction can be prevented from affecting the generation of the sampling signal.

It has been described with reference to Fig. 1 and Fig. 2 that the deviation measurement value holding unit 301 has three holding units. However, the number of holding units may be any number equal to or greater than two.

It has been described above that the latest clock deviation measurement value is output to the sampling period counting unit 105 only when the latest clock deviation measurement value in the deviation measurement value holding unit 301 completely coincides with the other clock deviation measurement values.

Alternatively, a predetermined allowable range may be provided, and the latest clock deviation measurement value maybe output to the sampling period counting unit 105 when the latest clock deviation measurement value coincides with the other clock deviation measurement values within this allowable range.

[0044] Second Embodiment The first embodiment above has described that the deviation amount of the clock signal with respect to the IPPS signal is measured, and that the count upper limit is value of the sampling period counting unit is decided using a measurement result, so as to make the duration of the sampling period coincide with the ideal duration (duration with 0 ppm).

The first embodiment has also presented an example of preventing the generation of the sampling signal using an incorrect clock deviation measurement value when a malfunction occurs in the reception of the 1PPS signal.

This embodiment presents a method for aligning a position to start the generation of the sampling timing signal with the reception timing of the IPPS signal when a dismption of the IPPS signal continues over a prolonged period of time or when the IPPS signal is received for the first time after the data collection device is powered on, [0045] With reference to Fig. 3, a sampling position aligning unit 501 generates a timing correction amount for aligning the position to start the generation of the sampling timing signal to be generated by the sampling signal generating unit 106 with the reception timing of the I PPS signal.

More specifically the sampling position aligning unit 501 monitors the input timing of the 1PPS signal to the sampling period counting unit tOS and the timing of the start count value in the sampling period counting unit 105.

Then, if the timing of the start count value does not coincide with the input timing of the I PPS signal, the sampling position aligning unit 501 calculates a timing correction value for making the timing of the start count value coincide with the input timing of the 1PPS signal.

Then, the sampling period counting unit 105 changes the count upper limit value (full count value) using the timing correction value calculated by the sampling position aligning unit 501, so as to make the timing of the start count value coincide with the input timing of the tPPS signal.

The sampling position aligning unit 501 corresponds to an example of a timing correction value calculating unit.

The components other than the sampling position aligning unit 501 are substantially the same as those illustrated in Fig. 1.

[0046] With reference to Fig. 4, an example of the operation of the data collection device 00 according to this embodiment will now be described.

[0047] To make sampling timing coincide with one another among a plurality of data collection devices, it is necessary to make the duration of the sampling period coincide with one another, and also to make the start position of the sampling timing signal coincide with the reception timing of the I PPS signal.

Therefore, a calculation formula to decide the upper limit value of the sampling signal generating counter requires an item (2) for setting the duration of the sampling period in accordance with the clock deviation measurement value and also an item (3) for shifting the generation timing of the sampling timing signal.

<Calculation formula to decide the upper limit value of the sampling signal generating counter> Counter upper limit value = (I) Counter base value (period count value with 0 ppm) ± (2) Clock deviation value ± (3) Timing correction amount [0048] When a dismption of the PPS signal continues over a prolonged period of time or when the 1PPS signal is received for the first time after the data collection device is powered on, there exists a synchronization misalignment amount (misalignment between the position of the sampling timing signal and the reception position of the IPPS signal) in Fig. 4, and this synchronization misalignment amount is a value which varies with each data collection device.

[0049] The sampling position aligning unit 501 calculates the synchronization misalignment amount from the count value of the sampling signal generating counter at the time of the reception of IPPS.

Then, the sampling position aligning unit 501 outputs the calculated synchronization misalignment amount to the sampling period counting unit 105 as the timing correction amount.

The sampling period counting unit 105 can adjust the synchronization misalignment amount to zero by changing the upper limit value of the counter based on the above calculation formula to decide the upper limit value of the sampling signal generating counter.

[0050] The sampling position aligning unit 50] decides a direction in which the sampling timing signal is adjusted, that is, whether to add or subtract the timing correction amount of the above item (3), based on the count value of the sampling signal generating counter at the time of the reception of the IPPS signal.

With reference to Fig. 4, when the reception timing of the I PPS signal is before S an intermediate value of the sampling signal generating counter and after the start count value ((11) in Fig. 4), the sampling position aligning unit SOt makes the sampling timing signal coincide with the reception timing of the IPPS signal by subtracting the timing correction amount from the count upper limit value.

When the reception timing of the I PPS signal is after the intermediate value of the sampling signal generating counter and before the count upper limit value ((2) in Fig. 4), the sampling position aligning unit SOt makes the sampling timing signal coincide with the reception timing of the I PPS signal by adding the timing correction amount to the count upper limit value.

[005 t] The adjustment using the timing correction amount of the above item (3) may be made with a plurality of separate adj ustments instead of a single adjustment.

For example, in a case where a change in the interval of the sampling timing signal needs to be limited to 75 nanoseconds or less and the synchronization misalignment amount is 750 ns, the amount to be adjusted at a time may be set to a maximum of 75 ns (corresponding to counting 4 times with the 80-TvlHz counter) and the upper limit value of the counter may be adjusted tO times.

Alternatively, the amount to be adjusted may be different each time.

[0052] As described above, according to this embodiment, when a disruption of the 1PPS signal continues over a prolonged period of time or when the 1PPS signal is received for the first time after the data collection device is powered on, the position to start the generation of the sampling timing signal can be made to coincide with the reception timing of the 1PPS signal.

[0053] The first and second embodiments have described examples in which the sampling period counting unit 105 is configured to count by incrementing the count, so that the start count value is the lower limit value and the full count value is the upper S limit value of the sampling period counting unit 105.

When the sampling period counting unit 105 is configured to count by decrementing the count, the start count value is the upper limit value and the full count value is the lower limit value of the sampling period counting unit 05, [0054] Lastly, with reference to Fig. 9, an example of the hardware configuration of the data collection device 100 presented in each of the first and second embodiments will be described.

The data collection device 100 is a computer, and each component of the data collection device 100 can be implemented by a program.

As the hardware configuration of the data collection device tOO, a control device 90t, an external memory device 902, a main memory device 903, a communication device 904, an input/output device 905, a clock generation circuit 906, and a counter 907 are connected to a bus.

[0055] The control device 901 is a CPU that executes programs.

The external memory device 902 is, for example, a ROM (Read Only Memory), a flash memory, and a hard disk device.

The main memory device 903 is a RAM (Random Access Memory).

The deviation measurement value holding unit 301 is realized, for example, by the main memory device 903.

The communication device 904 corresponds to a physical layer of each of the IPPS signal receiving unit 101 and the communication unit 109, The input/output device 905 is, for example, a mouse, a keyboard, a display device, and the like.

The cloclc generation circuit 906 is provided with a crystal oscillator, and generates the cloclc signal of the data collection device 100, The clock generating unit 102 is realized by the clock generation circuit 906.

The sampling period counting unit 105 is realized by the counter 907.

[0056] The programs are normally stored in the external memory device 902, and are loaded into the main memory device 903 to be sequentially read and executed by the control device 901.

The programs realize the functions described as "units" (excluding the clock generating unit 102 and the deviation measurement value holding unit 30 t; the same also applies hereinafter) illustrated in Fig. I and Fig. 3, Further, the external memory device 902 also stores an operating system (OS), and at least a part of the OS is loaded into the main memory device 903. The control device 90 t executes each program that realizes the function of each "unit" illustrated in Fig. 1 while executing the OS.

Information, data, signal values, and variable values indicating results of processes described as "measure", "count", "change", "decide", "set", "specify", "calcu'ate", "recognize", "determine", "select", "generate", "input", "receive", and so on in the description of the first and second embodiments are stored as files in the main memory device 903.

[0057] The configuration of Fig. 9 is an example of the hardware configuration of the data collection device tOO, arid the hardware configuration of the data collection device is not limited to and may be different from the configuration described in Fig. 9.

Reference Signs List [0058] 100: data collection device, 101: 1PPS signal receiving unit, 102: clock generating unit, 103: clock deviation measuring unit, 104: deviation measurement value holding unit, 105: sampling period counting unit, 106: sampling signal generating unit, 07: electricity amount measuring unit, 108: data generating unit, 109: communication unit, 301: deviation measurement value holding unit, 302: clock deviation value generating unit, 5011 sampling position aligning unit