GB2520603B - Atomic memory update unit and methods - Google Patents
Atomic memory update unit and methodsInfo
- Publication number
- GB2520603B GB2520603B GB1416844.7A GB201416844A GB2520603B GB 2520603 B GB2520603 B GB 2520603B GB 201416844 A GB201416844 A GB 201416844A GB 2520603 B GB2520603 B GB 2520603B
- Authority
- GB
- United Kingdom
- Prior art keywords
- methods
- update unit
- memory update
- atomic memory
- atomic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30072—Arrangements for executing specific machine instructions to perform conditional operations, e.g. using predicates or guards
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
- G06F9/30087—Synchronisation or serialisation instructions
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3824—Operand accessing
- G06F9/3834—Maintaining memory consistency
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T1/00—General purpose image data processing
- G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T15/00—3D [Three Dimensional] image rendering
- G06T15/10—Geometric effects
- G06T15/40—Hidden part removal
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Image Generation (AREA)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201361882755P | 2013-09-26 | 2013-09-26 | |
US201461955086P | 2014-03-18 | 2014-03-18 | |
US14/494,496 US9466091B2 (en) | 2013-09-26 | 2014-09-23 | Atomic memory update unit and methods |
Publications (3)
Publication Number | Publication Date |
---|---|
GB201416844D0 GB201416844D0 (en) | 2014-11-05 |
GB2520603A GB2520603A (en) | 2015-05-27 |
GB2520603B true GB2520603B (en) | 2016-04-06 |
Family
ID=51869401
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB1416844.7A Active GB2520603B (en) | 2013-09-26 | 2014-09-24 | Atomic memory update unit and methods |
Country Status (2)
Country | Link |
---|---|
DE (1) | DE102014014256A1 (en) |
GB (1) | GB2520603B (en) |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1990005953A1 (en) * | 1988-11-14 | 1990-05-31 | Unisys Corporation | Hardware implemented cache coherency protocole with duplicated distributed directories for high-performance multiprocessors |
US5889983A (en) * | 1997-01-21 | 1999-03-30 | Intel Corporation | Compare and exchange operation in a processing system |
EP0930574A2 (en) * | 1998-01-16 | 1999-07-21 | Sony Corporation | Parallel processor and processing method |
US6651124B1 (en) * | 2000-04-28 | 2003-11-18 | Hewlett-Packard Development Company, L.P. | Method and apparatus for preventing deadlock in a distributed shared memory system |
EP1612661A2 (en) * | 2004-06-30 | 2006-01-04 | Intel Corporation | Compare-and-exchange operation using sleep-wakeup mechanism |
US20060161919A1 (en) * | 2004-12-23 | 2006-07-20 | Onufryk Peter Z | Implementation of load linked and store conditional operations |
US20110153989A1 (en) * | 2009-12-22 | 2011-06-23 | Ravi Rajwar | Synchronizing simd vectors |
-
2014
- 2014-09-24 GB GB1416844.7A patent/GB2520603B/en active Active
- 2014-09-25 DE DE201410014256 patent/DE102014014256A1/en active Pending
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1990005953A1 (en) * | 1988-11-14 | 1990-05-31 | Unisys Corporation | Hardware implemented cache coherency protocole with duplicated distributed directories for high-performance multiprocessors |
US5889983A (en) * | 1997-01-21 | 1999-03-30 | Intel Corporation | Compare and exchange operation in a processing system |
EP0930574A2 (en) * | 1998-01-16 | 1999-07-21 | Sony Corporation | Parallel processor and processing method |
US6651124B1 (en) * | 2000-04-28 | 2003-11-18 | Hewlett-Packard Development Company, L.P. | Method and apparatus for preventing deadlock in a distributed shared memory system |
EP1612661A2 (en) * | 2004-06-30 | 2006-01-04 | Intel Corporation | Compare-and-exchange operation using sleep-wakeup mechanism |
US20060161919A1 (en) * | 2004-12-23 | 2006-07-20 | Onufryk Peter Z | Implementation of load linked and store conditional operations |
US20110153989A1 (en) * | 2009-12-22 | 2011-06-23 | Ravi Rajwar | Synchronizing simd vectors |
Also Published As
Publication number | Publication date |
---|---|
GB2520603A (en) | 2015-05-27 |
GB201416844D0 (en) | 2014-11-05 |
DE102014014256A1 (en) | 2015-03-26 |
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