SG11201602639TA - Concurrently accessing memory - Google Patents

Concurrently accessing memory

Info

Publication number
SG11201602639TA
SG11201602639TA SG11201602639TA SG11201602639TA SG11201602639TA SG 11201602639T A SG11201602639T A SG 11201602639TA SG 11201602639T A SG11201602639T A SG 11201602639TA SG 11201602639T A SG11201602639T A SG 11201602639TA SG 11201602639T A SG11201602639T A SG 11201602639TA
Authority
SG
Singapore
Prior art keywords
accessing memory
concurrently accessing
concurrently
memory
accessing
Prior art date
Application number
SG11201602639TA
Inventor
Ling Ma
Sihai Yao
Lei Zhang
Original Assignee
Alibaba Group Holding Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alibaba Group Holding Ltd filed Critical Alibaba Group Holding Ltd
Publication of SG11201602639TA publication Critical patent/SG11201602639TA/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1615—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement using a concurrent pipeline structrure
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/466—Transaction processing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/466—Transaction processing
    • G06F9/467—Transactional memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores
    • G06F9/526—Mutual exclusion algorithms
    • G06F9/528—Mutual exclusion algorithms by using speculative mechanisms

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
SG11201602639TA 2013-10-18 2014-10-16 Concurrently accessing memory SG11201602639TA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201310492402.3A CN104572506B (en) 2013-10-18 2013-10-18 A kind of method and device concurrently accessing memory
PCT/US2014/060901 WO2015057962A1 (en) 2013-10-18 2014-10-16 Concurrently accessing memory

Publications (1)

Publication Number Publication Date
SG11201602639TA true SG11201602639TA (en) 2016-05-30

Family

ID=51866334

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11201602639TA SG11201602639TA (en) 2013-10-18 2014-10-16 Concurrently accessing memory

Country Status (9)

Country Link
US (1) US20150113244A1 (en)
EP (1) EP3058461A1 (en)
JP (1) JP2016537708A (en)
KR (1) KR20160086820A (en)
CN (1) CN104572506B (en)
HK (1) HK1205806A1 (en)
SG (1) SG11201602639TA (en)
TW (1) TW201516688A (en)
WO (1) WO2015057962A1 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106874074B (en) * 2016-12-26 2020-05-05 哈尔滨工业大学 Concurrent defect avoidance system and method based on software transactional memory
CN110059115B (en) * 2019-03-19 2023-08-11 创新先进技术有限公司 Data reading method and device
CN113421073A (en) * 2019-08-30 2021-09-21 创新先进技术有限公司 Method and apparatus for concurrently executing transactions in a blockchain

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05197604A (en) * 1991-05-21 1993-08-06 Digital Equip Corp <Dec> Multiprocessor computer and operating method thereof
US5504899A (en) * 1991-10-17 1996-04-02 Digital Equipment Corporation Guaranteeing global serializability by applying commitment ordering selectively to global transactions
US6256713B1 (en) * 1999-04-29 2001-07-03 International Business Machines Corporation Bus optimization with read/write coherence including ordering responsive to collisions
US7558923B1 (en) * 1999-12-22 2009-07-07 Intel Corporation Prevention of live-lock in a multi-processor system
US8180977B2 (en) * 2006-03-30 2012-05-15 Intel Corporation Transactional memory in out-of-order processors
US8024714B2 (en) * 2006-11-17 2011-09-20 Microsoft Corporation Parallelizing sequential frameworks using transactions
US7908255B2 (en) * 2007-04-11 2011-03-15 Microsoft Corporation Transactional memory using buffered writes and enforced serialization order
US8661204B2 (en) * 2007-08-15 2014-02-25 University Of Rochester, Office Of Technology Transfer Mechanism to support flexible decoupled transactional memory
US7971248B2 (en) * 2007-08-15 2011-06-28 Microsoft Corporation Tolerating and detecting asymmetric races
US20090138890A1 (en) * 2007-11-21 2009-05-28 Arm Limited Contention management for a hardware transactional memory
US9170844B2 (en) * 2009-01-02 2015-10-27 International Business Machines Corporation Prioritization for conflict arbitration in transactional memory management
US8473952B2 (en) * 2010-06-30 2013-06-25 Oracle International Corporation System and method for communication between concurrent transactions using transaction communicator objects
US9619301B2 (en) * 2011-04-06 2017-04-11 Telefonaktiebolaget L M Ericsson (Publ) Multi-core memory model and speculative mode processor management
US20140075124A1 (en) * 2012-09-07 2014-03-13 International Business Machines Corporation Selective Delaying of Write Requests in Hardware Transactional Memory Systems
US9086974B2 (en) * 2013-09-26 2015-07-21 International Business Machines Corporation Centralized management of high-contention cache lines in multi-processor computing environments

Also Published As

Publication number Publication date
EP3058461A1 (en) 2016-08-24
US20150113244A1 (en) 2015-04-23
WO2015057962A1 (en) 2015-04-23
TW201516688A (en) 2015-05-01
CN104572506B (en) 2019-03-26
CN104572506A (en) 2015-04-29
KR20160086820A (en) 2016-07-20
JP2016537708A (en) 2016-12-01
HK1205806A1 (en) 2015-12-24

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