GB2510956A - Recessed discrete component mounting on organic substrate - Google Patents
Recessed discrete component mounting on organic substrate Download PDFInfo
- Publication number
- GB2510956A GB2510956A GB1321803.7A GB201321803A GB2510956A GB 2510956 A GB2510956 A GB 2510956A GB 201321803 A GB201321803 A GB 201321803A GB 2510956 A GB2510956 A GB 2510956A
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- 239000000758 substrate Substances 0.000 title claims abstract description 73
- 239000010410 layer Substances 0.000 claims abstract description 121
- 238000000034 method Methods 0.000 claims abstract description 51
- 239000004020 conductor Substances 0.000 claims abstract description 34
- 229910000679 solder Inorganic materials 0.000 claims abstract description 15
- 239000003990 capacitor Substances 0.000 claims abstract description 9
- 238000000059 patterning Methods 0.000 claims description 8
- 229920000642 polymer Polymers 0.000 claims description 5
- 239000011521 glass Substances 0.000 claims description 3
- 239000011347 resin Substances 0.000 claims description 3
- 229920005989 resin Polymers 0.000 claims description 3
- 239000012044 organic layer Substances 0.000 claims description 2
- 239000012792 core layer Substances 0.000 abstract description 6
- 230000003071 parasitic effect Effects 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229920003023 plastic Polymers 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4697—Manufacturing multilayer circuits having cavities, e.g. for mounting components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5383—Multilayer substrates
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/183—Components mounted in and supported by recessed areas of the printed circuit board
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09372—Pads and lands
- H05K2201/09472—Recessed pad for surface mounting; Recessed electrode of component
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/01—Tools for processing; Objects used during processing
- H05K2203/0104—Tools for processing; Objects used during processing for patterning or coating
- H05K2203/0126—Dispenser, e.g. for solder paste, for supplying conductive paste for screen printing or for filling holes
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
- H05K2203/0264—Peeling insulating layer, e.g. foil, or separating mask
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/03—Metal processing
- H05K2203/0384—Etch stop layer, i.e. a buried barrier layer for preventing etching of layers under the etch stop layer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
- H05K2203/0756—Uses of liquids, e.g. rinsing, coating, dissolving
- H05K2203/0769—Dissolving insulating materials, e.g. coatings, not used for developing resist after exposure
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0017—Etching of the substrate by chemical or physical means
- H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
- H05K3/0032—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material
- H05K3/0038—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material combined with laser drilling through a metal layer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3442—Leadless components having edge contacts, e.g. leadless chip capacitors, chip carriers
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
- H05K3/3485—Applying solder paste, slurry or powder
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Ceramic Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
A method and device include an organic multiple layer substrate 200 having patterned conductors 215 disposed on a core layer of the substrate. Above the conductors and exposed portions of the substrate is formed a releasable layer (225, fig 2B). An additional layer (240, fig 2C) is formed on top of this before a recess 260 is formed in the additional and releasable layer to expose the patterned conductors by laser scribing the layers. A discrete component is buried within the recessed layer such that the component is recessed from a top layer of the organic multiple layer substrate. The component may be a capacitor, resistor or inductor. The component may be attached to the conductors using solder paste.
Description
RECESSED DISCRETE COMPONENT MOUNTING ON ORGANTC
SUBSTRATE
Background
[0001] Mounting of discrete components on a substrate using surface mount methods can lead to an electronics package having undesirable package height, commonly referred to as a z-height. Using surface mount technologies, discrete components, such as capacitors, resistors, inductors, and other components are typically attached to a die side substrate surface with solder balls on the substrate that are reflowed when the component is placed on the balls. This provides a secure electrical and retentive connection of the component directly to the substrate. Many times, the z-height of a resulting package and component is higher than desired in a product in which the package wifl he used.
Summary
[0002] A device includes an organic multiple layer substrate having patterned conductors disposed on a recessed layer of the organic multiple layer substrate. A discrete component is coupled to the recessed layer via a surface mount process such that the component is recessed from a top layer of the organic multiple layer substrate.
[0003] A method includes patterning conductors on a selected layer of an organic multiple layer substrate, forming a releasable layer on the selected layer between the patterned conductors, forming an additional layer on the selected layer and releasable layer, forming an opening through the additional layer to form a recess in the multiple layer substrate, removing the releasable layer, and attaching a component to substrate within the recess.
[0004] A further method includes patterning conductors on a selected layer of an organic multiple layer substrate, forming a releasable layer on the selected layer between the patterned conductors, forming an additional layer on the selected layer and releasable layer, forming an opening through the additional layer to form a recess in the multiple layer substrate, removing the releasable layer, and attaching the discrete component to the selected layer such that the component is recessed in the organic multiple layer substrate.
Brief Description of the Drawings
[0005] FIG. I is a cross section schematic view of an organic substrate having multiple layers, according to an example embodiment.
[90061 FIGs. 2A, 2B, 2C, 2D, and 2E are cross section schematic views of an organic substrate during build-up and component mounting, according to an
example embodiment.
[00071 FIG. 3 is a cross section schematic view of an organic substrate having components recessed at multiple levels, according to an example embodiment.
Detailed Description
[000$] The following description and the drawings sufficiently illListrate specific embodiments to enable those skilled in the art to practice them. Other embodiments may incorporate structural, logical, electrical, process, and other changes. Portions and features of some embodiments may be included in, or substituted for, those of other embodiments. Embodiments set forth in the claims encompass all available equivalents of those claims.
[0009] FIG. 1 is a cross section schematic view of a portion of an organic substrate 100 having multiple layers. The view may not include an entire substrate, but illustrates a specific segment or section that is relevant for the discussion. A full substrate may have many more features than depicted in FIG. 1, such as via plated through hole (PTH), die, etc. In one embodiment, the substrate 100 is formed with a bottom layer 110, second layer 115, third layer 120, and fourth layer 125, which is the last layer formed during a growing of the organic substrate 100. Bottom layer may be used to mount a central processing unit or other processing element. A discrete component 130 is mounted on the third layer 120 in one embodiment, below the last layer. in further embodiments, the component may be mounted directly on even lower layers, closer to the bottom layer, or the bottom layer itself.
A protective or passivation layer 135 maybe added following attachment of the discrete component I 30.
119010] The discrete component 130 maybe mounted on a layer by the use of a standard sLirface mount process corresponding to each electrical connection to he made between the component and metal lands on the corresponding layer of the substrate. In one embodiment, the surface-mount process utilizes a solder paste (solder and flux mix) that is dispensed onto lands. The discrete component 130 is placed on top of that paste and reflowed (melted) into place. In various embodiments, the discrete component may be a capacitor, resistor, inductor, or other component. Such discrete components may not be easily reduced in height. By recessing the discrete component in the substrate 100, lower Z-height profiles of resulting packages that include the substrate 100 may be obtained without expending resources in attempting to reduce the height of the components themselves. Recessing the components may also provide for reduced parasitic effects, including reduced parasitic capacitance and parasitic resistance.
[0011] Process steps to form substrate 200 having a recessed discrete component are illustrated in schematic cross section in FiGs. 2A, 2B, 2C, 2D, and 2E. in FIG. 2A, a core layer 210 is illustrated. In one embodiment, core layer 210 forms a core of a substrate and is formed of glass reinforced resin. The entire substrate, in one embodiment, may be formed symmetrically, with multiple layers added to both sides of the core layer 210 in a semi additive process. The core layer 210, in one embodiment, is patterned on both sides with conductors 215, 220, as indicated. Conductors may also be formed between layers as illustrated. Copper is used as the conductor in one embodiment. Conductor 215 is formed on an attachment side of the substrate 200, and corresponds to connections to be made to the component when added, along with other patterning.
[0012] In FIG. 2B, a releasable film 225 has been added to the component attachment side of the substrate 200. In one embodiment, the releasable film 225 may be applied by a squeeze process, resulting in a layer that is approximately the same thickness as the conductor 215. Various releasable films may be used in different embodiments, such as common photo resists or dry films that may be stripped off at an appropriate time. The releasable film 225 is formed on top of the layer on which the component will he mounted.
[9013] FTG. 2C illustrates a build-up of additional symmetric layers 240, 245, as indicated, until a SR layer and sLirface finish are symmetrically applied. In one embodiment, the substrate is built up with organic materials, such as plastics and polymers, as well as metallization layers for certain conductive paths.
[9014] FIG. 2D illustrates removal of build-up layers on the component attachment side of substrate 200, where the component is to be embedded. An opening 260 is formed down to the conductor 215 level, and the releasable film 225 is also removed. The build-up layers, in one embodiment, are removed via laser scribing or other available methods. The releasable film 225 may be a resist and may be removed via common etching processes. In one embodiment, a desmear may he performed to dean out remnants from the releasable film 225. Tn one embodiment, the releasable film s formed on the layer on which the component is to be mounted. This layer is shown as a single layer above the core layer 210 in one embodiment, but may be any layer below an outside layer to provide for some amount of recessing of the component from a top layer of the substrate 200 when the component is mounted.
[0015] FIG. 2E illustrates a component 265 positioned in the opening 260.
Prior to positioning the component 265, an organic surface protectant (OSP) surface finish for component pads may be performed, and solder paste dispensed via a nozzle or other means at selected points of attachment. Component 265 is then attached, and the solder paste reflowed to secure the component 265 to layer 240 of substrate 200.
[0016] In one embodiment, the component is recessed at or below the top surface of the substrate 200. In further embodiments, the component may be recessed such that a top of the component is still above the substrate top surface, but lower than it would be had it been attached to the substrate top surface.
[0017] FIG. 3 is a cross section schematic view of an organic substrate 300 having components recessed at multiple levels, according to an example embodiment. Conductor patterning on and between levels is minimized in FIG. 3 to simplify the drawing. An organic core 303 has multip'e symmetric organic ayers 305, 310, 315, 320, 325, and 330 formed about it. Multiple discrete components are bonded to different levels on one or more sides of the core 303. On a top side of the substrate 300, a component 335 is shown mounted to layer 3 IS via conductors 340.
A component 345 is shown mounted to layer 305 via conductors 350. Only two conductors are shown for simplicity. On a bottom side of the substrate 300, a component 355 is shown mounted to layer 320 via conductors 360. A processor 370 is also shown mounted to the bottom side of the substrate 300 on layer 330.
Contacts are omitted for simplicity, but the processor may be mounted to multiple conductors via a ball grid array, surface mount process, or any type of solder connections.
Examples
1. A method comprising: patterning conductors on a selected layer of an organic multiple layer substrate; forming a releasable layer on the selected layer between the patterned conductors; forming an additional layer on the selected layer and releasable layer; forming an opening through the additional layer to form a recess in the multiple layer substrate; removing the releasable layer; and attaching a component to substrate within the recess.
2. The method of example 1, wherein the substrate comprises a polymer core with multiple symmetric layers formed on a top and a bottom of the core.
3. The method of example 2, wherein forming an additional layer comprises forming multiple additional layers; and wherein the forming an opening comprises forming a recess through multiple layers to the selected layer.
4. The method of any of examples 1-3, wherein the component is a capacitor.
5. The method of any of examples 1-4, wherein the component is a resistor.
6. The method of any of examples 1-5, wherein the component is an inductor.
7. The method of any of examples 1-6, wherein the opening is formed via laser scribing.
8. The method of any of examples 1-7, wherein the releasable layer is formed via a squeeze process.
9. The method of any of examples 1-8, wherein attaching a compollent to the substrate withill the recess is performed by: dispensing solder paste through a nozzle onto the patterned conductors on the selected layer; placing the component on the solder paste: and reflowing the solder paste to solder the component to the patterned conductors.
10. A method comprising: patterning conductors on a seecied layer of an organic multiple layer substrate; forming a releasable layer on the selected layer between the patterned conductors; forming an additiollal layer on the selected layer mid releasable layer; forming an opening through the additional layer to form a recess in the multiple layer substrate; removing the releasable layer; surface mounting a discrete component to the selected layer such that the component is recessed in the organic multiple layer sithstrate.
11. The method of example 10, wherein the substrate comprises a glass reinforced resin core with multiple symmetric layers formed on a top and a bottom of the core.
12. The method of example II, wherein forming an additional layer comprises forming multiple additional organic layers; and wherein the forming a opening comprises formifig a recess through multiple layers to the selected layer.
13. The method of any of examples 10-12, wherein the component is a discrete capacitor.
14. The method of any of examples 10-13, wherein tile component is a discrete resistor.
15. The method of any of examples 10-14, wherein the component is an discrete niductor.
16. The method of any of examples 10-15, wherein the releasable layer is formed via a squeeze process.
17. A device comprising: an organic multiple layer substrate; patterned conductors disposed on a recessed layer of the organic multiple layer substrate; and a discrete component coupled to the recessed layer such that the component is recessed from a top layer of the organic multiple layer substrate.
18. The device of example 17, wherein multiple layers of the organic multiple layer substrate are symmetrically disposed ahoLit an organic core.
19. The device of any of examples 17-18, wherein the organic multiple layer substrate comprises a polymer core with multiple symmetric layers formed on a top and a bottom of the core.
20. The device of example 19, wherein the component is recessed multiple layers.
21. The device of any of examples 19-20, wherein the component is a capacitor.
22. The device of any of examples 19-21, wherein the component is a resistor.
23. The device of any of examples 19-22, wherein the component is an inductor.
[90181 Although a few embodiments have been described in detail above, other modifications are possible. For example, the logic flows depicted in the figures do not require the particular order shown, or sequential order, to achieve desirable results. Other steps may be provided, or steps may be eliminated, from the described flows, and other components may be added to, or removed from, the described systems. Other embodiments may be within the scope of the following claims, such as packages with pin grid array, land grid array, die connected to substrate through wire bond, etc. [9019] The Abstract is provided to comply with 37 C.F.R. Section 1.72(h) requiring an abstract that will allow the reader to ascertain the nature and gist of the technical disclosure. It is submitted with the understanding that it will not he used to limit or interpret the scope or meaning of the claims. The following claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment.
S
Claims (25)
- CLAIMS-A method comprising: patterning conductors on a s&ecied layer of an organic multiple layer substrate; forming a releasable layer on the selected layer between the patterned conductors; forming an additional layer on the selected layer and releasable layer; forming an opening through the additional layer to form a recess in the multiple layer substrate: removing the releasable layer; and attaching a component to substrate within the recess.
- 2. The method of claim I, wherein the substrate comprises a polymer core with multiple symmetric layers formed on a top and a bottom of the core.
- 3. The method of claim 2, wherein forming an additional layer comprises forming multiple additional layers; and wherein the forming an opening comprises forming a recess through multiple layers to the selected layer.
- 4. The method of claim 1, wherein the component is a capacitor.
- 5. The method of claim 1, wherein the component is a resistor.
- 6. The method of claim 1, wherein the component is an inductor.
- 7. The method of claim 1, wherein the opening is formed via laser scribing.
- 8. The method of claim 1, wherein the releasable layer is formed via a squeeze process.
- 9. The method of claim 1, wherein attaching a component to the substrate within the recess is performed by: dispensing solder paste through a nozzle onto the patterned condLictors on the selected layer; placing the component on the solder paste: and reflowing the solder paste to solder the component to the patterned conductors.
- 10. A method comprising: patterning conductors on a selected layer of an organic multiple layer substrate; forming a releasable layer on the selected layer between the patterned conductors; forming an additional layer on the selected layer and releasable layer; forming an opening through the additional layer to form a recess in the multiple layer sLibstrate: removing the releasable layer; surface mounting a discrete component to the selected layer such that the component is recessed in the organic multiple layer substrate.
- 11. The method of claim 10, wherein the substrate comprises a glass reinforced resin core with multiple symmetric layers formed on a top and a bottom of the core.
- 12. The method of claim 11, wherein forming an additional layer comprises forming multiple additional organic layers; and wherein the forming an opening comprises forming a recess through multiple layers to the selected layer.
- 13. The method of claim 10, wherein the component is a discrete capacitor.
- 14. The method of claim 10, wherein the component is a discrete resistor.
- 15. The method of claim 10, wherein the component is an discrete inductor.
- 16. The method of claim 10, wherein the r&easahle layer is formed via a squeeze process.
- 17. A device comprising: an organic multiple layer substrate; patterned conductors disposed on a recessed layer of the organic multiple layer substrate; and a discrete component coupled to the recessed layer such that the component is recessed from a top layer of the organic multiple layer substrate.
- 18. The device of claim 17, wherein mulliple ayers of the organic muhiple layer substrate are symmetrically disposed about an organic core.
- 19. The device of claim 17, wherein the orgallic multiple layer substrate comprises a polymer core with multiple symmetric layers formed on a top and a bottom of the core.
- 20. The device of claim 19, wherein the component is recessed multiple layers.
- 21. The device of claim 19, wherein the component is a capacitor.
- 22. The device of claim 19, wherein the component is a resistor.
- 23. The device of claim 19, wherein the component is an inductor.
- 24. A method as hereinbefore described and with reference to, or as illustrated in any one of Figures 1 to 3 of the accompanying drawings.I I
- 25. A device as hereinbefore described and with reference to, or as illustrated in any of the Figures I to 3 of tile accompanying drawings.
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US13/711,092 US20140158414A1 (en) | 2012-12-11 | 2012-12-11 | Recessed discrete component mounting on organic substrate |
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GB201321803D0 GB201321803D0 (en) | 2014-01-22 |
GB2510956A true GB2510956A (en) | 2014-08-20 |
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GB1321803.7A Expired - Fee Related GB2510956B (en) | 2012-12-11 | 2013-12-10 | Recessed discrete component mounting on organic substrate |
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US (1) | US20140158414A1 (en) |
JP (1) | JP5779834B2 (en) |
KR (3) | KR20140075619A (en) |
CN (1) | CN103871913B (en) |
GB (1) | GB2510956B (en) |
SG (1) | SG2013089552A (en) |
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CN103270819B (en) * | 2010-10-20 | 2016-12-07 | Lg伊诺特有限公司 | Printed circuit board and manufacturing methods |
WO2016204209A1 (en) * | 2015-06-19 | 2016-12-22 | 株式会社村田製作所 | Laminated wiring board and probe card provided with same |
CN105916290A (en) * | 2016-06-28 | 2016-08-31 | 广东欧珀移动通信有限公司 | Electronic product |
FR3069127B1 (en) * | 2017-07-13 | 2019-07-26 | Safran Electronics & Defense | ELECTRONIC CARD COMPRISING BRASED CMS ON BRAZING BEACHES ENTERREES |
CN111869334B (en) | 2018-03-12 | 2024-04-30 | 朱马技术有限公司 | Method for manufacturing printed circuit board using conductor element mold |
FR3093271B1 (en) | 2019-02-25 | 2021-11-05 | Safran Electronics & Defense | Electronic board comprising components in cavities and shared soldering areas |
FR3093270B1 (en) | 2019-02-25 | 2021-11-05 | Safran Electronics & Defense | Superposition of electronic components with insertion into cavities |
FR3114215B1 (en) | 2020-09-15 | 2023-05-26 | Safran Electronics & Defense | Electronic board comprising components buried in cavities |
FR3114214B1 (en) | 2020-09-15 | 2023-03-24 | Safran Electronics & Defense | Electronic board comprising components buried in cavities |
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Also Published As
Publication number | Publication date |
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CN103871913A (en) | 2014-06-18 |
TW201442206A (en) | 2014-11-01 |
KR20150113943A (en) | 2015-10-08 |
GB201321803D0 (en) | 2014-01-22 |
JP5779834B2 (en) | 2015-09-16 |
TWI562332B (en) | 2016-12-11 |
CN103871913B (en) | 2017-09-12 |
JP2014116603A (en) | 2014-06-26 |
KR20140075619A (en) | 2014-06-19 |
KR101594004B1 (en) | 2016-02-16 |
KR20150073897A (en) | 2015-07-01 |
GB2510956B (en) | 2016-03-09 |
SG2013089552A (en) | 2014-07-30 |
US20140158414A1 (en) | 2014-06-12 |
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Effective date: 20211210 |