GB2489397A

GB2489397A - A method of cleaving thin semiconductor substrates using a surface trench and side etching

Info

Publication number: GB2489397A
Application number: GB201103720A
Authority: GB
Inventors: Owen J Guy; Yufei Liu
Original assignee: Swansea University
Current assignee: Swansea University
Priority date: 2011-03-04
Filing date: 2011-03-04
Publication date: 2012-10-03
Anticipated expiration: 2031-03-04
Also published as: GB2489397A8; GB2489397B; GB201103720D0

Abstract

In a method of making a semiconductor wafer, the method comprises forming a trench or groove (26, fig. 7) in a single crystal wafer substrate (10); anisotropically etching in the trench (26) to form an elongate notch 28, 30 and using the notch 28, 30 as an initiation site to cleave the substrate '10 along a crystal plane to separate a slim wafer 12. The anisotropic etch can be potassium hydroxide (KOH) or tetramethylammonium hydroxide (TMAH). The trench can be formed by either saw or laser cutting. The plane of cleavage of the wafer runs parallel to the substrate surface, i.e. the surface which received the trench. This method produces thin wafers whose thicknesses can be less than 60 micron.

Description

A Semiconductor Wafer and a Method of Making a Semiconductor Wafer The invention relates to a semiconductor wafer and a method of making a semiconductor wafer.

Semiconductor wafers are used for integrated circuits, photovoltaic cells, LEDs, MEMs, and other applications. Semiconductor wafers are fonned of very pure, substantially defect free single crystal semiconductor material, commonly silicon. It is known to produce a large silicon ingot which is then cut into wafers using a saw. A common wafer thickness is 300 sm, but reduced thicknesses are desirable for efficiency. It is known to grind a wafer to reduce its thickness, and in that way a thickness down to 55 pm can be achieved, but there is a great deal of waste from this process both from the ground away material and from production losses due to the wafer breaking or cracking as a result of the grinding process. There is a limit to the size of wafer which can be ground accurately.

According to one aspect of the invention there is provided a method of making a semiconductor wafer, the method comprising splitting a wafer substrate along a crystal plane.

Compared with existing technology, the method of the invention is more cost effective, has a greater manufacturing efficiency, and is relatively simple.

. .: The method can be used for any suitable single crystal semiconductor material * :°: including silicon, germanium, silicon germanium, gallium arsenide, gallium nitride, gallium phosphide, aluminium gallium arsenide, gallium nitride and indi gallium arsernde.

The wafer formed by the method may be less than 160 pin thick, preferably : less than 100 im thick, and in one embodiment is less than 60 pm thick. The thickness * : of the wafer can be varied and the thickness is controlled by the conditions under which is split/cleaved. It is possible to have stand alone wafer which are less than 50 jnn. However it is also possible to have thinner wafer, for example those that are a thin as 10 jim and typically these thin wafer are supported by a carrier substrate to preserve the intactness of the wafer. Furthermore, several wafers may be supported on a substrate. Typical substrates for the wafers are rubber, glass or other crystalline materials. By the method according to the invention, such wafers may be made with minimal waste. The risk of breakage or cracking is much less than for the known grinding technique and there is no inherent loss of material as there is in grinding.

The method preferably includes creating a notch and splitting the substrate using the notch as an initiation site for the split. The notch may be formed in any suitable way, and may be formed by a chemical or physical process, but preferably is formed by anisotropic etching of the substrate. Suitable etches for silicon include potassium hydroxide (KOH) and tetramethylammonium hydroxide (TMAH). The process is in effect a multi stage process, typically at least a two stage process where initially a notch or trench is made in the surface of the wafer and then there is a splitting of the wafer where the notch is.

In one embodiment, the method includes splitting the substrate again along a second crystal plane which may be parallel to the first. In this way, two or more wafers may be created from a single substrate in an efficient manner.

Preferably, a trench is formed in the substrate and the notch is formed in a wall of the trench. The trench may be formed by a physical method such as saw cutting, or laser cutting or by a chemical method, for example an etching process, such as reactive ion etching (RIB) or deep reactive ion etching (DRIB). The trench may also be formed by a combined physical/chemical process. The trench may form a circuit which surrounds the region to be split. However it is also possible that the trench may for a perimeter for an area about the trench. For example if a wafer substrate is formed * that has uneven edges, the trench may be formed in proximity to the edges so that the *0*5*S * uneven edges can be removed. In effect the trench acts as a way of trimming the wafer L: :* so that it has a desired overall shape or dimension. The wafer may be split using a physical method such as mechanical splitting, splitting by thermal effect, ultrasonic splitting or other suitable methods.

A layer may be added to protect the integrity of the wafer during splitting.

* This layer could be any type of flexible layer such as a rubber of a polymer layer such as polyimide or a SU8 photoresist and it is envisaged that the layer could even be a powder layer. Furthennore layers formed of a laminate of the materials discussed could be used.

According to another aspect of the invention there is provided a single crystal semiconductor wafer including at least one major side formed by cleaving along a crystal plane.

According to a further aspect of the invention there is provided an intermediate product comprising a single crystal semiconductor wafer substrate, the substrate including an elongate notch, the apex of the notch forming a line which lies in a plane which is parallel to a crystal plane of the substrate and substantially parallel to a surface of the substrate.

The elongate notch may follow any desired line and in one embodiment forms a complete circuit around a region of the substrate.

The notch may be in the side of a trench in the substrate.

Embodiments of the invention will now be described by way of example and with reference to the accompanying drawings, in which: Figs. 1 to 9 are side elevations in cross section the substiEate in the stages of the process in the first embodiment; Fig 10 is a plan view of the substrate; and, Figs. 11 to 15 are side elevations in cross section the substrate in the stages of the process in the second embodiment. * *I

* * Fig. 1 shows a single crystal silicon wafer about 200.tm. thick which in this ****** * embodiment forms the substrate 10 starting material to be split to form the ultra thin 1: waler 12 or foil of this embodiment of the invention.

The substrate 10 as shown in Fig 10 is a disc with a flat 14 cut along a chord to * show its crystal orientation. The major surfaces 16 are aligned with the [100] plane.

In other embodiments, the major surfaces may be aligned with the [110) plane.

*****.

* The substrate 10 is first cleaned. In this embodiment, the substrate 10 is placed in a solution of H2S04:F120 2= 3:1, at 90°C for 5-9 minutes followed by NH4OH: H202: H20 1:2:5, <90°C for 10 minutes followed by HC1: H202: H20 = 1:2:7, <90°C for 10 minutes.

An Si02 protection layer 18 is then grown on the substrate 10 by wet oxidation. Other types of protection layers may be used such as Si Nitride. The substrate 10 is placed in a furnace in a steam atmosphere. The furnace temperature is increased to 700°C with N2 flow of 1 11mm and kept stable for 5 minutes, then the temperature is increased to 1140°C with N2 flow of 1 1/mm, then oxygen is introduced with 02 flow of 1 1/mm. 6.5 hours growth results in a thickness of Si02 of 2 micrometres on the substrate 10, as shown in Fig 2.

A photoresist 20 is then applied to the upper surface of the substrate 10 by a spin coating process. The photoresist material AZ9260 is applied at a spin rate of 3000 rpm for 30 seconds followed by a soft bake at 85 °C for 5 minutes. The coated substrate 10 is shown in Fig 3.

Using the same technique and material a photoresist layer 22 is applied to the °. : rear surface of the substrate 10. The upper photoresist layer 20 is then patterned by * the photolithography process to make the required pattern for the next step. The aim * .s S * is to create a trench in the upper surface of the substrate 10 to form a complete circuit 1: * 20 around the periphery thereof The substrate 10 is subjected to UV exposure at 2SmJ/cm2 for 20 seconds foHowed by development using AZ 726 M1F developer for Sminutes and 30 seconds. The resulting construction is shown in Fig 4, which :.: * illustrates the gap or window 24 in the photoresist layer 20.

* The exposed Si02 protection layer 18 at the gap 24 is then etched away using NH4F:HF = 7:1 at 38±2 °C. The Si02 etching rate is about 200-220 nmlmin. The resulting construction is shown in Fig 5.

Deep reactive ion etching (DRIE) is then carried out on the exposed silicon substrate 10 in the gap 24 to form the required trench 26 as shown in Fig 6. The DRIE silicon etching is carried out with the standard Bosch process using SF6 and 02 gases.

It is important that the orientation of the wafer is properly aligned during the DRIE chemical etching process.

The photoresist layers 20, 22 are then removed with acetone, resulting in the construction shown in Fig 7.

An isotropic chemical etch is then applied in the trench 26, in this case, 20% KOR at 70°C. This results in an etching rate of 50 nñcrometres/minute. The etch will remove material preferentially in relation to the crystal structure of the single crystal substrate 10, in this case horizontally, resulting in a tapering notch 28, 30 to each side of the trench 26 in the direction of the plane of the substrate 10. In terms of axes, if the trench 26 is sunk and defined along the Z axis, the notches 28,30 extend in the XY plane, as shown in Fig 8. The substrate 10 at this point forms the aforesaid "intermediate product". It is noted that the apex 34 of each notch 28, 30 forms a line which lies in a plane which is parallel to a crystal plane of the substrate 10 and substantially parallel to each major surface 16 of the substrate 10.

It is to be understood that the nature of the wafer can be controlled by the parameters such as temperature, timing and rates that are used in the process to optimise the characteristics of the wafer, such as thickness.

The sharp notch 28 to the inside of the trench 26 is used as an initiation site for splitting the substrate 10 by cleavage along a crystal plane. In this embodiment, the * * splitting is by thermal stress although mechanical stress can be used. A metal in the form of an ink, in this case silver ink, is printed onto the exposed surface of the upper **s * silicon dioxide layer 18. The workpiece comprising the substrate 10 with silver layer thereon is placed in an oven at high temperature. The differences in rate of take up of heat due to differences in thermal conductivity and the differences in coefficient of * thermal expansion between the silver and the substrate 10 will cause stress as the workpiece heats up. The workpiece is then removed from the oven and allowed to * cool rapidly. This causes further stress resulting in splitting of the workpiece at the initiation site which has been created, namely the notch 28, so that a wafer 12 is cleaved from the substrate 10 by a split 32 along the crystal plane parallel to the top surface 16 of the wafer substrate 10. As an alternative to thermal expansion, thermal contraction could be used cause stress that splits the workpiece. It is the difference between thermal mismatch between expansion and contraction that is used to cause the splitting.

By control of the depth of the trench 26, the thickness of the wafer 12 can be controlled and in this embodiment is typically 55 microns. The wafer thickness following splitting is typically half the depth of the trench in the surface of the wafer.

It is thus seen that the invention enables a very thin wafer to be made in a controlled fashion with low risk of breakage and at low energy cost and with low waste.

By repeating the process, one or more further thin wafers 12 can be split from the same substrate 10.

The second embodiment is shown in Figs ii to 15. The second embodiment is similar to the first and the same reference numerals will be used for equivalent features.

In the second embodiment, the protection layer 40 which is created is silicon nitride rather than silicon dioxide and is deposited by chemical vapour deposition (CVD). The conditions are as follows 30W, 900mTorr, SiH4 40 sccm (standard cubic centimetres per minute), NH3 55 sccm, N2 1960 sccm, substrate temperature 300 °C.

30 minutes growth resulted in a thickness of SiN of 0.5 micrometres. Fig 11 shows . : the substrate 10 and Fig 12 shows the substrate with the silicon nitride protection * layers 40 on the top and underneath surfaces.

* ***.* * Instead of using photolithography as in the first embodiment, in the second embodiment the trench 26 is formed by laser cutting, mechanical cutting, use of a dicing saw or sonic cutting resulting in the construction shown in Fig 13.

* In the second embodiment, the anisotropic etch is TMAH :.: (tetramethylammonium hydroxide). The trench 26 is filled, and in this way the height of the apices of the V notches 28, 30 will be half the height of the trench 26, as shown in Fig 14.

The wafer 12 is split from the substrate 10 by ultrasonic cleavage, as shown in Fig 15.

The skilled person will appreciate that the protection layer can be provided by wet or dry thermal growth or other known ways of forming a layer, in particular of Si02. In a variant on the first or second embodiment, the protection layer can be a layer of metal or metals. Other deposition methods such as electron beam evaporation, sputtering and PVD are also envisaged.

The step of creating a protection layer on the underside of the substrate may be S omitted in the first embodiment if a dry etching method is used for etching of the protection layer 18.

In another variant on the first embodiment, the SiO2 protection layer 18 may be etched using any suitable buffered oxide etch (BOB).

In a variant on the second embodiment, the trench 26 could be cut by RIB or dicing saw cutting.

The wafer 12 could be split from the substrate in other ways such as by mechanical splitting, thermomechanical splitting, megasonic or ultrasonic splitting, or electrothermal means.

Although individual embodiments are discussed, it is to be understood that the invention can cover combinations of the embodiments described. * �S * *S *

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S OS * 0 0 S*S 0 * 00 * 0 0*0 0

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Claims

Claims 1. A method of making a semiconductor wafer, the method comprising splitting a single crystal wafer substrate along a crystal plane.
2. A method as claimed in claim 1, wherein the wafer made by the method is less than 160 p.m thick.
3. A method as claimed in claim 1, wherein the wafer made by the method is less than 100 p.m thick.
4. A method as claimed in claim 1, wherein the wafer made by the method is less than 60 p.m thick.
5. A method as claimed in any preceding claim, wherein the method includes creating a notch and splitting the substrate using the notch as an initiation site for the split.
6. A method as claimed in claim 5, wherein the notch is created by anisotropic etching of the substrate. * * S * *S

*
7. A method as claimed in claim 6, wherein the anisotropic etch is potassium * ,* hydroxide (KOH) or tetramethylammonium hydroxide (TMAH).

:.: * 25
8. A method as claimed in claim 5, 6 or 7, wherein a trench is fonned in the : substrate and the notch is formed in a wall of the trench.

* 05.00 * 0
9. A method as claimed in claim 8, wherein the trench is formed by cutting, such as by saw cutting, or laser cutting.
10. A method as claimed in claim 8, wherein the trench is formed by a chemical method, such as reactive ion etching (RIB) or deep reactive ion etching (DRIB).
11. A method as claimed in claim 8, 9 or 10, wherein the trench forms a circuit which surrounds the region to be split.
12. A method as claimed in any preceding claim wherein the wafer is split using a physical method such as mechanical splitting, splitting by thermal effect, or ultrasonic splitting.
13. A method as claimed in any preceding claim, wherein the method includes at least one step of splitting the substrate again along a second crystal plane which is parallel to the first to create a plurality of wafers from one substrate.
14. A method of making a semiconductor wafer, the method being substantially as described herein with reference to Figs 1 to 10 or 11 to 15 of the accompanying drawings.
15. A wafer made by the method of any preceding claim.
16. A single crystal semiconductor wafer including at least one major side formed by cleaving along a crystal plane.
17. An intermediate product comprising a single crystal semiconductor wafer S.. S S. * substrate, the substrate including an elongate notch, the apex of the notch forming a 1: line which lies in a plane which is parallel to a crystal plane of the substrate and substantially parallel to a surface of the substrate.
18. An intermediate product as claimed in claim 17, wherein the elongate notch * forms a complete circuit around a region of the substrate.
19. An intermediate product as claimed in claim 17 or claim 18, wherein the notch is in the side of a trench in the substrate.
20. A single crystal semiconductor wafer substantially as described herein with reference to Figs 1 to 10 or 11 to 15 of the accompanying drawings.
21. An intermediate product substantially as described herein with reference to Figs 1 to 10 or 11 to 15 of the accompanying drawings. * * S * *S* I. S*. * SV S. S S.. S * *S * a SSS *S* .* *.* * S