GB2454810B - Cache memory system - Google Patents

Cache memory system

Info

Publication number
GB2454810B
GB2454810B GB0821080.9A GB0821080A GB2454810B GB 2454810 B GB2454810 B GB 2454810B GB 0821080 A GB0821080 A GB 0821080A GB 2454810 B GB2454810 B GB 2454810B
Authority
GB
United Kingdom
Prior art keywords
cache memory
memory system
cache
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
GB0821080.9A
Other versions
GB2454810B8 (en
GB0821080D0 (en
GB2454810A (en
GB2454810A8 (en
Inventor
Andrew Michael Jones
Stuart Ryan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics Ltd Great Britain
Original Assignee
STMicroelectronics Ltd Great Britain
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from GBGB0722707.7A external-priority patent/GB0722707D0/en
Application filed by STMicroelectronics Ltd Great Britain filed Critical STMicroelectronics Ltd Great Britain
Publication of GB0821080D0 publication Critical patent/GB0821080D0/en
Publication of GB2454810A publication Critical patent/GB2454810A/en
Application granted granted Critical
Publication of GB2454810B publication Critical patent/GB2454810B/en
Publication of GB2454810B8 publication Critical patent/GB2454810B8/en
Publication of GB2454810A8 publication Critical patent/GB2454810A8/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/126—Replacement control using replacement algorithms with special data handling, e.g. priority of data or instructions, handling errors or pinning
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0888—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using selective caching, e.g. bypass

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
GB0821080A 2007-11-19 2008-11-18 Cache memory system Expired - Fee Related GB2454810B8 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GBGB0722707.7A GB0722707D0 (en) 2007-11-19 2007-11-19 Cache memory
US12/284,331 US9311246B2 (en) 2007-11-19 2008-09-19 Cache memory system

Publications (5)

Publication Number Publication Date
GB0821080D0 GB0821080D0 (en) 2008-12-24
GB2454810A GB2454810A (en) 2009-05-20
GB2454810B true GB2454810B (en) 2012-11-14
GB2454810B8 GB2454810B8 (en) 2012-11-21
GB2454810A8 GB2454810A8 (en) 2012-11-21

Family

ID=40194829

Family Applications (1)

Application Number Title Priority Date Filing Date
GB0821080A Expired - Fee Related GB2454810B8 (en) 2007-11-19 2008-11-18 Cache memory system

Country Status (1)

Country Link
GB (1) GB2454810B8 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB0722707D0 (en) 2007-11-19 2007-12-27 St Microelectronics Res & Dev Cache memory
US9311251B2 (en) 2012-08-27 2016-04-12 Apple Inc. System cache with sticky allocation
US20140089600A1 (en) * 2012-09-27 2014-03-27 Apple Inc. System cache with data pending state

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5713003A (en) * 1994-12-13 1998-01-27 Microsoft Corporation Method and system for caching data
US5944815A (en) * 1998-01-12 1999-08-31 Advanced Micro Devices, Inc. Microprocessor configured to execute a prefetch instruction including an access count field defining an expected number of access
US20020116584A1 (en) * 2000-12-20 2002-08-22 Intel Corporation Runahead allocation protection (rap)
US20060112229A1 (en) * 2004-11-19 2006-05-25 Moat Kent D Queuing cache for vectors with elements in predictable order
US20070067577A1 (en) * 2002-06-18 2007-03-22 Ip-First, Llc Microprocessor, apparatus and method for selective prefetch retire

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5713003A (en) * 1994-12-13 1998-01-27 Microsoft Corporation Method and system for caching data
US5944815A (en) * 1998-01-12 1999-08-31 Advanced Micro Devices, Inc. Microprocessor configured to execute a prefetch instruction including an access count field defining an expected number of access
US20020116584A1 (en) * 2000-12-20 2002-08-22 Intel Corporation Runahead allocation protection (rap)
US20070067577A1 (en) * 2002-06-18 2007-03-22 Ip-First, Llc Microprocessor, apparatus and method for selective prefetch retire
US20060112229A1 (en) * 2004-11-19 2006-05-25 Moat Kent D Queuing cache for vectors with elements in predictable order

Also Published As

Publication number Publication date
GB2454810B8 (en) 2012-11-21
GB0821080D0 (en) 2008-12-24
GB2454810A (en) 2009-05-20
GB2454810A8 (en) 2012-11-21

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Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee

Effective date: 20141118