GB2436164A - Improvements in electrical connections between electronic components and conductive tracks - Google Patents

Improvements in electrical connections between electronic components and conductive tracks Download PDF

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Publication number
GB2436164A
GB2436164A GB0605249A GB0605249A GB2436164A GB 2436164 A GB2436164 A GB 2436164A GB 0605249 A GB0605249 A GB 0605249A GB 0605249 A GB0605249 A GB 0605249A GB 2436164 A GB2436164 A GB 2436164A
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GB
United Kingdom
Prior art keywords
substrate
component
conductive
channel
track
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GB0605249A
Other versions
GB0605249D0 (en
Inventor
Keith Fawdington
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
UVASOL Ltd
Original Assignee
UVASOL Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by UVASOL Ltd filed Critical UVASOL Ltd
Priority to GB0605249A priority Critical patent/GB2436164A/en
Publication of GB0605249D0 publication Critical patent/GB0605249D0/en
Publication of GB2436164A publication Critical patent/GB2436164A/en
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49855—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers for flat-cards, e.g. credit cards
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/0772—Physical layout of the record carrier
    • G06K19/07728—Physical layout of the record carrier the record carrier comprising means for protection against impact or bending, e.g. protective shells or stress-absorbing layers around the integrated circuit
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07743—External electrical contacts
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07749—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07749—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
    • G06K19/0775—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card arrangements for connecting the integrated circuit to the antenna
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Theoretical Computer Science (AREA)
  • Ceramic Engineering (AREA)
  • Details Of Aerials (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)

Abstract

Radio Frequency Identification Devices (RFIDs) sometimes fail because of a break in the connection between a microchip mounted on a substrate sheet and a conductive track printed on the substrate forming an antenna for the device, owing to twisting or bending of the substrate. The problem is solved by depositing conductive material forming the conductive track over a surface of the component 2, thereby making electrical contact with it. The conductive material may serve as an adhesive which attaches the component to the substrate. The component may be positioned within a recess in the substrate, with the conductive material deposited into the recess which is, shaped as a channel 1A corresponding to a desired track pattern.

Description

<p>Improvements in Electrical Connections between Electronic Components
and Conductive Tracks This invention relates to an electrical device comprising a substrate carrying an electrical component and a conductive track connected electrically to the component.</p>
<p>The manufacture of circuit boards typically involves the process of forming a pattern of conductive tracks on a substrate, followed by physically attaching electrical components and forming electrical connections between the components and the tracks. The components are attached using any one of a large number of known techniques such as soldering or pressure welding. Whatever technique is used has to be performed with delicacy and a high degree of accuracy because the conductive terminals on the electrical components can be very small. The connections may consequently be weak and prone to fail if subjected to flexural stresses.</p>
<p>This invention arose when considering the design of RFID (radio frequency identification) devices. These devices typically comprise a chip and an antenna which is usually formed from a conductive track formed on a substrate. The inventors observed that, in known constructions of this type, the connections between the RFID chip and its antenna were unable to survive stresses caused when the substrate was subjected to bending or twisting forces.</p>
<p>The invention provides an electrical device comprising a substrate carrying an electrical component and a conductive track connected electrically to the component characterised in that conductive material forming the track is deposited over a surface of the component thereby making electrical contact with it.</p>
<p>The invention may also be defined as a method and hence there is provided a method of making an electrical connection to a component on a substrate characterised in that a conductive material forming a track on the substrate is deposited over a surface of the component.</p>
<p>Because the track is deposited over a surface of the component, its connection to the component can be made at the same time as it is deposited. Also, the material of the track can serve to hold the component securely to itself and to the substrate in a manner similar to an adhesive so that is likely to retain a reliable electrical contact with the track even when the assembled device is subjected to flexing.</p>
<p>The track may be deposited over all or a substantial part of the chip so that it covers an electrical terminal with a significant overlap onto adjacent parts of the chip surface. This allows the manufacturing process to tolerate some degree of inaccuracy in alignment of the track with the component.</p>
<p>In one method in accordance with the invention the component is positioned and temporarily fixed onto the surface of the substrate; and the conductive track material is then deposited onto the substrate and over at least part of the component so as to make electrical contact with a conductive terminal of the component. Deposition of the conductive material may be performed by printing conductive ink (i.e. a liquid that subsequently solidifies) onto the substrate using conventional printing techniques such as flexography or screen printing. Alternatively it could be deposited using other techniques such as vapour deposition. The conductive material may serve as an adhesive so as to attach the component to the substrate. Alternatively, the component may be fixed to the substrate before the conductive material is deposited over it.</p>
<p>Because the conductive material is deposited over a surface of the component, the invention is particularly applicable for use with components formed as an encapsulating body having conductive areas on its surface defining its terminals. By applying the conductive material as a layer covering those terminals and adjacent parts of the surface of the component, reliable electrical connection can be achieved without the need for perfect alignment of the print with the terminals.</p>
<p>The component may be positioned onto a flat substrate or alternatively within a recess formed in the substrate. This recess can be shaped as a channel to, correspond to a desired track pattern, and then filled with the conductive material. The channel may be formed by ablation of the surface of the substrate, possibly by use a laser.</p>
<p>Alternatives would be to form it by etching using a solvent or by moulding during manufacture of the substrate. The conductive material may be printed into the channel or deposited in some other fashion such as by pouring or injecting. These methods could be used to envelop the component in the conductive material so as to physically secure it into to a set position in the channel.</p>
<p>Four ways in which the invention can be performed will now be described with reference to the following drawings in which: Figure 1 schematically represents a cross section of an embodiment of the invention pursuant to claim 1; Figure 2 schematically represents a cross section of an alterative embodiment of the invention; Figure 3 schematically represents a perspective view of a third embodiment of the invention in which the component is located in a channel; and Figure 4 schematically represents a cross section of a fourth embodiment of the invention invention.</p>
<p>Referring to Figure 1, there is shown an insulating substrate 1 made from a flexible polymer, a radio frequency identification (RFID) chip 2 comprising two electrical contacts 3, and two ends of a track 4 which follows a looped path (not shown) along the surface of the substrate 1 and acts as an antenna for the chip 2. The track 4, whose ends are separated by gap 5, is formed from a solidified conductive ink adhered to the top surface of the substrate 1, the sides of the RFID chip 2 and the contacts 3. In this particular construction the ink serves a secondary purpose as an adhesive to hold the component 2 onto the substrate 1. In alternative constructions the component could be prefixed to the substrate using a special purpose adhesive or other means.</p>
<p>The above construction is created by positioning the chip 2 in the required position on top the substrate I. An ink jet printing process is then employed to deposit the ink onto the surface of the substrate along a defined path so as to create an antenna. At the two ends of the antenna 4, the ink is deposited so as to envelop the two sides of the chip 2 carrying the contacts 3 so as to form an electrical connection with the contacts 3 and to secure the chip to the substrate. Care is taken during the printing process to ensure that there a gap exists between the two ends of the antenna 4 so as to prevent short circuiting.</p>
<p>In the arrangement of Fig 1 the thickness of the printed track is shown as being greater than the depth of the chip 2. In an alternative construction the depth of the chip could be larger. In that latter case the conductive ink could cover only the sides of the chip 2, but it is preferred that part of the top surface be also covered to allow for imperfect registration of the printing process and to improve adhesion of the chip to the substrate.</p>
<p>Figure 2 illustrates an alternative construction to Fig 1. The substrate 1 is formed with a hole 6 and the chip 2 is orientated so that one of the contacts 3 is exposed to the hole 6. One end of the conductive ink antenna 4A is printed onto the topside of the substrate so as to completely envelop three sides of the chip 3. The other end of the antenna 4B is formed by printing onto the reverse side of the substrate 1 insuring that ink completely fills the hole 5 creating an electrical connection with the chip.</p>
<p>The two ends of the antenna are connected via another hole in the substrate (not shown) through which ink is deposited so as to fill. Alternatively either of the holes may be plated with a conductive solid such as a copper using any of many possible known through-hole plating techniques.</p>
<p>Although the figures show the ink to be resting on the top surface of the substrate the substrate may be made of a material selected to have a porous character so as to allow the ink to permeate a little under the surface so as to improve the adhesion of the ink and thus the chip to the substrate.</p>
<p>Figure 3 illustrates another possible embodiment of the invention. The substrate I defines a recess in the form of a channel I A formed by laser ablation. The shape of the channel corresponds to the path of the antenna for the RFID chip 2. The chip 2 is positioned into channel 1 A with the contacts 3 orientated so that they face along the length of the channel 1 A. The chip forms a resistance fit in the channel so that it is held in the required position prior to the application of the conductor.</p>
<p>Conductive material may be deposited into the channel 1A by printing. Alternatively the ink may be applied initially over the whole surface of the substrate and then any excess ink, not within the channels, removed. Another possible technique would be to form the surface of the substrate so that the ink will not adhere to it. The solidified ink in the channels forms a conductive track which acts as an antenna.</p>
<p>Preferably the ink fills the channel 1A substantially up to the level of the surface of the substrate 1, though an electrical connection can be formed so long as the ink covers the contacts 3.</p>
<p>Figure 4 shows another embodiment similar to that illustrated in Figure 2 but incorporating a channel 1 A in the substrate. In addition to the channel, the substrate also defines a hole into which the chip 2 is housed. The chip 2 is orientated so that the contacts 3 face a lateral direction to the surface of the substrate 1. Conductive ink is then deposited in the channel IA, forming the antenna and completely covering one face of the chip 2. A track forming the rest of the antenna it then printed onto the reverse side of the substrate, and the two portions connected by a connection through a second hole in the substrate as described with reference to Fig 2. In an alternative embodiment the reverse side of the substrate may also be ablated to as to form a channel which may form the basis of the antenna.</p>
<p>It is believed that it will be particularly simple to manufacture products, using the principles described with reference to the drawings and that the manner in which the components are fixed to the flexible substrates will allow repeated flexing without damaging the integrity of the electrical connections. It is emphasised, however, that the above only describe a few of forms which the invention may embody and that, although described with reference to RDIF tags, the invention may be applied to form electrical connections in relation to any electrical component.</p>

Claims (1)

  1. <p>CLAIMS</p>
    <p>1. An electrical device comprising a substrate carrying an electrical component and a conductive track connected electrically to the component characterised in that conductive material forming the track is deposited over a surface of the component thereby making electrical contact with it.</p>
    <p>2. An electrical device according to Claims 1 or 2 characterised in that the conductive material is printed.</p>
    <p>3. An electrical device according to any preceding Claim characterised in that the component sits in a channel formed in the substrate.</p>
    <p>4. An electrical device according to any preceding Claim characterised in that the material is deposited into the channel.</p>
    <p>5. A method of making an electrical connection to a component on a substrate characterised in that a conductive material is deposited on the substrate to form a conductive track and over a surface of the component to connect the track electrically to the component.</p>
    <p>6. A method according to Claim 5 characterised in that the conductive material is deposited by printing.</p>
    <p>7. A method according to claim 5 or 6 characterised in that the component is placed in a channel formed in the substrate.</p>
    <p>8. A method according to Claim 7 characterised in that the channel is formed using a laser.</p>
    <p>9. A method according to Claim 7 characterised in that the material is deposited into the channel.</p>
GB0605249A 2006-03-16 2006-03-16 Improvements in electrical connections between electronic components and conductive tracks Withdrawn GB2436164A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB0605249A GB2436164A (en) 2006-03-16 2006-03-16 Improvements in electrical connections between electronic components and conductive tracks

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB0605249A GB2436164A (en) 2006-03-16 2006-03-16 Improvements in electrical connections between electronic components and conductive tracks

Publications (2)

Publication Number Publication Date
GB0605249D0 GB0605249D0 (en) 2006-04-26
GB2436164A true GB2436164A (en) 2007-09-19

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GB0605249A Withdrawn GB2436164A (en) 2006-03-16 2006-03-16 Improvements in electrical connections between electronic components and conductive tracks

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010023272A2 (en) 2008-08-29 2010-03-04 Féinics Amatech Nominee Teoranta Inlays for security documents

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1254716A (en) * 1967-12-01 1971-11-24 Gen Electric A method of embedding electronic components in a dielectric layer
GB2224600A (en) * 1988-10-29 1990-05-09 Stc Plc Circuit assembly
EP0506526A1 (en) * 1991-03-26 1992-09-30 Thomson-Csf Hybrid module and its process for manufacture
US6147662A (en) * 1999-09-10 2000-11-14 Moore North America, Inc. Radio frequency identification tags and labels
US6365440B1 (en) * 1998-09-03 2002-04-02 Fraunhofer-Gesellschaft Zur Forderung Der Angewandten Forschung E.V. Method for contacting a circuit chip
US20030226901A1 (en) * 2002-06-11 2003-12-11 Kim Deok-Heung IC card and manufacturing method thereof

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1254716A (en) * 1967-12-01 1971-11-24 Gen Electric A method of embedding electronic components in a dielectric layer
GB2224600A (en) * 1988-10-29 1990-05-09 Stc Plc Circuit assembly
EP0506526A1 (en) * 1991-03-26 1992-09-30 Thomson-Csf Hybrid module and its process for manufacture
US6365440B1 (en) * 1998-09-03 2002-04-02 Fraunhofer-Gesellschaft Zur Forderung Der Angewandten Forschung E.V. Method for contacting a circuit chip
US6147662A (en) * 1999-09-10 2000-11-14 Moore North America, Inc. Radio frequency identification tags and labels
US20030226901A1 (en) * 2002-06-11 2003-12-11 Kim Deok-Heung IC card and manufacturing method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010023272A2 (en) 2008-08-29 2010-03-04 Féinics Amatech Nominee Teoranta Inlays for security documents
EP2332097A2 (en) * 2008-08-29 2011-06-15 Féinics AmaTech Teoranta Inlays for security documents

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