GB2417132B - Method of forming a metal layer over a patterned dielectric by electroless deposition using a catalyst - Google Patents
Method of forming a metal layer over a patterned dielectric by electroless deposition using a catalystInfo
- Publication number
- GB2417132B GB2417132B GB0513698A GB0513698A GB2417132B GB 2417132 B GB2417132 B GB 2417132B GB 0513698 A GB0513698 A GB 0513698A GB 0513698 A GB0513698 A GB 0513698A GB 2417132 B GB2417132 B GB 2417132B
- Authority
- GB
- United Kingdom
- Prior art keywords
- catalyst
- forming
- metal layer
- layer over
- electroless deposition
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000003054 catalyst Substances 0.000 title 1
- 230000008021 deposition Effects 0.000 title 1
- 239000002184 metal Substances 0.000 title 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76846—Layer combinations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76855—After-treatment introducing at least one additional element into the layer
- H01L21/76859—After-treatment introducing at least one additional element into the layer by ion implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76874—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroless plating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1068—Formation and after-treatment of conductors
- H01L2221/1073—Barrier, adhesion or liner layers
- H01L2221/1084—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L2221/1089—Stacks of seed layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10302644A DE10302644B3 (en) | 2003-01-23 | 2003-01-23 | Process for producing a metal layer over a structured dielectric by means of electroless deposition using a catalyst |
US10/602,192 US6951816B2 (en) | 2003-01-23 | 2003-06-24 | Method of forming a metal layer over patterned dielectric by electroless deposition using a catalyst |
PCT/US2003/041185 WO2004068576A2 (en) | 2003-01-23 | 2003-12-22 | Method of forming a catalyst containing layer over a patterned dielectric |
Publications (3)
Publication Number | Publication Date |
---|---|
GB0513698D0 GB0513698D0 (en) | 2005-08-10 |
GB2417132A GB2417132A (en) | 2006-02-15 |
GB2417132B true GB2417132B (en) | 2007-04-04 |
Family
ID=32826166
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB0513698A Expired - Lifetime GB2417132B (en) | 2003-01-23 | 2003-12-22 | Method of forming a metal layer over a patterned dielectric by electroless deposition using a catalyst |
Country Status (5)
Country | Link |
---|---|
JP (1) | JP5214092B2 (en) |
KR (1) | KR101098568B1 (en) |
AU (1) | AU2003299875A1 (en) |
GB (1) | GB2417132B (en) |
WO (1) | WO2004068576A2 (en) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6943106B1 (en) * | 2004-02-20 | 2005-09-13 | Micron Technology, Inc. | Methods of fabricating interconnects for semiconductor components including plating solder-wetting material and solder filling |
JP2006128288A (en) * | 2004-10-27 | 2006-05-18 | Tokyo Electron Ltd | Film forming method, semiconductor device, manufacturing method thereof, program, and recording medium |
CN101578394B (en) | 2007-07-31 | 2011-08-03 | 日矿金属株式会社 | Plated material having metal thin film formed by electroless plating, and method for production thereof |
US8395264B2 (en) | 2009-01-30 | 2013-03-12 | Jx Nippon Mining & Metals Corporation | Substrate comprising alloy film of metal element having barrier function and metal element having catalytic power |
TW202117075A (en) * | 2019-09-25 | 2021-05-01 | 日商東京威力科創股份有限公司 | Substrate liquid treatment method and substrate liquid treatment device |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5969422A (en) * | 1997-05-15 | 1999-10-19 | Advanced Micro Devices, Inc. | Plated copper interconnect structure |
US6316359B1 (en) * | 1998-02-12 | 2001-11-13 | Motorola Inc. | Interconnect structure in a semiconductor device and method of formation |
US20020050459A1 (en) * | 2000-11-02 | 2002-05-02 | Kabushiki Kaisha Toshiba | Electronic device manufacturing method |
WO2002045155A2 (en) * | 2000-11-29 | 2002-06-06 | Intel Corporation | ELECTROLESS METHOD OF SEED LAYER DEPOSITION, REPAIR, AND FABRICATION OF Cu INTERCONNECTS |
US6461675B2 (en) * | 1998-07-10 | 2002-10-08 | Cvc Products, Inc. | Method for forming a copper film on a substrate |
US6479902B1 (en) * | 2000-06-29 | 2002-11-12 | Advanced Micro Devices, Inc. | Semiconductor catalytic layer and atomic layer deposition thereof |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4574095A (en) * | 1984-11-19 | 1986-03-04 | International Business Machines Corporation | Selective deposition of copper |
JPH0762545A (en) * | 1993-08-30 | 1995-03-07 | Mitsubishi Cable Ind Ltd | Wiring board and its production |
US6380083B1 (en) * | 1998-08-28 | 2002-04-30 | Agere Systems Guardian Corp. | Process for semiconductor device fabrication having copper interconnects |
JP4049978B2 (en) * | 1999-09-15 | 2008-02-20 | 三星電子株式会社 | Metal wiring formation method using plating |
JP2001240960A (en) * | 1999-12-21 | 2001-09-04 | Nippon Sheet Glass Co Ltd | Article coated with photocatalytic film, method of manufacturing for the article, and sputtering target used for depositing the film |
KR100338112B1 (en) * | 1999-12-22 | 2002-05-24 | 박종섭 | Method of forming a copper wiring in a semiconductor device |
CN1174118C (en) * | 2000-01-07 | 2004-11-03 | 株式会社日矿材料 | Method for metal plating, pretreating agent, and semiconductor wafer and semiconductor device using same |
JP2001335952A (en) * | 2000-05-31 | 2001-12-07 | Rikogaku Shinkokai | Electroless plating method, wiring device and its production method |
JP2002004081A (en) * | 2000-06-16 | 2002-01-09 | Learonal Japan Inc | Electroplating method to silicon wafer |
JP2002025943A (en) * | 2000-07-12 | 2002-01-25 | Ebara Corp | Substrate film forming method |
JP2002053971A (en) * | 2000-08-03 | 2002-02-19 | Sony Corp | Plating method, plating structure, method for producing semiconductor device, and semiconductor device |
EP1180553A1 (en) * | 2000-08-15 | 2002-02-20 | Air Products And Chemicals, Inc. | CVD process for depositing copper on a barrier layer |
US6596344B2 (en) * | 2001-03-27 | 2003-07-22 | Sharp Laboratories Of America, Inc. | Method of depositing a high-adhesive copper thin film on a metal nitride substrate |
-
2003
- 2003-12-22 AU AU2003299875A patent/AU2003299875A1/en not_active Abandoned
- 2003-12-22 GB GB0513698A patent/GB2417132B/en not_active Expired - Lifetime
- 2003-12-22 WO PCT/US2003/041185 patent/WO2004068576A2/en active Application Filing
- 2003-12-22 KR KR1020057013668A patent/KR101098568B1/en active IP Right Grant
- 2003-12-22 JP JP2004567443A patent/JP5214092B2/en not_active Expired - Lifetime
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5969422A (en) * | 1997-05-15 | 1999-10-19 | Advanced Micro Devices, Inc. | Plated copper interconnect structure |
US6316359B1 (en) * | 1998-02-12 | 2001-11-13 | Motorola Inc. | Interconnect structure in a semiconductor device and method of formation |
US6461675B2 (en) * | 1998-07-10 | 2002-10-08 | Cvc Products, Inc. | Method for forming a copper film on a substrate |
US6479902B1 (en) * | 2000-06-29 | 2002-11-12 | Advanced Micro Devices, Inc. | Semiconductor catalytic layer and atomic layer deposition thereof |
US20020050459A1 (en) * | 2000-11-02 | 2002-05-02 | Kabushiki Kaisha Toshiba | Electronic device manufacturing method |
WO2002045155A2 (en) * | 2000-11-29 | 2002-06-06 | Intel Corporation | ELECTROLESS METHOD OF SEED LAYER DEPOSITION, REPAIR, AND FABRICATION OF Cu INTERCONNECTS |
Also Published As
Publication number | Publication date |
---|---|
JP2006513325A (en) | 2006-04-20 |
KR20050088363A (en) | 2005-09-05 |
AU2003299875A1 (en) | 2004-08-23 |
WO2004068576A3 (en) | 2004-09-10 |
WO2004068576A2 (en) | 2004-08-12 |
KR101098568B1 (en) | 2011-12-26 |
GB2417132A (en) | 2006-02-15 |
JP5214092B2 (en) | 2013-06-19 |
GB0513698D0 (en) | 2005-08-10 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PE20 | Patent expired after termination of 20 years |
Expiry date: 20231221 |