GB2398193A

GB2398193A - Digital delay line

Info

Publication number: GB2398193A
Application number: GB0302931A
Authority: GB
Inventors: Nicholas Faithorn
Original assignee: Zarlink Semiconductor Ltd
Current assignee: Microsemi Semiconductor Ltd
Priority date: 2003-02-08
Filing date: 2003-02-08
Publication date: 2004-08-11
Also published as: GB0302931D0

Abstract

A digital delay line (10) is provided for generating a digital output signal delayed with respect to a digital input signal. The digital delay line (10) comprises a plurality of delay elements (DLY1 to DLYN) arranged in series. The digital output signal is taken from the delay line at the final delay elements DLYN. The digital delay line (10) further comprises insertion control circuitry (15) which causes the digital input signal to be inserted selectively into the delay line at one of the delay elements DLYM preceding or the same as the final delay element DLYN. The insertion delay element is selected based on the desired delay between the input and output digital signals.

Description

: P52509GB 1 2398193

DIGITAL DELAY LINE

The present invention relates to a digital delay line for generating a digital output signal that is delayed with respect to a digital input signal, and also to a phase locked loop and an oscillator circuit comprising such a digital delay line, to a method of generating a digital output signal delayed with respect to a digital input signal, and to a method of calibrating such a digital delay line.

US-5,602,884, entitled "Digital phase locked loop", describes a digital phase locked loop for recovering a stable clock signal from an input signal that is subject to jitter.

The disclosed digital phase locked loop makes use of a tapped delay line to alter the timing of a clock synthesised from a digitally controlled oscillator circuit in the phase locked loop, thereby to reduce the jitter in the generated clock signal. This jitter reduction is achieved by selecting a signal from one of N taps of an N-stage delay line, thereby obtaining the desired phase shift from the system clock.

Figure I of the accompanying drawings shows a conventional N-stage tapped delay line 1 suitable for use in the above phase locked loop, comprising N delay elements DLY' to DLYN. Tap outputs are taken from the N respective delay elements DLY to DLYN, and the N tap outputs are selected and combined by N corresponding tristate buffers 5 to 5N controlled by respective tap select signals TSS to TSSN In order to maintain timing accuracy in the relative delays obtained from the delay line 1, the signal delays from each delay stage DLYn to its associated tristate buffer 5n must match one another. In addition, the delay from each of the tristate buffers 5n to the combined reduced jitter clock output must also match. This may require, for example, the use of a star routing technique to match resistive and capacitive loads and the use of high drive buffers to minimise the impact of tracking loads. However, increasing drive strength in this way is not ideal since the tristate buffers themselves present an output load which increases with the drive capability.

if tristate buffers are not available in the implementation technology, the conventional tapped delay line approach may use a tree of multiplexers to select and combine the tap P52509GB outputs. Figure 2 of the accompanying drawings illustrates such a tree for a delay line 2 comprising eight delay elements DLY to DLYs and seven 2:1 multiplcxers MUX' to MUX'4, MUDS, MUX22 and MUX. Four pairs of tap outputs are taken from successive delay stages of the delay line and are fed to the dual inputs of four corresponding first-row multiplexers MUX; to MUX'4, the outputs of which are controlled by coded tap select signal TESS. Two pairs of successive first-row multiplexer outputs are fed to the dual inputs of two corresponding second-row multiplexers MUX2' and MUX22, the respective outputs of which are controlled by coded tap select signal TSS2. Finally, the two outputs of the second-row multiplexers are fed to the dual inputs of the single third-row multiplexer MUX3', the output of which is controlled by coded tap select signal TSS3. The multiplexers are arranged in a balanced tree formation to equalize path delays.

In practice, jitter reduction circuits will use many more delay stages than the eight depicted in Figure 2, with correspondingly larger multiplex trees, and the problem of balancing delays from the tap outputs to the combined reducedjitter output clock involves many separate nodes. In order to maintain the relative shifts obtained from the delay line, the delays through the multiplexers must match for all inputs to better than the desired jitter. In other words, the difference between the delays through the multiplexers for any two different tap outputs must be less than the delay of a single stage of the delay line. This can present a difficult layout design task when implementing the design in an integrated circuit, especially if the technology and/or digital cell library used does not support 3-state busses.

In addition, in order to obtain a glitch-free output signal, the changes in the tap select control lines must be made in the gaps between output clock pulses. However, the timing of these tap select signals is, by its very nature, asynchronous to the system clock. One solution is to use two parallel delay lines that are used for alternate clock pulses, allowing the tap select for one delay line to be changed while the output is taken from the other delay line. This, however, implies a doubling of the size of the balanced output multiplexer tree, compounding the difficulty of the layout task.

P52509GB Calibration of the conventional delay line, which requires measurement of the number of delay stages equivalent to one system clock period, will now briefly be described.

The number of delay stages equivalent to one system clock period will vary with temperature and operating voltage variations, so calibration is repeated at regular intervals during normal operation. In the conventional tapped delay line, this involves injecting a rising clock edge into the end of the delay line and capturing the state of all the tap outputs on the next rising clock edge. Such a calibration arrangement for an eight-stage delay line is shown in Figure 3 of the accompanying drawings. Inspection of the values captured in N flip-flops 7 will reveal how many stages the pulse passed through during the interval of one system clock period. This calibration may typically be performed on one of the pair of delay lines, the other being assumed to match delays by virtue of its using identical gate types and being physically adjacent to the calibrated line.

According to a first aspect of the present invention there is provided a digital delay line for generating a digital output signal delayed with respect to a digital input signal, comprising: a plurality of delay elements arranged in series, a predetermined one of the delay elements being an output delay element for supplying the digital output signal; insertion control means for causing the digital input signal to be inserted selectively into the delay line at one of the delay elements preceding or the same as the predetermined output delay element. The insertion delay element may be selected based on the desired delay between the input and output digital signals.

In such a digital delay line, the predetermined output delay element may be the final delay element in the series of delay elements. The digital input signal may be a clock signal.

Each delay element in the digital delay line may comprise: an insertion input for receiving the digital input signal; a delay input for receiving an output signal from the preceding delay element in the series; a delay output for outputting the signal passed through the delay element; and control means operable selectively to cause the delay element to pass to its delay output the signal received at the insertion input. The control means may be operable selectively to cause the delay element to pass to its delay output P52509GB either the signal received at the insertion input or the signal received at the delay input.

Each delay element may further comprise a control input for receiving a control signal and the control means operate in dependence upon the received control signal. The digital delay line may further comprise control signal generating means for generating the control signals such that only one of the delay elements is selected for passing the insertion input signal at any one time.

The digital delay line may further comprise input signal distribution means for delivering the input signal to each of the delay elements substantially simultaneously.

The input signal distribution means may comprise a balanced fanout tree.

The digital delay line may further comprise control signal synchronising means for ensuring the control signals operate synchronously with the digital input signal. The control signal synchronizing means and the control means may be located in each delay element and may comprise an AND gate connected to receive the control signal and the digital input signal, an OR gate connected to receive the delay input signal and the output of the AND gate, with the output of the OR gate providing the signal to be passed through the delay element to the delay output.

According to a second aspect of the present invention there is provided a method of generating a digital output signal delayed with respect to a digital input signal, comprising the steps of: selectively inserting the digital input signal into a delay line, comprising a plurality of delay elements arranged in series, at one of the delay elements preceding or the same as a predetermined output delay element, the insertion delay element being selected based on the desired delay between the input and output digital signals; and taking the digital output signal from the delay line at the predetermined output delay element.

According to a third aspect of the present invention there is provided a method of calibrating a digital delay line according to the first aspect of the present invention, comprising determining the earliest delay element in the series of delay elements into which a calibration pulse is inserted such that the pulse appears at the output delay element a predetermined calibration time later.

P52509GB s According to a fourth aspect of the present invention there is provided an oscillator circuit comprising a digital delay line according to the first aspect of the present invention.

According to a fifth aspect of the present invention there is provided a phase locked loop comprising a digital delay line according to the first aspect of the present invention.

Reference will now be made, by way of example, to the accompanying drawings, in which: Figure 1, discussed hereinbefore, is a block diagram showing a conventional N-stage tapped delay line with tristate buffers to select the output; Figure 2, also discussed hereinbefore, is a block diagram of a conventional eight-stage tapped delay line with a balancedtree formation of multiplexers to select the output; Figure 3, also discussed hereinbefore, is a block diagram showing circuitry for use in calibrating a conventional eight-stage delay line; Figure 4 is a block diagram for use in illustrating the basic principle of an embodiment of the present invention; Figure 5 is a block diagram showing an N-stage digital delay line according to a specific embodiment of the present invention; Figure 6 is a logic diagram showing means for controlling the insertion of an input signal into a single stage of a digital delay line embodying the present invention; Figure 7 is an illustrative block diagram showing the use of a delay line embodying the present invention connected to an oscillator in a phase locked loop; and P52509GB Figure 8 is a block diagram showing circuitry for use in calibrating an N-stage digital delay line embodying the present invention.

Figure 4 is a block diagram for use in illustrating the basic principle of a digital delay line embodying the present invention for generating a digital output signal delayed with respect to a digital input signal. As shown in Figure 4, a digital delay line 10 embodying the present invention comprises N delay elements IDLY to DLYN arranged in series, and an insertion control portion 15. The insertion control portion 15 has a first input for receiving the digital input signal that is to be delayed by the digital delay line 10, a second input for receiving a control signal CS from a control signal generator 12, and N outputs connected respectively for receipt by the N delay elements DLY' to DLYN. The delayed output signal is taken from the final delay element DLYN.

The insertion control portion 15 acts, based on the received control signal CS, to cause the digital input signal to be inserted selectively into the delay line at one of the delay elements DLYM preceding or the same as the final output delay element DLYN, by routing the input signal to the selected insertion delay element DLYM. Once inserted into the delay line, the signal propagates through each of the subsequent delay elements in turn.

If the input signal is inserted at delay element M, and the delayed output signal is taken from delay element N. the signal propagates through (N-M+1) delay elements.

Therefore if the delay associated with each delay element is represented as D, then this corresponds to a delay time of D*(N-M+1) between the input and output signals.

The insertion delay element can therefore selected based on the desired delay between the input and output digital signals, being inserted earlier in the delay line for a longer delay and later in the delay line for a shorter delay. The input signal may be any type of digital signal, for example a clock signal.

Compared with a conventional delay line, therefore, an embodiment of the present invention involves changing the mechanism for selecting the phase delay obtained from the delay line. A conventional tapped delay line uses a single, common insertion point P52509GB for an input signal, such as a system clock pulse, and selects the stage from which the delayed signal is obtained. On the other hand, an embodiment of the present invention selects a stage into which the input signal is inserted and the output of a particular known delay element, usually the final delay element, is used as the source of the delayed output signal.

For time-critical applications such as the jitter-reducing phase locked loop described above, this has the major advantage that there is no need to balance the delays from various tap outputs as there is for a conventional delay line. Instead, the input signal (e.g. a system clock) must be distributed to all potential insertion delay elements with a skew less than the required output jitter. However, such a requirement for low-skew clock distribution is common in integrated circuit layout and is easily addressed, as will be described below.

Figure 5 shows a specific embodiment of the present invention. A delay line 20 embodying the present invention comprises N delay elements DLY' to DLYN arranged in series. The input signal, which in this embodiment is a system clock, is distributed by a balanced fanout tree including buffer 22 and tracking 24, to each delay element of the delay line, IDLY through DLYN. Each delay element DLYn has an input for receiving an insert control signal ICSn corresponding to that delay element. As will be described in more detail below, depending on the state of the insert control signal ICSn fed to a particular delay element DLYn, a clock pulse is either inserted into the delay line at that element or is blocked.

Figure 6 shows one possible implementation of insert control logic to be included in each delay element DLYn for causing the input signal, in this example a system clock, to be selectively inserted into or blocked at that delay element. The insert control logic comprises an AND gate 26 connected to receive at its respective inputs the insert control signal ICSn for that delay element DLYn and the system clock. The output of the AND gate 26 is received at one of the inputs of an OR gate 28. The other input of the OR gate 28 is connected to receive the signal "delay_in" which is the output from the preceding delay element DLYn i. The output of the OR gate 28 is fed to the main delay-producing circuitry 30, which itself outputs the delayed output signal "delay_out" P52509GB for feeding to the input of the subsequent delay element DLYn+' or, if delay element DLYn is the last in the delay line, "delay_out" represents the final delayed output signal.

With the insert control logic shown in Figure 6, a positive-going system clock pulse will be inserted into the delay line if the insert control signal ICSn is a logical high. If the insert control signal ICSn is logical low, the "delay_in" signal will be passed through the delay element to appear as the "delay_out" signal, modified only by the delay of the element.

Although the AND gate 26 and the OR gate 28 are shown separated in Figure 6 from the delay-producing circuitry 30, in practice the insertion gating will be included in the stage delay. It will also be appreciated that various other logic circuits could be used to perform an equivalent function to that shown in Figure 6. For example, with the Figure 6 circuitry, when the system clock is to be inserted into a particular delay element DLYn (control signal ICSn at a logical high level), then for correct operation the "delay_in" signal from the previous delay element DLYn must be at a logical low level since an OR logical function is performed on the inserted system clock and the "delay_in" signal. Alternative circuitry could be provided that is operable selectively to cause the delay element to pass to its delay output either the signal received at said insertion input or the signal received at said delay input, rather than a logical combination of both.

Another function performed by the insert control logic 26, 28 of Figure 6 is to ensure that the insert control signals ICY to ICSN, which replace the output tap select signals of the conventional design described above, operate synchronously to the system clock, and the N insert control signals ICS to ICSN may be changed at any time during the clock low period without risk of introducing glitches. This synchronous operation of the insert control signals has a major advantage over the conventional tapped delay line approach described above in that it obviates the need to have dual delay lines handling alternate clock pulses, and therefore leads to a far greater simplicity of design and a reduction in chip size.

Figure 7 is an illustrative block diagram showing the use of a delay line as described with reference to Figure 4 connected to an oscillator in a phase locked loop, similar to P52509GB the jitter-reducing arrangement used in US-5,602,884 as mentioned above. The delay line 20 of Figure 4 is arranged in a phase locked loop 40 to receive its input signal (clock signal) from a voltage controlled oscillator (VCO) 36, and the output signal (delayed clock signal) of the delay line 20 is fed back to a phase comparator 34.

In this example, the voltage controlled oscillator 36 generates a control signal CS (corresponding to that shown in Figure 4) based on the time error in the input signal to the delay line 20, and this control signal CS is used as the control signal CS input to the insertion control portion 15 shown in Figure 4. Therefore, in this example, the voltage controlled oscillator 36 acts as the control signal generator 12 of Figure 4. The phase comparator 34 also receives a clock signal CLK that to be stabilised and controls the voltage controlled oscillator 36 based on a comparison of the respective phases of the clock signal CLK and the output signal fed back from the delay line 20.

Calibration of the delay line architecture embodying the present invention is not easily performed on the active delay line as all clock pulses inserted into the line appear on the reduced jitter output clock and there is no opportunity to inject pulses for delays greater than one system clock period. However, the conventional technique of characterising an identical, physically adjacent delay line can conveniently be used. Because such a line is dedicated to calibration, a sequential approach to the calibration process can replace the conventional "parallel" approach described above, utilising far fewer D- type flip-flops.

One possible calibration procedure will now be described with reference to Figure 8. A positive-going system clock pulse is inserted into delay element DLY' and the value of the reduced jitter output clock is captured by a D-type flip flop 32 on the next rising system clock edge. If the delay of N delay line elements is greater than one system clock period, the pulse will not have reached the end of the delay line and the D-Type flip flop 32 will capture a logic 0. After a short interval, sufficient for the injected pulse to clear out of the delay line, the process is repeated, this time inserting the pulse into delay element DLY2, and so on. Eventually, when the clock pulse is inserted into delay element DLYM (as depicted in Figure 8), the delay to the output stage, equal to (N P52509GR M+ I) single delay stages, will be less than the system clock period and the D-type flip flop 32 will capture a logic 1. In this way the delay line can be calibrated.

It will be appreciated that, although it is convenient to provide a separate dedicated calibration delay line, calibration can also be performed on the active delay line by provision of appropriate control circuitry which, during the calibration procedure, re- routes the output of the final delay stage DLYN to a D-type flip flop rather than to the reduced jitter output and which causes the generation of appropriate calibration pulses for distribution to the delay elements rather than the usual continuous clock signal.

Although the above embodiment has been described as including only a single delay line and a single system clock, it will be appreciated that the system described can be expanded for multiple clocks, with each output clock generated from its own dedicated jitter reduction delay line, but with a single calibration delay line for a large number of identical, physically adjacent jitter reducing delay lines.

It will also be appreciated that a delay line embodying the present invention will find practical use in the field of clock signal re-timing outside the context of a phase locked loop as shown in Figure 7, for example simply connected to an oscillator for providing a specified and accurate delay to the output of the oscillator for other purposes.

In addition, although the main application of an embodiment of the invention is for use in a jitter-reducing environment to reduce the jitter of a synthesised clock generated by a digitally controlled oscillator, the approach may be used to apply a variable delay, with a precision of less than one system clock period, to any synchronous signal.

Claims

P52509GB CLAIMS: 1. A digital delay line for generating a digital output

signa] delayed with respect to a digital input signal, comprising: a plurality of delay elements arranged in series, a predetermined one of said delay elements being an output delay element for supplying said digital output signal; insertion control means for causing said digital input signal to be inserted selectively into the delay line at one of said delay elements preceding or the same as said predetermined output delay element.
2. A digital delay line as claimed in claim 1, wherein said predetermined output delay element is the final delay element of said plurality of delay elements arranged in series.
3. A digital delay line as claimed in claim 1 or 2, wherein each delay element comprises: an insertion input for receiving said digital input signal; a delay input for receiving an output signal from the preceding delay element in said series; a delay output for outputting the signal passed through the delay element; and control means operable selectively to cause the delay element to pass to its delay output the signal received at said insertion input.
4. A digital delay line as claimed in claim 3, wherein said control means are operable selectively to cause the delay element to pass to its delay output either the signal received at said insertion input or the signal received at said delay input.
5. A digital delay line as claimed in claim 3 or 4, wherein each delay element further comprises a control input for receiving a control signal and said control means operate in dependence upon the received control signal.

P52509GB r:
6. A digital delay line as claimed in claim 5, further comprising control signal generating means for generating said control signals such that only one of said delay elements is selected for passing the insertion input signal at any one time.
7. A digital delay line as claimed in any preceding claim, further comprising input signal distribution means for delivering said input signal to each of said delay elements substantially simultaneously.
8. A digital delay line as claimed in claim 7, wherein said input signal distribution means comprise a balanced fanout tree.
9. A digital delay line as claimed in any one of claims 3 to 8, further comprising control signal synchronising means for ensuring the control signals operate synchronously with the digital input signal.
10. A digital delay line as claimed in claim 9, wherein said control signal synchronising means and said control means are located in each said delay element and comprise an AND gate connected to receive said control signal and said digital input signal, an OR gate connected to receive said delay input signal and the output of said AND gate, with the output of said OR gate providing the signal to be passed through the delay element to said delay output.
11. A digital delay line as claimed in any preceding claim, wherein said digital input signal is a clock signal.
12. A method of generating a digital output signal delayed with respect to a digital input signal, comprising the steps of: selectively inserting said digital input signal into a delay line, comprising a plurality of delay elements arranged in series, at one of the delay elements preceding or the same as a predetermined output delay element, the insertion delay element being selected based on the desired delay between the input and output digital signals; and taking said digital output signal from the delay line at said predetermined output delay element.

J P52509GB
13. A method of calibrating a digital delay line as claimed in any one of claims I to 11, comprising determining the earliest delay element in said plurality of delay elements arranged in series into which a calibration pulse is inserted such that the pulse appears at the output delay element a predetermined calibration time later.
14. A digital delay line substantially as hereinbefore described with reference to Figures 4 to 8 of the accompanying drawings. i
15. A method of generating a delayed digital output substantially as hereinbefore described with reference to Figures 4 to 8 of the accompanying drawings.
16. A method of calibrating a digital delay line substantially as hereinbefore - described with reference to Figures 4 to 8 of the accompanying drawings.
17. A digital oscillator comprising a digital delay line as claimed in claim 11 or substantially as hereinbefore described with reference to Figures 4 to 8 of the accompanying drawings.
18. A phase locked loop comprising a digital delay line as claimed in claim 11 or substantially as hereinbefore described with reference to Figures 4 to 8 of the accompanying drawings.