GB2390224A - Method of forming nickel silicide using a one-step rapid thermal anneal process and backend processing - Google Patents

Method of forming nickel silicide using a one-step rapid thermal anneal process and backend processing Download PDF

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Publication number
GB2390224A
GB2390224A GB0315661A GB0315661A GB2390224A GB 2390224 A GB2390224 A GB 2390224A GB 0315661 A GB0315661 A GB 0315661A GB 0315661 A GB0315661 A GB 0315661A GB 2390224 A GB2390224 A GB 2390224A
Authority
GB
United Kingdom
Prior art keywords
nickel
silicide
temperature treatment
high resistance
nickel silicide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB0315661A
Other versions
GB2390224B (en
GB0315661D0 (en
Inventor
Eric N Paton
Ercan Adem
Jacques J Bertrand
Paul R Besser
Matthew S Buynoski
John Clayton Foster
Paul L King
George Jonathan Kluth
Minh Van Ngo
Christy Mei-Chu Woo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/729,699 external-priority patent/US6605513B2/en
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of GB0315661D0 publication Critical patent/GB0315661D0/en
Publication of GB2390224A publication Critical patent/GB2390224A/en
Application granted granted Critical
Publication of GB2390224B publication Critical patent/GB2390224B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
    • H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A self-aligned silicide process that can accommodate a low thermal budget and form silicide regions (64, 66) of small dimensions in a controlled reaction. In a first temperature treatment, nickel metal or nickel alloy (52) is reacted with a silicon material (46) to form at least one high resistance nickel silicide region (56, 58). Unreacted nickel (54) is removed. A dielectric layer (60) is then deposited over the high resistance nickel silicide regions (56, 58). In a second temperature treatment, the at least one high resistance nickel silicide regions (56, 58) and dielectric (60) are reacted at a prescribed temperature to form at least one low resistance silicideregion (64, 66) and process the dielectri c layer (60). Bridging between regions is avoided by the two-step process as silicide growth is controlled, and unreacted nickel (54) between silicide region (56, 58) is removed after the first temperature treatment. The processing of the high resistance nickel silicide regions (56, 58) and the dielectric layer (60) are conveniently combined into a single temperature treatment. In other embodiments, the second temperature treatment is performed prior to, and separate from, the depositing and processing of the dielectric layer (60).

Description

GB 2390224 A continuation (72) cons: Ercan Adem Jacques J Bertrand Paul R
Besser Matthew S Buynoskl John Clayton Foster Paul L King George Jonathan Kluth Mlnh Van Ngo Christy Mel-Chu Woo (74) Agent and/or Address for Service: Brookes Batchellor 102-108 Clerkenwell Road, LONDON, EC1M 5SA, United Kingdom
GB0315661A 2000-12-06 2001-12-03 Method of forming nickel silicide using a one-step rapid thermal anneal process and backend processing Expired - Fee Related GB2390224B (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US72969800A 2000-12-06 2000-12-06
US09/729,699 US6605513B2 (en) 2000-12-06 2000-12-06 Method of forming nickel silicide using a one-step rapid thermal anneal process and backend processing
PCT/US2001/045829 WO2002047145A1 (en) 2000-12-06 2001-12-03 Method of forming nickel silicide using a one-step rapid thermal anneal process and backend processing

Publications (3)

Publication Number Publication Date
GB0315661D0 GB0315661D0 (en) 2003-08-13
GB2390224A true GB2390224A (en) 2003-12-31
GB2390224B GB2390224B (en) 2004-12-08

Family

ID=27111928

Family Applications (1)

Application Number Title Priority Date Filing Date
GB0315661A Expired - Fee Related GB2390224B (en) 2000-12-06 2001-12-03 Method of forming nickel silicide using a one-step rapid thermal anneal process and backend processing

Country Status (7)

Country Link
EP (1) EP1342260A1 (en)
JP (1) JP2004521486A (en)
CN (1) CN1633703A (en)
AU (1) AU2002230565A1 (en)
GB (1) GB2390224B (en)
TW (1) TW531792B (en)
WO (1) WO2002047145A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7622374B2 (en) 2005-12-29 2009-11-24 Infineon Technologies Ag Method of fabricating an integrated circuit

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7232756B2 (en) 2003-04-16 2007-06-19 Samsung Electronics Co., Ltd. Nickel salicide process with reduced dopant deactivation
KR100870176B1 (en) * 2003-06-27 2008-11-25 삼성전자주식회사 Nickel alloy salicide process, Methods of fabricating a semiconductor device using the same, nickel alloy silicide layer formed thereby and semiconductor devices fabricated using the same
US7592674B2 (en) * 2004-06-23 2009-09-22 Nec Corporation Semiconductor device with silicide-containing gate electrode and method of fabricating the same
US7385294B2 (en) 2005-09-08 2008-06-10 United Microelectronics Corp. Semiconductor device having nickel silicide and method of fabricating nickel silicide
CN1937181B (en) * 2005-09-19 2010-11-17 联华电子股份有限公司 Semiconductor element with nickel silicide and method for preparing nickel silicide
US7456095B2 (en) * 2005-10-03 2008-11-25 International Business Machines Corporation Method and apparatus for forming nickel silicide with low defect density in FET devices
JP2007242894A (en) * 2006-03-08 2007-09-20 Toshiba Corp Semiconductor device and its manufacturing method
CN100442460C (en) * 2006-04-03 2008-12-10 中芯国际集成电路制造(上海)有限公司 Method for forming nickel silicide by plasma annealing
US7432255B2 (en) * 2006-05-16 2008-10-07 Hoffmann-La Roche Inc. 1H-indol-5-yl-piperazin-1-yl-methanone derivatives
JP5538975B2 (en) 2010-03-29 2014-07-02 ルネサスエレクトロニクス株式会社 Manufacturing method of semiconductor device
CN102468150B (en) * 2010-11-19 2013-12-04 中芯国际集成电路制造(上海)有限公司 Method for forming semiconductor device
CN103165485B (en) * 2011-12-08 2015-11-25 中芯国际集成电路制造(上海)有限公司 The monitoring method of Millisecond annealing technology stability

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0831521A2 (en) * 1996-09-18 1998-03-25 Texas Instruments Incorporated Method for forming a silicide region
EP0836223A2 (en) * 1996-10-08 1998-04-15 Texas Instruments Inc. Method of forming a silicide layer
EP0936664A2 (en) * 1998-02-13 1999-08-18 Sharp Kabushiki Kaisha Partial silicidation method to form shallow source/drain junctions
US5953612A (en) * 1997-06-30 1999-09-14 Vlsi Technology, Inc. Self-aligned silicidation technique to independently form silicides of different thickness on a semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0831521A2 (en) * 1996-09-18 1998-03-25 Texas Instruments Incorporated Method for forming a silicide region
EP0836223A2 (en) * 1996-10-08 1998-04-15 Texas Instruments Inc. Method of forming a silicide layer
US5953612A (en) * 1997-06-30 1999-09-14 Vlsi Technology, Inc. Self-aligned silicidation technique to independently form silicides of different thickness on a semiconductor device
EP0936664A2 (en) * 1998-02-13 1999-08-18 Sharp Kabushiki Kaisha Partial silicidation method to form shallow source/drain junctions

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7622374B2 (en) 2005-12-29 2009-11-24 Infineon Technologies Ag Method of fabricating an integrated circuit

Also Published As

Publication number Publication date
GB2390224B (en) 2004-12-08
GB0315661D0 (en) 2003-08-13
WO2002047145A1 (en) 2002-06-13
JP2004521486A (en) 2004-07-15
TW531792B (en) 2003-05-11
EP1342260A1 (en) 2003-09-10
AU2002230565A1 (en) 2002-06-18
CN1633703A (en) 2005-06-29

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732E Amendments to the register in respect of changes of name or changes affecting rights (sect. 32/1977)

Free format text: REGISTERED BETWEEN 20091210 AND 20091216

PCNP Patent ceased through non-payment of renewal fee

Effective date: 20111203