GB2362029A - Multi-layer structure for MOSFET Spacers - Google Patents
Multi-layer structure for MOSFET Spacers Download PDFInfo
- Publication number
- GB2362029A GB2362029A GB0025340A GB0025340A GB2362029A GB 2362029 A GB2362029 A GB 2362029A GB 0025340 A GB0025340 A GB 0025340A GB 0025340 A GB0025340 A GB 0025340A GB 2362029 A GB2362029 A GB 2362029A
- Authority
- GB
- United Kingdom
- Prior art keywords
- layer
- integrated circuit
- recited
- spacer
- low
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 125000006850 spacer group Chemical group 0.000 title claims abstract description 38
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 27
- 239000000463 material Substances 0.000 claims abstract description 23
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 16
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 16
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 15
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 238000002955 isolation Methods 0.000 claims abstract description 12
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims abstract description 4
- 229910052799 carbon Inorganic materials 0.000 claims abstract description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 8
- 150000004767 nitrides Chemical class 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 8
- 229910021426 porous silicon Inorganic materials 0.000 claims description 4
- 238000005530 etching Methods 0.000 abstract description 16
- 230000003071 parasitic effect Effects 0.000 abstract description 10
- 238000000034 method Methods 0.000 abstract description 7
- 230000008569 process Effects 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 57
- 239000003989 dielectric material Substances 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 5
- 239000000969 carrier Substances 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 230000002411 adverse Effects 0.000 description 4
- 230000008901 benefit Effects 0.000 description 4
- 230000005669 field effect Effects 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 244000208734 Pisonia aculeata Species 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 210000003323 beak Anatomy 0.000 description 1
- 230000001010 compromised effect Effects 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 230000002939 deleterious effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000010561 standard procedure Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
Abstract
A multi-layer spacer is formed adjacent a gate 301 of a FET structure. The multi-layer spacer includes a layer of low-k material 306 which reduces parasitic capacitance, and a layer of material which enables etch selectivity relative 307 to the substrate 101 and isolation oxides 301. The process helps avoid over-etching of active and isolation regions. The layers are preferably porous or carbon doped silicon dioxide 306 and silicon nitride 307. The transistor may be a lightly doped drain (LLD) structure.
Description
2362029 Multi-Layer Structure For MOSFET Spacers
Field of the Inventio
The present invention relates to a spacer for a metaboxidesemiconductor field effect transistor (MOS FET).
Back&Lomd of the Invention Device scaling in integrated circuits often requires thinner gate oxides and more bighly-doped channels. Tbimer gate oxides and higher-doped channels result in an increase in the horizontal and vertical components of the electric field near the drain (referred to as the drain field). Carriers accelerated by the electric field can become '%oe' and overcome the oxide barrier resulting in injection into the gate oxide.
Hot carriers injected into the gate oxide may degrade device performance.
Accordingly, it is desirable to reduce the incidence of hot carriers.
One technique used to reduce the incidence of hot carriers is to reduce the drain field. Lightly doped drain (LDD) structures are used to reduce the drain field and abate many of the problems associated with hot carriers. In an LDD structure, the source and drain are formed typically through two map steps. A first implant forms the lightly doped region. A spacer is then formed on either side of the gaw and serves as a mask during formation of the more heavily doped regions of the source and drain.
While spacers are beneficW to the formation of LDD structures, there are certain drawbacks associated with tkm and their fabrication. To this end, in many instances a relatively thick field oxide region is used to electrically isolate active device areas. The field oxide is normally formed by the local oxidation of silicon (LOCOS).
ne LOCOS process consists essentially of depositing or thermally growing a thin pad oxide of silicon dioxide (Si02) on the substrate surface. Thereafter a layer of silicon nitride (SiN) is deposited over the pad oxide. The SiN serves as a barrier to thermal oxidation. This silicon nitride layer is normally patterned leaving portions of the SiN over the silicon substrate where active devices are desired. The substrate is then annealed to form the field oxide in the exposed areas. During this process, a portion of the field oxide naturally forms under the perimeter of the nitride layer by lateral oxidation of the silicon substrate and is commonly referred in the industry as a "birds beale' because of its shape.
During the fabrication of the spacer, it is often necessary to account for variations in the spacer oxide layer thickness with an over-etch. Through the over-etch sequence, the source and drain regions at the silicon surface are subjected to over etching to ensure a good ohmic contact to the source and drain. As a result of the over-etch sequence excessive etching of the field oxide may occur. This excess etching is known as birds beak "pullback" and may result in gate dielectric thinning and a reduction in isolation achieved by the field oxide. Thus, over-etching of the source and drain regions may result in leakage current at the sourceldrain junctions. The leakage at the source/drain junctions is typically localized in the junction directly beneath the spacer edge in the LDD structure. This leakage problem is generally attributed to silicon loss and etch damage in the substrate arising from the spacer over-etch.
In order to avoid the drawbacks associated with over-etch in conventional silicon dioxide spacer structures, alternative materials have been used as the spacer material in lieu of silicon dioxide. One such material is silicon nitride.
Because different etch chemistries may be used, etch selectivity between the field oxide (silicon dioxide) and the silicon nitride can be achieved and problems associated with over-etch may be reduced. Unfortunately, the dielectric constant of silicon nitride is on the order of two times that of silicon dioxide. The higher dielectric constant of the silicon nitride increases parasitic capacitance between the gate oxide and the source/drain regions. This deleterious parasitic capacitance adversely impacts device response and speed. Therefore, while problems associated with over- etching may be reduced by the use of a silicon nitride spacer, device performance may be compromised.
Accordingly, what is needed is a lightly doped drain structure which overcomes the adverse effects of over-etch while simultaneously avoiding the adverse impact of parasitic capacitance associated with prior LDD structures.
Summ= of the Invention The present invention relates to a multi-layer spacer for a lightly doped drain field effect transistor structure (LDD-FET). The spacer includes a first layer adjacent a gate structure, and a second layer disposed over the first layer. Preferably, the first layer is a material having a relatively low dielectric constant, while the second layer is chosen to exhibit etch selectivity relative to the materials used for the active device and device isolation regions. I'his selectivity enables formation of the IDD spacer without substantial over-etch. Accordingly, the present invention reduces parasitic capacitance effects by virtue of the low-k dielectric while etch selectivity enables the formation of the spacer without the adverse impact of over- etch.
Brief Despription of the Drawin The invention is best understood from the following detailed description when read with the accompanying drawing figures. It is emphasized that the various features are not necessarily drawn to scale. In fact, the dimensions of the various features in the drawings may be arbitrarily increased or reduced for clarity of discussion.
Figure 1 shows the gate stack structure in an exemphuy embodiment of the present invention with the layer of low-k dielectric material disposed thereover.
Figure 2 shows the gate stack structure of an exemplary embodiment of the present invention having a low-k layer and a subsequent layer disposed thereover.
Figure 3 is an exemplary embodiment of the present invention showing the resultant spacer structure with a first layer of low-k dielectric material and an outer layer of dielectric materiaL 3 Detailed Dt.ti n of the Inventio Briefly, the present invention is drawn to a multi-layer spacer and its method of fabrication. Fig. 3 is a cross sectional view of an exemplary embodiment of the invention showing the gate 301 of a field effect transistor (FET) having a lightly doped drain region 302 and a lightly doped source region 303. The drain 304 and source 305 are more heavily doped. In the illustrative embodiment, the FET is NMOS with regions 302, 303 doped n7 and regions 304 and 305 doped e. The multilayer spacer of the present invention has a first layer 306 and a second layer 307. In the exemplary embodiment, the first layer 306 is a low-k dielectric material. The material used to form second layer 307 is chosen to enable the fabrication of the spacer through etch selectivity in a manner which does not result in over-etching of active regions (308, 309) of the device nor of the field oxide isolation regions (31.0, 311).
Accordingly, by virtue of the exempluy spacer structure shown in Fig. 3, parasitic capacitance between the gate 301 and the source 305 and drain 304 is reduced, while 1-9 the problems of over-etch associated with single layer silicon dioxide spacers are overcome.
Turning to Fig. 1, local oxidation- of silicon (LOCOS) is used to form the exemplary field oxide isolation regions 310, 311. Alternatively, trench isolation can be employed and formed by known techn iques. The gate 301 is disposed over the substrate 101. Illustratively, the gate 301 is a bilayer of polysilicon with an oxide layer acting as the gate dielectric. The gate may also include a high dielectric constant (high-k) material. One example of a gate structure incorporating a high-k dielectric is disclosedin EP-A-0851473 the disclosure of which is specifically incorporated herein by reference.
The reduction in parasitic capacitance- by virtue of the present invention affords particular benefits in MO$ structures which use a high-k gate dielectric layer.
When the high-k gate materials are used for the gate dielectric, the dimensional thickness of the gate dielectric, is generally greater. Tbs thicker high- k gate dielectric layer may result in an increase in the parasitic interaction between the gate and the sourceldrain. Accordingly, the low-k spacer layer of the present invention, which reduces the parasitic capacitance, is of particular benefit in high-k dielectric gate structures.
4 The first layer 306 is illustratively a low-k material having a dielectric constant approximately in the range of 2.1 to 2.6. In an exemplary embodiment shown in Fig. 1, the low-k dielectric 306 is silicon dioxide doped with carbon at a level of approximately 10% (carbon doped silicon dioxide is an example of porous silicon dioxide) - However, other materials maybe used as the low-k layer 306. In the exemplary embodiment, the low-k layer 306 is fabricated by a standard spin-on techniqu. e, and has a thickness in the range of approximately 5-50 nm.
After the first layer 306 is deposited, the second layer 307 is deposited as shown in Figure 2. The material chosen for the second layer 307 is one which enables the selective etching to form the spacer layer, while avoiding the problems experienced in the prior art with over-etching. In an illustrative embodiment, the material chosen for the second layer 307 is silicon nitride, although other materials that would enable the desired etch selectivity may be used. The silicon nitride layer 307 may be deposited by standard technique, for example by plasma enhanced chemical vapor deposition (PECVD) or low temperature (<750'C) SiH4 based low pressure chemical vapor deposition (LPCVD). In this embodiment, the layer of nitride 307 has a thickness on the order of approximately 20-80 mn. After the nitride layer 307 is deposited, an etching sequence is effected to form the spacer.
In an exemplary embodiment, the etching to selectively remove the layer 307 is done by reactive ion etching (RIE), which is anisotropic. In this first etch step, the first layer 306 and the second layer 307 act as mask for the field oxide regions (310, 311), as well for as the regions of the source and drain shown at 308, 309, respectively. The etch chemistry chosen for the first etch step should be one that will etch the layer 307 without appreciably etching the field oxide (310, 311) or regions
308, 309 of the source and drain. In the exemplary embodiment in which layer 307 is silicon nitride, C2F6 is used to carry out the nitride etch, and a CH3F end point - detection technique is used to determine the end of the etch. In this step, the nitride layer 307 will be etched but the underlying layers 306, 3 10 and 311 will not be etched appreciably due to the etch selectivity of the chosen chemistry. After the etching of the layer 307 is complete, the second etch step used to form the spacer is carried out. The chosen etch chemistry in this step will etch the first layer 306 much more rapidly than the field oxide (310, 311), which is normally a high temperature grown oxide. In the exemplary embodiment in which layer 306 is porous silicon dioxide, a REE step is done with CH4 used to carry out the selective etch.
By virtue of the present invention, certain advantages are realized. The chosen materials and etch chemistries result in etch selectivity which reduces over etching of the isolation and active regions. In the illustrative embodiment, the multi layer spacer is comprised generally of a relatively thick nitride layer disposed over a relatively thin low-k layer. Selective etching enables the removal of the nitride layer in selective areas. Thereafter, the low-k layer is removed by conventional techniques with the required over-etch to assure its proper removal from the active regions of the device for example. Over-etch tolerances are usually on the order of 10%- 20% to assure removal of unwanted materials. In the invention of the present disclosure where the over-etch is carried out on a relatively thin layer of low-k material, a 10%-20% over-etch is acceptable. This is in contrast to conventional techniques in which a single layer having a thickness of greater than 100 ran is over-etched with a tolerance of 10%-20%. As outlined previously, such a degree of over-etch can have degrading effects on the device.
The invention having been described in detail above, it is clear that variations and modifications of the present inventions will be readily apparent to one ha:ving ordinary skill in the semiconductor art. To this end, the present invention discloses a structure and its method of manufacture for use in a MOSFET device which is preferably an LDD device using a spacer layer. The spacer layer has the benefits of reducing parasitic capacitance between the gate stack and the source/drain regions associated with certain dielectric materials by having a multi- layer spacer with at least one layer of low-k dielectric material incorporated into the spacer. At least the outer layer of the spacer is chosen for its etch selectivity, enabling the formation of the spacer, while avoiding the problems associated with over-etching as discussed above.
Claims (1)
- What is Claimed:1 1. An integrated circuit, comprising:2 a substrate; 3 a gate disposed over said substrate; and 4 a multi-layer spacer including a low-k layer.1 2. An integrated circuit as recited in claim 1, wherein said low-k layer 2 is porous silicon dioxide.1 3. An integrated circuit as recited in claim 2, wherein said porous 2 silicon dioiiide is carbon doped.1 4. An integrated circuit as recited in claim 1, wherein multi-layer spacer 2 includes a layer of silicon nitride.1 5. An integrated circuit as recited in claim 2, wherein said porous 2 silicon dioxide has a thickness in the range of 5-50 run.1 6. An integrated circuit as recited in claim 4, wherein said silicon 2 nitride has a thickness in the range of 20-80 mn.1 7. An integrated circuit as recited in claim 1, wherein said low-k 2 dielectric has a dielectric constant in the range of approximately 2.1 to 2.6.1 8. An integrated circuit, comprising:2 a gate disposed over a substrate; and 3 a spacer disposed adjacent said gate, said spacer having at least two 4 layers and one of said layers is a low-k layer.1 9. An integrated circuit as recited in claim 8, wherein said low-k 2 material is porous silicon dioxide.1 10. An integrated circuit as recited in claim 8, wherein said porous 2 silicon dioxide has a thickness on the order of 5-50 nm.1 11. An integrated circuit as recited in claim 8, wherein one of said at 2 least two layers is silicon dioxide.1 12. An integrated circuit as recited in claim 8, wherein said low-k layer 2 has a thickness in the range of approximately 2.1 to 2.6.13. An integrated circuit, comprising:2 a substrate; 3 a gate disposed over said substrate; and 4 a multi-layer spacer including a layer which exhibits etch selectivity 5 relative to said substrate. 14. An integrated circuit as recited in claim 13, wherein an isolation 2 material is disposed near said gate and said layer exhibits etch selectivity relative to 3 said isolation material. 1 15. An integrated circuit as recited in claim 13, wherein said multi-layer 2 spacer further includes a low-k dielectric layer. 1 16. An integrated circuit as recited in claim 14, wherein said isolation 2 material is a field oxide. 1 17. An integrated circuit as recited in claim 14, wherein said isolation 2 material is a trench oxide.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US42808599A | 1999-10-27 | 1999-10-27 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB0025340D0 GB0025340D0 (en) | 2000-11-29 |
| GB2362029A true GB2362029A (en) | 2001-11-07 |
Family
ID=23697490
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB0025340A Withdrawn GB2362029A (en) | 1999-10-27 | 2000-10-16 | Multi-layer structure for MOSFET Spacers |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JP2001177090A (en) |
| KR (1) | KR20010051263A (en) |
| GB (1) | GB2362029A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2840453A1 (en) * | 2002-06-04 | 2003-12-05 | St Microelectronics Sa | METHOD FOR MANUFACTURING A MOS TRANSISTOR OF REDUCED GRID LENGTH, AND INTEGRATED CIRCUIT COMPRISING SUCH A TRANSISTOR |
| EP2876677A1 (en) * | 2013-11-25 | 2015-05-27 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Method for forming spacers of a transistor gate |
| US9502418B2 (en) | 2014-10-02 | 2016-11-22 | International Business Machines Corporation | Semiconductor devices with sidewall spacers of equal thickness |
| CN107689329A (en) * | 2016-08-03 | 2018-02-13 | 中芯国际集成电路制造(上海)有限公司 | Fin formula field effect transistor and its manufacture method |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4867176B2 (en) * | 2005-02-25 | 2012-02-01 | ソニー株式会社 | Manufacturing method of semiconductor device |
| JP5817205B2 (en) * | 2011-04-28 | 2015-11-18 | 株式会社デンソー | Manufacturing method of semiconductor device |
| CN105336592B (en) * | 2014-07-09 | 2018-04-10 | 中芯国际集成电路制造(上海)有限公司 | Form the post tensioned unbonded prestressed concrete technique of high-K metal gate device |
| KR102613157B1 (en) | 2021-11-09 | 2023-12-12 | 오미경 | Plant fertilization promoter that promote pollination of self-incompatibility fruit |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0456318A2 (en) * | 1990-05-11 | 1991-11-13 | Koninklijke Philips Electronics N.V. | CMOS process utilizing disposable silicon nitride spacers for making lightly doped drain transistors |
| JPH04152535A (en) * | 1990-10-16 | 1992-05-26 | Sanyo Electric Co Ltd | Semiconductor device |
| EP0506287A1 (en) * | 1991-03-27 | 1992-09-30 | AT&T Corp. | Method of fabricating semiconductor devices and integrated circuits using sidewall spacer technology |
| US5274261A (en) * | 1990-07-31 | 1993-12-28 | Texas Instruments Incorporated | Integrated circuit degradation resistant structure |
| US5654212A (en) * | 1995-06-30 | 1997-08-05 | Winbond Electronics Corp. | Method for making a variable length LDD spacer structure |
| US5663586A (en) * | 1994-11-07 | 1997-09-02 | United Microelectronics Corporation | Fet device with double spacer |
| US5920783A (en) * | 1998-02-07 | 1999-07-06 | United Microelectronics Corp. | Method of fabricating a self-aligned silicide MOSFET |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0715938B2 (en) * | 1985-05-23 | 1995-02-22 | 日本電信電話株式会社 | Semiconductor device and manufacturing method thereof |
| JP3413823B2 (en) * | 1996-03-07 | 2003-06-09 | 日本電気株式会社 | Semiconductor device and manufacturing method thereof |
| JPH09298297A (en) * | 1996-04-30 | 1997-11-18 | Ricoh Co Ltd | Semiconductor device and manufacture thereof |
| JP2950408B2 (en) * | 1996-07-11 | 1999-09-20 | 日本電気株式会社 | Semiconductor device and manufacturing method thereof |
| JPH1065151A (en) * | 1996-08-14 | 1998-03-06 | Sony Corp | Semiconductor device and its manufacturing method |
| JPH10303141A (en) * | 1997-04-28 | 1998-11-13 | Sony Corp | Semiconductor device and its manufacture |
| JP3502750B2 (en) * | 1997-09-10 | 2004-03-02 | 株式会社ルネサステクノロジ | Semiconductor integrated circuit device and method of manufacturing the same |
-
2000
- 2000-10-16 GB GB0025340A patent/GB2362029A/en not_active Withdrawn
- 2000-10-26 KR KR1020000063187A patent/KR20010051263A/en not_active Application Discontinuation
- 2000-10-27 JP JP2000328522A patent/JP2001177090A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0456318A2 (en) * | 1990-05-11 | 1991-11-13 | Koninklijke Philips Electronics N.V. | CMOS process utilizing disposable silicon nitride spacers for making lightly doped drain transistors |
| US5274261A (en) * | 1990-07-31 | 1993-12-28 | Texas Instruments Incorporated | Integrated circuit degradation resistant structure |
| JPH04152535A (en) * | 1990-10-16 | 1992-05-26 | Sanyo Electric Co Ltd | Semiconductor device |
| EP0506287A1 (en) * | 1991-03-27 | 1992-09-30 | AT&T Corp. | Method of fabricating semiconductor devices and integrated circuits using sidewall spacer technology |
| US5663586A (en) * | 1994-11-07 | 1997-09-02 | United Microelectronics Corporation | Fet device with double spacer |
| US5654212A (en) * | 1995-06-30 | 1997-08-05 | Winbond Electronics Corp. | Method for making a variable length LDD spacer structure |
| US5920783A (en) * | 1998-02-07 | 1999-07-06 | United Microelectronics Corp. | Method of fabricating a self-aligned silicide MOSFET |
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2840453A1 (en) * | 2002-06-04 | 2003-12-05 | St Microelectronics Sa | METHOD FOR MANUFACTURING A MOS TRANSISTOR OF REDUCED GRID LENGTH, AND INTEGRATED CIRCUIT COMPRISING SUCH A TRANSISTOR |
| EP1369909A1 (en) * | 2002-06-04 | 2003-12-10 | STMicroelectronics S.A. | Method of fabricating a MOS transistor with reduced gate length and integrated circuit comprising such transistor |
| US6806156B2 (en) | 2002-06-04 | 2004-10-19 | Stmicroelectronics S.A. | Process for fabricating a MOS transistor of short gate length and integrated circuit comprising such a transistor |
| EP2876677A1 (en) * | 2013-11-25 | 2015-05-27 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Method for forming spacers of a transistor gate |
| FR3013895A1 (en) * | 2013-11-25 | 2015-05-29 | Commissariat Energie Atomique | METHOD FOR FORMING SPACERS OF A GRID OF A TRANSISTOR |
| US9437418B2 (en) | 2013-11-25 | 2016-09-06 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Method for forming spacers for a transistor gate |
| US9502418B2 (en) | 2014-10-02 | 2016-11-22 | International Business Machines Corporation | Semiconductor devices with sidewall spacers of equal thickness |
| US9576961B2 (en) | 2014-10-02 | 2017-02-21 | International Business Machines Corporation | Semiconductor devices with sidewall spacers of equal thickness |
| US9887198B2 (en) | 2014-10-02 | 2018-02-06 | International Business Machines Corporation | Semiconductor devices with sidewall spacers of equal thickness |
| US9905479B2 (en) | 2014-10-02 | 2018-02-27 | International Business Machines Corporation | Semiconductor devices with sidewall spacers of equal thickness |
| US10580704B2 (en) | 2014-10-02 | 2020-03-03 | International Business Machines Corporation | Semiconductor devices with sidewall spacers of equal thickness |
| US10622259B2 (en) | 2014-10-02 | 2020-04-14 | International Business Machines Corporation | Semiconductor devices with sidewall spacers of equal thickness |
| CN107689329A (en) * | 2016-08-03 | 2018-02-13 | 中芯国际集成电路制造(上海)有限公司 | Fin formula field effect transistor and its manufacture method |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20010051263A (en) | 2001-06-25 |
| JP2001177090A (en) | 2001-06-29 |
| GB0025340D0 (en) | 2000-11-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6716689B2 (en) | MOS transistor having a T-shaped gate electrode and method for fabricating the same | |
| US6812111B2 (en) | Methods for fabricating MOS transistors with notched gate electrodes | |
| US6797579B2 (en) | Semiconductor device having trench isolation structure and method of fabricating the same | |
| US6586311B2 (en) | Salicide block for silicon-on-insulator (SOI) applications | |
| JP3607431B2 (en) | Semiconductor device and manufacturing method thereof | |
| KR100498476B1 (en) | MOSFET having recessed channel and fabricating method thereof | |
| US6093590A (en) | Method of fabricating transistor having a metal gate and a gate dielectric layer with a high dielectric constant | |
| US6869839B2 (en) | Method of fabricating a semiconductor device having an L-shaped spacer | |
| TWI283481B (en) | BiCMOS integration scheme with raised extrinsic base | |
| US20070170511A1 (en) | Method for fabricating a recessed-gate mos transistor device | |
| US6197648B1 (en) | Manufacturing method of MOSFET having salicide structure | |
| US20060276001A1 (en) | Method for manufacturing a semiconductor device having a STI structure | |
| US6352897B1 (en) | Method of improving edge recess problem of shallow trench isolation | |
| US6847086B2 (en) | Semiconductor device and method of forming the same | |
| US6107140A (en) | Method of patterning gate electrode conductor with ultra-thin gate oxide | |
| GB2362029A (en) | Multi-layer structure for MOSFET Spacers | |
| US6524938B1 (en) | Method for gate formation with improved spacer profile control | |
| US6884669B2 (en) | Hatted polysilicon gate structure for improving salicide performance and method of forming the same | |
| US6306741B1 (en) | Method of patterning gate electrodes with high K gate dielectrics | |
| JP3529220B2 (en) | Semiconductor device and manufacturing method thereof | |
| JPH07273330A (en) | Semiconductor device and its manufacture | |
| JPH10270645A (en) | Semiconductor integrated circuit device and its manufacture | |
| US6303497B1 (en) | Method of fabricating a contact window | |
| JPH06151842A (en) | Semiconductor device and its manufacture | |
| KR100564432B1 (en) | Method for manufacturing Transistor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |