GB2359662A - A DRAM cell semiconductor device - Google Patents

A DRAM cell semiconductor device Download PDF

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Publication number
GB2359662A
GB2359662A GB0031525A GB0031525A GB2359662A GB 2359662 A GB2359662 A GB 2359662A GB 0031525 A GB0031525 A GB 0031525A GB 0031525 A GB0031525 A GB 0031525A GB 2359662 A GB2359662 A GB 2359662A
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gate electrode
impurity
region
spacer
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GB2359662B (en
GB0031525D0 (en
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Won-Suk Yang
Ki-Nam Kim
Chang-Hyun Cho
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823864—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

A DRAM cell semiconductor device comprises a first NMOS transistor (fig 11A) formed in a cell array region of a semiconductor device 100, and a second NMOS transistor (fig 11B) and a PMOS transistor (fig 11C) formed in a peripheral region of the semiconductor substrate. The first NMOS transistor has a gate electrode with single sidewall spacers, and the second NMOS transistor and the PMOS transistor each have double sidewall spacers. The second NMOS transistor has an LDD structure and the PMOS transistor has a double LDD structure. An interlayer insulating layer 120 covers the transistors and has a contact hole which exposes a source/drain region 108a of the first NMOS transistor. The double sidewall spacers suppress a short channel effect, prevent current leakage and reduce sheet resistance. An insulating layer from which sidewall spacers are formed serves as an etching stopper during formation of the contact hole and also serves as a barrier layer during silicidation of regions 118.

Description

2359662 METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE The present
invention relates to a semiconductor device and a method for the fabrication thereof, and more particularly to a method for fabricating a MOS transistor having gate double sidewall spacers.
DRAM cell device is generally divided into a cell array region and a peripheral logic region. The cell array region includes a plurality of memory cells in matrix type and the peripheral region includes a circuit to operate the memory cells.
Transistors are to be formed on the cell array region and peripheral. region respectively to their optimal characteristics since the transistors need different function according to their roles in the device. For example, the transistor in the cell array region has a single sourceldrain region of low concentration impurities diffusion region and the transistor in the peripheral region has a source/drain of LDD(Iightly doped drain) structure. The transistor in the cell array region has gate single spacers and the transistor in the peripheral region has gate double spacers.
Figs. IA to 1 C are cross-sectional views ofMOS transistors formed by a conventional method. Fig.1A schematically shows a first NMOS transistor of the cell array region. Referring to Fig. 1, the NMOS transistor family includes a gate electrode 12 formed on a semiconductor substrate 10, gate spacers 14 with a thickness of about 700A to 800A aligned on lateral side ofthe gate electrode 12, and a low concentration n-type impurity diffusion region 16a with a predetermined depth in the semiconductor substrate outwardly disposed from the gate spacers 14.
Figs.1B and IC schematically show a second NMOS transistor and a PMOS 1 transistor respectively formed on the peripheral region. lle second NMOS transistor family includes the gate electrode 12, the gate spacers 14 with a thickness of about 700A to 800A aligned on lateral side of the gate electrode 12, a low concentration n- type impurity diffusion region 15a with a predetermined depth in the semiconductor substrate 10 downwardly disposed from lateral edge of the gate spacers 14, and a high concentration n type impurity region 16b with a predetermined depth in the semiconductor substrate 10 disposed outwardly from lateral edge of the gate spacers 14. Namely, the second NMOS transistor has so called WD(lightly doped drain) structure.
Referring to Fig. 1 C, the PMOS transistor family includes the gate electrode 12, the gate spacers 14 with a thickness of about 700A to 800A aligned on lateral side of the gate electrode 12, a low concentration n-type or p-type impurity diffusion region 1 5b with a predetermined depth in the semiconductor substrate 10 downwardly disposed from lateral edge of the gate spacers 14, and a high concentration p-type impurity region 16c with a predetermined depth in the semiconductor substrate 10 disposed outwardly from lateral edge ofthe gate spacers 14. Namely, the PMOS transistor has so called LM(lightly doped drain) structure.
The n-type impurity includes P(phosphorous), As(arsenic), or the like. As is well known, arsenic impurity has greater molecular weight than phosphorous impurity and thereby causing substrate damage and current leakage. On the other hand, phosphorous has a greater diffusion rate than arsenic and thereby causing a short channel effect of the transistor. Therefore, phosphorous is generally used for the transistor formation in the cell array region for clear on/off operation and improved refresh time thereof In the peripheral region, for long channel transistor, phosphorous is generally used and for short channel, arsenic is generally used despite leakage loss.
As described previously, phosphorous ion has a greater diffusion rate, which increases short channel effect. To address problems with phosphorous ion and to obtain maximum effective channel length, the NMOS transistor in the cell array region is formed by the following process sequence. After a gate spacer is formed on the lateral sidewall of the gate, an impurity ions implanting Process is performed using the gate and gate spacer as a mask to form n-type impurity diffusion region and thereby maximum effective channel length can be obtained. Herein, it is required of heat treatment to drive out n-type impurity into the semiconductor substrate both outside of the gate electrode. It is very difficult, however, to diffuse out n-type impurity with a desired depth within the semiconductor substrate. Also. the impurity in the peripheral region simultaneously diffuses out and the effective channel length ofthe transistor thereofis reduced,and thereby causing device fail. Particularly, p-type impurity diffusion region ofthe PMOS in the peripheral region is formed by implanting boron(B) which has a greater diffusion rate. As a result, the PMOS is greatly affected by the reduction of the effective channel length.
To address the effect ofthe reduced effective channel length in the peripheral region, n-type low concentration impurity diffusion region can be replaced by n-type low concentration impurity diffusion region as shown in Fig. 1 C. By doing this, the problem of reduction of the effective channel length encountered in the p-type diffusion region can be prevented. As can be seen in Fig. 1 C, high concentration p-type impurity diffusion region is overlapped with low concentration n-type impurity diffusion region. However, the formation of such diffusion region configuration requires very careful controlling over the thickness of gate spacer and annealing temperature. Also, diffusion of high concentration p-type impurity makes impurity in LM region maintain high concentration, making it difficult to prevent hot carrier effect.
lie present invention was made in view ofthe above problem, and it is therefore an obj ect ofthe invention to provide a MOS transistor with an improved sourceldrain structural configuration and a method for fabricating thereof which can prevent short channel effect and hot carrier effect and can avoid reduction of effective channel length.
The present invention provides a double LDD structure ofa first lightly doped region of first type, a second lightly doped region of second type and a third heavily doped region 3 of second type. Such a double LDD structure in accordance with the present invention is formed by first implanting a low concentration of first type impurity into a semiconductor substrate using a gate as a mask. Second implantation of a low concentration of second type impurity is implemented after formation of first gate spacers on lateral sides of the gate.
After second implantation, second gate spacers are formed on the first gate spacers. After that third implantation of a high concentration of second type impurity is implemented using the double gate spacers as a mask. Implanted impurities are then diffused out by heat treatment and thereby to complete LDD structure.
In accordance with one aspect of the present invention, the method for fabricating a MOS transistor includes the steps of forming a device isolation region on a semiconductor substrate having a cell array region and a peripheral circuit region; forniing a furst gate on the cell array region and a second and a third gates on the peripheral circuit region, respectively; using the second and third gates as a mask and implanting first impurity ions' of low concentration into the semiconductor substrate adjacent to the second and third gates to form a first impurity diffusion layer of a first conductivity type, respectively; forming first gate spacers on lateral sides of the gates, respectively; using the first gate and first spacers thereof as a mask and implanting second impurity ions of low concentration into the semiconductor substrate adjacent to the first gate and spacers thereof to form a second impurity diffusion layer of a first conductivity type; using the third gate and spacers thereof as a mask and implanting third impurity ions of low concentration into the semiconductor substrate adjacent to the third gate and spacers thereof to form a third impurity diffusion layer of a second conductivity type; forming an insulating layer over a resulting semiconductor topology; etching the insulating layer at the peripheral region and forming second spacers on first spacers of the second and third gates respectively; using the second gate and first and second spacers as a mask thereof and implanting fourth impurity ions of high concentration into the semiconductor substrate adjacent to the second gate and second spacers thereofto form a fourth impurity diffusion of a first conductivity type; and using the third gate and first and second spacers thereof as a mask and implanting fifth impurity ions 4 of high concentration into the semiconductor substrate adjacent to the third gate and second spacers thereof to form a fifth impurity diffusion of a second conductivity type.
In accordancewith another aspect ofthe present invention, themethod forfabricating a MOS transistor includes the steps of. forming a gate electrode over a semiconductor substrate; using the gate electrode as a mask and implanting first impurity ions of low concentration of a first conductivity type to form a first impurity diffusion layer; forming first spacers on lateral sides ofthe gate; using the gate and first spacers thereof as a mask and implanting second impurity ions oflow concentration of a second conductivity type to form a second impurity diffusion layer, forming a second spacers on the first spacers of the gate; using the second and first spacers as a mask and implanting third irnpurity ions of high concentration of a second conductivity type to form a third impurity diffusion layer; and annealing and diffusing the hnpurity diffusion layers to overlap the first diffusion layer with the second diffusion layer.
7Iese and other features, aspects, and advantages of the present invention will become better understood with regard to the following description, appended claims, and accompanying drawings where:
Figs.1A to IC illustrate cross-sectionaI views of completed MOS transistor configurations in accordance with conventional method; Figs.2A to 2C illustrate cross-sectional views of a semiconductor substrate having a gate electrode wherein low concentration of n-type impurity implantation is carried out only in the peripheral region, i.e., Fig.2B and Fig.2C in accordance with the present invention; Figs.3A to 3C respectively illustrate a process step subsequent to that shown in Figs.2A to 2C wherein first gate spacers are formed on sidewalls of the gate electrode; Figs.4A to 4C respectively illustrate a process step subsequent to that shown in Figs.3A to 3C wherein low concentration ofn-type impurity lantation is carried out only IMP in the cell array region, i.e., Fig.4A using the first spacers and gate electrode as a mask; Figs.SA to SC respectively illustrate. a process step subsequent to that shown in Figs.4A to 4C wherein low concentration ofp-type impurity implantation is carried out in the peripheral region; Figs.6A to 6C respectively illustrate a process step subsequent to that shown in Figs.5A to 5C wherein an insulating layer for second spacers is formed; Figs.7A to 7C respectively illustrate a process step subsequent to that shown in Figs.6A to 6C wherein etch back is carried out only in the peripheral region and thereby to form second spacers, on sidewalls of the first spacers in the peripheral region; Figs.8A to 8C respectively illustrate a process step subsequent to that shown in Figs.7A to 7C wherein high concentration ofn-type impurity implantation is carried out only in the peripheral region; Figs.9A to 9C respectively illustrate a process step subsequent to that shown in Figs.8A to 8C wherein high concentration ofp-type impurity implantation is carried out only in Fig.9C for PMOS sistor formation in the peripheral region; Figs. I OA to I OC respectively illustrate a process step subsequent to that shown in Figs.9A to 9C wherein silicidation process is carried out to form a silicide layer in the peripheral region; and Figs.1 IA to 1 1Crespectively illustrate a process step subsequent to that shown in Figs.] OA to 1 OC wherein contact hole is formed in the cell arTay region(Fig. 1A).
Now in keeping with the objects of the invention, the method for fabricating a MOSFET is covered in detail with reference to accompanying drawings. The present invention is related to a MOS transistor with double LM structure, especially forming a PMOS with double LM structure in the peripheral region while forming NMOS with single LDD structure in the cell array region. The double LDD structure of PMOS in the peripheral region can suppress short channel effect and hot carrier effect.
6 Figs.2A to 1 IA illustrate, at selected stages of fabrication, the cross- sections of NMOS in the cell array region in accordance with an embodiment of the present invention, Figs.2B to 1 1B illustrate, at selected stages of fabrication, the cross-sections of NMOS in the peripheral region in accordance with an embodiment of the present invention, and Figs.2C to 11 C illustrate, at selected stages of fabrication, the cross- sections ofPMOS in the peripheral region in accordance with an embodiment of the present invention.
Referring to Figs.2A to 2C, gate electrodes are simultaneously formed in the cell array region(Fig.2A) and peripheral region(Fig.2B and FigIC), i. e., first gate electrode 102a, second gate electrode 102b, and third gate electrode 102c. Before formation of the gate electrodes 102a-102c over a semiconductor substrate 100, a device isolation layer(not shown) is formed to define cell array and peripheral region and gate oxide layer(not shown) is formed over the semiconductor substrate. The gate electrodes 102a, 102b, and 102c are conventionally formed by depositing polysilicon layer and patterning thereof Since cell array region is more susceptible to the design rule than peripheral region, the gate width of the cell array region is narrower than that ofthe peripheral region(compare the width of the gate electrode in Fig.2A with Figs.2B and 2C).
A first photoresist layer is spin coated over the resulting semiconductor substrate and patterned into a desired configuration, i.e., first photoresist pattern 103 exposing the peripheral region while covering the cell array.region. Low concentration n-type impurity ions are implanted into the semiconductor substrate 100 of the peripheral region using the gate electrodes 102b and 102c as a mask and thereby forming first impurity diffusion layers 104b and 104c of n-type, respectively. The implantation of n-type impurity ions is carried out with arsenic(As) at an energy of about 50keV, with a dose of about SE12 ions/c&.
Formation of the first spacers is next addressed and shown schematically in Figs.3A to 3 C. After removing the first photoresist pattern 103, a first insulating layer is deposited over the entire resulting semiconductor topology. For example, a silicon nitride layer may be deposited. The deposited insulating layer is then anisotropically etched to form first gate spacers 106a, 106b, and 106c on sidewalls of the first, second, and third gate electrodes, 7 respectively with a thickness of about Mok The next process sequence is formation of the low concentration n-type impurity diffusion layer in the cell array region. Referring to Figs.4A to 4C, a second photoresist layer is spin coated over the entire resulting semiconductor topology and patterned into desired configuration, i.e., second photoresist pattern 107 exposing the cell array region while covering the peripheral region. Low concentration n-type impurity ions are implanted into the semiconductor substrate 100 of cell array region using the gate electrode 102a and first spacers 106a as a mask and thereby forming second impurity diffusion layer 108a of n type in the cell array region. Aforementioned implantation is carried out with phosphorous(P) at an energy of about 30keV, with a dose of about SE12 ionslcx&.
After removing the second photoresist pattem 107, a third photoresist pattern 109 is formed.to expose only the third gate electrode 102c in the peripheral region where PMOS trarisistor is to be forTned, as shown in Figs.5A to SC. First gate electrode 102a and second gate electrode 102b are covered by the third photoresist pattern 109. Low concentration p type impurity ions are implanted into the semiconductor substrate 100 in the peripheral region using the third gate electrode 102c and first spacers 106c as a mask and thereby forming third impurity diffusion layer 11 Oc of p-type in the cell array region. The p-type impurity may include boron(B) or BF3 and these impurity ions are implanted at an energy of about 20keV, with a dose of about 1E13 ions/c&.
Referring to Figs.6A to 6C, after removing the third photoresist pattern 109, an insulating layer 112, for example a silicon nitride layer, is deposited over the resulting semiconductor topology. As will be described later, the insulating layer 112 serves as a barrier layer against silicidation in the cell array region and serves as second gate spacers in the peripheral region.
A fourth photoresist layer is deposited and patterned into desired configuration, i.e., fourth photoresist pattern 111 exposing the insulating layer 112 in the peripheral region while covering the insulating layer 112 in the cell array region. Using the fourth photoresist pattern 111 as a mask, the insulating layer 112 is anisotropically etched to respectively form 8 second spacers 1 12b and 1 12c on the first spacers 106b and 106c of in the second and third gate electrode with a thickness of about 400Aas shown in Figs.7A to 7C. As a result, double spacer configuration is formed in the peripheral region. Herein, it is noted that since the insulating layer 112 in the cell array region is covered by the fourth photoresist pattern 111, it is not etched. The remaining insulating layer 1 12a in the cell array region serves as a barrier layeragainst silicidation.
After removing the fourth photoresist pattern 111, a fifth photoresist pattern 113 is formed to expose only the second gate electrode 102b and its spacers 106b and 112b in the peripheral region while covering the first and third gate electrodes and their spacers as shown in Figs.tA to 8C. Using the fifth photoresist pattern 115, gate electrode 102b, and second and third spacers 106b and 11 2b as a mask, high concentration ntype impurity ions are implanted into the semiconductor substrate 100 to form fifth impurity diffusion layer 1 14c of n-type. The implantation of n-type impurity ions is carried out with arsenic(As) at an energy of about 20keV, with a dose of about SEI S ions/cm.
After removing the fifth photoresist pattern 113, a sixth photoresist pattern 115 is formed to expose the region where PMOS is to be formed, i. e., expose the third gate electrode 102c and spacers 1 12c. Using the sixth photoresist pattern 115, the third gate electrode 102c and spacers 106c and 112c thereof as a mask, high concentration p-type hnpurity ions are implanted into the semiconductor substrate 100 to form fifth impurity diffusion layer 11 6c of p-type in the cell array region. The p-type impurity may include boron(I3) or BF3and these impurity ions are implanted at an energy of about 20keV, with a dose of about SEI 5 ions/cm. Consequently, PMOS transistor is formed in the peripheral region to the desired configuration with the first impurity diffusion layer 104c of low concentration n-type impurity, the third impurity diffusion layer 11 Oc of low concentration p-type impurity, and the fifth impurity diffusion layer 116c of high concentration p-type impurity.
Ile next process sequence is the formation of the silicide layer and schematically shown in Figs. 1 OA to 1 OC. The silicide layer formed on sourceldrain region and on the gate 9 electrode in the peripheral region can decrease the consumption voltage of the DRAM device and increase the operation speed thereof Transition metal such as Ti, Ta, Co, or Mo is deposited over the resulting semiconductor topology. After depositing the transition metal, annealing process is carried out to form silicide layer. As is well known, silicide layer is formed by the reaction between the silicon and the transition metal. Therefore, as can be seen in Figs. 1 OB and 1 OC, silicide layer 118 is formed only on the exposed silicon and polysilicon, i.e., on exposed semiconductor substrate and exposed polysilicon gate in the peripheral region. Herein it is noted that the insulating layer 1 12a covers the semiconductor substrate and first gate electrode in the cell array region. The presence ofthe insulating layer 1 12a prevents silicidation process in the cell array region. Otherwise, current leakage ofthe transistor in the cell array region can be increased.
During annealing process for silicidation, impurity ions of hereinbefore mentioned impurity diffusion layers are diffused to form impurity regions, respectively. More specifically referring to Figs. 1 OA to 1 OC, the transistor formed on the cell array region, i.e., i s NMOS transistor(see Fig. 1 OA), includes the first gate electrode 102a, first spacers 106a, and source/drain region 108a(i. - e., second impurity region 108a) of low concentration n-type impurity. The transistor formed on the peripheral.region, i.e., NMOS transistor(see Fig. 1 OB) includes the second gate electrode 102b, first and second spacers 106b and 112b, and source/drain regions 104b and 1 14b. As can be seen, the source/drains are composed of first impurity region 104b of low concentration n-type irnpurity aligned below the first and second spacers 106b and 1 12b and fourth impurity region 1 14b ofhigh concentration n-type impurity aligned outwardly from the lateral edges ofthe second spacers 1 12b. The transistor formed on the peripheral region, i.e., PMOS transistor(see Fig. 1 OC) includes the third gate electrode 102c, first and second spacers 106c and 1 12c, and source/drain regions 104c, 11 Oc, and 11 6c. As can be seen in Fig. 1 OC, the sourceldrain regions are composed of first impurity region 104c of low concentration n-type impurity aligned below the first spacers 106c, third impurity region 11 Oc of low concentration p-type impurity aligned below the second spacers 1 12c, and fifili impurity region 11 6c ofhigh concentration p-type impurity aligned outwardly from the lateral edges of the second spacers 112c.
In the PMOS transistor of the peripheral region, heat burden applied to the semiconductor device during subsequent layer formation makes the first impurity region 104c ofn-type overlap with the third impurity region 11 Oc and thereby transforming the first 5 impurity region 104c of n-type to p-type.
After formation ofthe silicide layer, the transition layer which does not react with the silicon or polysilicon is removed selectively. As a result, sheet resistance ofthe source/drain region can be reduced to increase the operation speed.
Referring to Figs. 11 A to 11 C, an interlayer insulating layer 120 is deposited over the entire semiconductor substrate. A seventh photoresist layer is deposited over the interlayer insulating layer and patterned into desired configuration. Using the patterned seventh photoresist layer, desired portion of the interlayer insulating layer 120 is anisotropically etched to form a contact hole which exposes the source/drain region ofthe NMOS in the cell array region, as shown in Fig. 1 IA. The interlayer insulating layer 120 is selectively etched(about five times) with respect to insulating layer 112a and thereby forming the contact hole in a self aligned manner.
According to the present invention, NMOS transistor in the cell array region includes gate electrode, single spacer, and source/drain region of low concentration n-type impurity region. Ile NMOS Cansistor in the peripheral region includes gate electrode, double spacers, and LDD source/drain region oflow concentration n-type impurity region and high concentration n-type impurity region. The PMOS transistor in the peripheral region includes gate electrode, double spacers, and double LDD source/drain structure of low concentration p-type impurity region, low concentration n-type impurity region, and high concentration p-type impurity region. The double LDD source/drain structure ofthe PMOS transistor can prevent short channel effect and reduce hot carrier effect advantageously. Furthermore, the remainder of the insulating layer for second spacers serves the dual purposes of silicidation barrier layer and etching stopping layer and thereby simplifying manufacturing process.
It will be recognized by those skilled in the art that the innovative concepts disclosed 11 in the present application can be applied in a wide variety of contexts. Moreover, the preferred implementation can be Modified in a tremendous variety of ways. Accordingly, it should be understood that embodiments and variations suggested below and above are merely illustrative. These examples may help to show some of the scope of the inventive concepts, but these examples do not nearly exhaust the full scope of variation in the disclosed novel concepts.
12 13

Claims (6)

  1. CLAIMS:
    A DRAM cell semiconductor device comprising:
    a first NMOS transistor formed in a cell array on a semiconductor substrate, a second NMOS trarisistor formed on a peripheral circuit region of said substrate, and a PMOS transistor formed on a peripheral circuit region of said substrate; said first NMOS transistor comprising at least one first gate electrode, covered at least partially by a first and second spacer; a first source/drain region comprising a first gate electrode impurity region of a first impurity type of low concentration; and an interlayer insulating layer partially covering said at least one first gate electrode and comprising a contact hole exposing at least a part of said sourceldrain region and said first spacer; said second NMOS transistor comprising a second gate electrode, at least partially covered by a first and second spacer.of said second gate electrode; and a second sourceldrain region; said PMOS transistor comprising a third gate electrode, at least partially covered by a first and second spacer of said third gate electrode; and a third source/drain region; wherein said interlayer insulating layer substantially covers said second NMOS transistor and PMOS t-ansistors.
  2. 2. A DRAM cell semiconductor device according to claim 12, wherein: the said at least one first gate electrode is covered laterally by a first spacer of said at least one first gate electrode, the remaining exposed at least one fug gate electrode being covered by a second spa= of said at least one first gate electrode and said first spacer of said at 1 o ' ne first gate electrode being partially covered by said second spacer of said at least one first gate electrode; 1 14
  3. 3. A DRAM cell semiconductor device according to claim 12, where in the said second gate electrode is covered laterally by a first spacer of said second gate electrode, and said first spacer of said second gate electrode is in turn covered laterally by a second spa= second gate electrode; and said second sourceldrain region comprises a first impurity region of said second gate electrode of low concentration impurity of a first type under the surflice of the substrate beneath the said first and second spacers, and a second impurity region of said second gate electrode of high concentration impurity of said first t" under the surface of 'the substrate, laterally outward from said first impurity region. of said seconfd gate elee under the surface of the substrate.
  4. 4. A DRAM cell semicon ductor device according to claim 12, wh'erein: the said third gate electrode is covered laterally by a first spacer of said third gate electrode, and said first gate el"ode spacer being in turn covered laterally by a s"nd. spacer of said third gate electrode; and said third source/drain region comprises a first impurity region of said third gate electrode of low concentration impurity of a first type under the surface of the substrate aligned with the first spacers of said third gate electrode, a second impurity region of said third gate electrode of low concentration impurity of a second type under the surface of the substrate aligned with the said second spacers, and a third impurity region of said third gate electrode of high concentration impurity of said second type under the surface of the substrate, laterally outward from said second impuirity region of said third gate electrode.
  5. 5. A DRAM cell semiconductor device according to any of the preceeding claims, wherein the first impurity type is a n-type impurity and the second impurity is a P-type impurity.
  6. 6. A semiconductor device substantially as hereinbefore described with reference to any one of Figures 2A to 11 C of the accompanying drawings.
    6. The DRAM cell semiconductor device according to any of the preceeding claims, wherein there is a silicide layer on contacting surfaces between said second and third gate electrodes and the interlayer insulating layer, said second impurity regions of said second gate electrode and the interlayer insulating layer, and said third impurity regions of said third gate electrode and the interlayer insulating layer.
    CLAIMS:
    Amendments to the claims have been filed as follows (0 A DRAM cell semiconductor device comprising:
    a first NMOS transistor formed in a cell array region on a semiconductor substrate, a second NMOS transistor formed on a peripheral circuit region of said substrate, and a PMOS transistor formed on a peripheral circuit region of said substrate; said first NMOS transistor comprising a first gate electrode, partially covered by a first spacer; a first source/drain region comprising an impurity region of said first NMOS transistor of a first gate electrode impurity region of a first impurity type of low concentration; and an interlayer insulating layer partially covering said first gate electrode and comprising a contact hole exposing a part of said first source/drain region and said first spacer; said second NMOS transistor comprising a second gate electrode, partially covered by a first and second spacer of said second gate electrode; a second source/drain region; said second source/drain region comprising a first impurity region of said second NMOS transistor of low concentration impurity of a first type and a second impurity region of said second NMOS transistor of high concentration impurity of said first type; said PMOS transistor comprising a third gate electrode, partially covered by a first and second spacer of said third gate electrode; a third source/drain region; said third source/drain region comprising a first impurity region of said PMOS transistor of low concentration impurity of a second type; a second impurity region of said PMOS transistor of low concentration impurity of a second type,., and 0 a third impurity region of said PMOS transistor of high concentration impurity of said second type; wherein said interlayer insulating layer substantially covers said second NMOS transistor and PMOS transistor.
    2. A DRAM cell semiconductor device according to claim 1, wherein: the said second gate electrode is covered laterally by the first spacer of said second gat electrode, and said first spacer of said second gate electrode is in turn covered laterally by the second spacer of said second gate electrode; and the first impurity region of said second NMOS transistor is disposed under the surface of the substrate beneath the said first and second spacers, and the second impurity region of said second NMOS transistor is disposed under the surface of the substrate, laterally outward from said first impurity region of said second NMOS transistor under the surface of the substrate.
    3. A DRAM cell semiconductor device according to Claims 1 or 2, wherein: the said third gate electrode is covered laterally by the first spacer of said third gate electrode, and said first gate electrode spacer being in turn covered laterally by the second spacer of said third gate electrode; and the first impurity region of the PMOS transistor is disposed under the surface of the substrate aligned with the first spacers of said third gate electrode, the second impurity region of said PMOS transistor is disposed under the surface of the substrate aligned with the said second spacers, and the third impurity region of said PMOS transistor is disposed under the surface of the substrate, laterally outward from said second impurity region of said PMOS transistor.
    4. A DRAM cell semiconductor device according to any of the preceding claims, wherein the first impurity type is a n-type impurity and the second impurity type is a p-type impurity.
    1 1 5. The DRAM cell semiconductor device according to claim 4 or 5, wherein there is a silicide layer on contacting surfaces between said second and third gate electrodes and the interlayer insulating layer, said second impurity regions of said second NMOS transistor and the interlayer insulating layer, and said third impurity regions of said PMOS transistor and the interlayer insulating layer.
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US5534449A (en) * 1995-07-17 1996-07-09 Micron Technology, Inc. Methods of forming complementary metal oxide semiconductor (CMOS) integrated circuitry
US5811329A (en) * 1996-06-03 1998-09-22 Micron Technology, Inc. Method of forming CMOS circuitry including patterning a layer of conductive material overlying field isolation oxide
WO1998044552A2 (en) * 1997-04-01 1998-10-08 Koninklijke Philips Electronics N.V. Method of manufacturing a non-volatile memory combining an eprom with a standard cmos process

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US5534449A (en) * 1995-07-17 1996-07-09 Micron Technology, Inc. Methods of forming complementary metal oxide semiconductor (CMOS) integrated circuitry
US5811329A (en) * 1996-06-03 1998-09-22 Micron Technology, Inc. Method of forming CMOS circuitry including patterning a layer of conductive material overlying field isolation oxide
WO1998044552A2 (en) * 1997-04-01 1998-10-08 Koninklijke Philips Electronics N.V. Method of manufacturing a non-volatile memory combining an eprom with a standard cmos process

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Publication number Priority date Publication date Assignee Title
DE10221884A1 (en) * 2002-05-16 2003-11-27 Infineon Technologies Ag Production of a layer arrangement comprises forming a laterally limited first layer sequence on a first surface region of a substrate and a second laterally limited second layer

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