GB2343332A - Adaptive filter structures - Google Patents

Abstract

An adaptive filter structure matches its response closely to the received signal pulse shape when there is a high level of co-channel or adjacent channel interference, and provides a less accurate match when there are low interference levels, to reduce the computational load and power consumption in, eg a portable phone receiver. A first adder provides a partial output providing a centre response. A second adder provides a tail response. For a full output in the presence of interference, the outputs of adders are combined. In the absence of interference the partial output from the first filter will suffice, enabling circuitry associated with the second adder to be inhibited, saving on power consumption. The power consumed by computation is determined by the number of gates required to carry out a computation and how often each gate switches. By altering the overall number of gate switches, power consumption is reduced.

Description

ADAPTIVE FILTER STRUCTURES The present invention relates to adaptive filter structures.

Modem radio receivers for digital information frequently contain an analogue and a digital part. The analogue part typically takes the signal from the antenna, amplifies it and downconverts it to a frequency suitable for digitisation. The analogue part will also contain some filtering, possibly at an intermediate frequency, which serves to provide a measure of receiver selectivity and also to attenuate frequencies which would be aliased by the sampling process associated with the digitisation.

Following the sampler and analogue to digital conversion (ADC), further digitally implemented filtering is usually applied. Almost invariably this is applied at complex baseband with one lowpass filter on the in-phase (I) channel and one on the quadrature (Q) channel. This will typically provide matched filtering to the pulse shape which was transmitted. If a pulse shape satisfying Nyquist 1 requirements is used then an ideal matched filter would also result in there being no interference between the received data symbols for a linear data modulation scheme (zero intersymbol interference).

Low intersymbol interference is important for conventional, that is, non spread spectrum, modulation in order to minimise the irreducible error floor. In a simple direct sequence spread spectrum system, low intersymbol interference (which in this case becomes inter-chip interference) is relatively unimportant because its effect is suppressed by the so called processing gain. However, in a code division multiple access (CDMA) system using orthogonal codes there may be a requirement to receive a weak wanted signal in the presence of one or more strong unwanted signals where the latter are spread using codes which are orthogonal to the codes used by the wanted signal. In this case it, again, is vital that the inter-chip interference should be very low.

The transmit pulse shape is also usually selected so that the ideal matched filter would provide very good, if not perfect, adjacent channel rejection. Thus, a filter which well approximated the ideal matched filter response would also have excellent stop band rejection. This will be important in the presence of one or more strong adjacent channel interferers.

In many types of system, in the absence of adjacent channel interference, near optimum performance can be obtained from a relatively poor approximation to the matched filter response. This poor approximation will also suffice for an orthogonal spread spectrum system when the total level of orthogonal interference to the wanted signal is relatively low. However, if there are one or more strong adjacent channel signals or, in an orthogonal spread spectrum system, if the total orthogonal interference to the wanted signal is relatively high, it will be important for the filter to be a good approximation to the matched filter response. Thus, depending on the interference environment, the accuracy of the matched filter response may need to be very good or a relatively poor accuracy may be adequate.

It is therefore an object of the present invention to provide an improved filter which can adapt in accordance with the presence of adjacent channel interference.

It is another object of the present invention to provide an improved filter which can adapt automatically.

In accordance with one aspect of the present invention, there is provided a method of reducing the power requirements of a receiver in accordance with interference from adjacent channels or orthogonal co-channels, the method comprising the steps of : a) determining the presence of adjacent channel or co-channel interference in an input signal, and b) filtering the input signal in accordance with the interference to provide an output signal.

Step b) may comprise applying a threshold to the input signal to determine a level of interference, the output signal being produced in accordance therewith.

The method may further comprise the step of producing at least one signal component, the output signal comprising said at least one signal component or a sum of said signal components. In one embodiment, the method further comprises the step of selecting the signal components for the output signal in accordance with the level of interference. In a preferred embodiment, the number of signal components produced is in accordance with the level of interference.

In accordance with another aspect of the present invention, there is provided a filter arrangement comprising at least two elements arranged to contribute to the filtration of a signal, each element performing a number of gate switches per second, and selection means arranged to selectively alter the contribution to the filtration of the signal from at least one of the elements to alter the number of gate switches per second.

The alteration of the number of gate switches per second may comprise a reduction in the number of gate switches per second.

The selection means may be arranged to selectively remove at least one of the elements arranged to contribute to the filtration of the signal.

It should be understood that the term"filter arrangement"can include one or more filters, where the elements can be a part of a filter or a complete filter, respectively.

A reduced computation filter is used when the levels of interfering signals are small enough to permit this. The interfering signals may be adjacent channel or orthogonal co-channel (for spread spectrum) signals. When the interfering signals are above a predetermined value, the filtering function must be improved to achieve the required wanted signal reception capability in the presence of the interfering signals. The aim of doing this to minimise the receiver filter power consumption and thereby, for example, improve the battery life of terminal equipment incorporating such filtering. Over the period of the battery life, the receiver is likely to encounter conditions under which the reduced computation filtering is adequate for a high proportion of the time.

It will be readily understood by a person skilled in the art that the power consumed by computation can be expressed in terms of the number of gates required to carry out the computation and how often each gate switches. The overall gate switches per second can be expressed as the average number of gate switches per second for all gates multiplied by the total number of gates. The overall number of gate switches per second is directly related to the current taken during the computation for complementary metal oxide semiconductors (CMOS) technology. Therefore, by reducing the computation, the power taken is also reduced.

In accordance with a further aspect of the present invention, there is provided a receiver having a filter arrangement as described above, the receiver further comprising interference determining means for determining the presence of adjacent channel or orthogonal co-channel interference, the selection means operating in accordance with the determination of the interference determining means.

In accordance with the present invention, there is also provided a mobile terminal having a receiver as described.

For a better understanding of the present invention, reference will now be made, by way of example only, to the accompanying drawings in which: Figure 1 illustrates the structure of a general finite impulse response (FIR) filter; Figure 2 illustrates a simplified FIR filter structure for symmetrical impulse response; Figure 3 illustrates an adaptive FIR filter in accordance with the present invention; Figure 4 illustrates automatic filter adaptation; Figure 5 illustrates an asymmetry filter; and Figure 6 illustrates a complex filter.

Digital low pass filters which implement approximate match filtered response are almost invariably implemented as finite impulse response (FIR) filters. A standard FIR structure 10 is shown in Figure 1. The filter 10 comprises a shift register 12 connected to input 14. The shift register 12 comprises nine elements, 12a, 12b, 12c, 12d, 12e, 12f, 12g, 12h, 12i, each element being connected to a respective multiplier 16a, 16b, 16c, 16d, 16e, 16f, 16g, 16h, 16i. Each multiplier 16a, 16b, 16c, 16d, 16e, 16f, 16g, 16h, 16i has a respective tap weight or coefficient a4, a 3, a. 2, a, aO, al, a2, a3, a4 as shown.

Respective outputs 18a, 18b, 18c, 18d, 18e, 18f, 18g, 18h, 18i from the multipliers 16a, 16b, 16c, 16d, 16e, 16f, 16g, 16h, 16i are passed to an adder 20 which provides an output 22. It will be appreciated that the shift register may contain a different number of elements to nine according to the particular application.

Since the requirement is frequently for a linear phase filter, the required impulse response is symmetrical in time. This means that in Figure 1, a, = a *.

The most computationally intensive operations in the filter are the multiplications. By using symmetry, it is possible to (almost) halve the number of multiplications required. This is shown in Figure 2.

In Figure 2, a shift register 30 is effectively split into two halves 32,34, but still has nine elements 30a, 30b, 30c, 30d, 30e, 30f, 30g, 30h, 30i. In this case, as the filter is symmetrical, that is, a, = a *, the outputs from the shift register 30 are grouped in pairs to form inputs to summing units 40,42,44,46.

As shown, outputs from element 30a and element 30i form the inputs to summing unit 40, outputs from element 30b and element 30h form the inputs to summing unit 42, outputs from element 30c and element 30g form the inputs to summing unit 44, and outputs from element 30d and element 30f form the inputs to summing unit 46. Outputs from summing units 40,42,44,46 are respectively passed to multipliers 50,52,54,56 where respective coefficients a4, a3, a2, a, are applied. The output from bit 30e passes directly to multiplier 58 where coefficient ao is applied. Outputs 60,62,64,66,68 from multipliers 50, 52,54,56,58 are passed to an adder 70 which provides output 72. It will be appreciated that for an even order filter, the number of multiplications is reduced by a factor exactly equal to two. This approach is well established in the prior art.

In accordance with the present invention, a filter 80 which can be used in the case where strong adjacent channel interference may or may not be present is shown in Figure 3. Components which have been previously described with reference to Figure 2 are numbered alike and no further explanation to their operation will be given.

When comparing Figure 3 to Figure 2, it will readily be seen that two separate overall adders 82,84 are used. One adder 82 provides the sum of terms multiplied by coefficients a 2, a l, aO, a, and a2 from multipliers 54,56,58 (where a i = a, as before) as output 86, and the other adder 84 provides the sum of terms multiplied by coefficients a, 4, a 3, a3 and a4 from multipliers 50,52 (again where a * = a,) as output 88. Thus, output 86 provides the centre impulse response and output 88 provides the tail response respectively of the filter 80.

Thus, the partial output 86 provides a truncated filter response. For a full output 90 from the filter 80, outputs 86 and 88 are added together in adder 92.

When there is little or no adjacent channel interference, the partial output 86 will suffice and all of the circuitry associated with adder 84 (apart from elements 30a, 30b, 30h, 30i in shift registers 32,34) can be inhibited, thus saving on power consumption. On the relatively rare occasions of significant adjacent channel interference, the additional circuitry associated with adder 84 can be enabled to provide the full response.

However, in order for filter 80 to be useful, it is necessary to provide a means for automatically inserting the extra filter tail response when needed and removing it when it is not needed. There may be many arrangements which make this possible. One such arrangement is shown in Figure 4.

In Figure 4, input I and Q signal components are assumed to have been adjusted to a fixed power level by the operation of automatic gain control (AGC). This is normal for this type of receiver and is necessary to ensure that the best use is made of the quantisation in the analogue-to-digital converter (ADC). The AGC will fix the level of the sum of the wanted signal and any additional co-channel and adjacent channel interferers. If, for example, the filter has unity gain in the passband and there is little or no adjacent channel interference, the level at the output of the filter will be close to the same as that at the input, apart from any attenuation of noise. However, if adjacent channel interference is present, even the simplified filter will attenuate this somewhat.

Thus, the power at the output of the filter will be lower than at the input under this condition. A certain power level at the output of the filter will correspond to the presence of adjacent channel interference at the maximum level which the simplified filter can acceptably attenuate. A threshold is set at this level and a comparison performed.

In more detail, the I and Q signal components are passed through respective partial filters 100,102 to provide respective first outputs 104,106.

Further outputs 108,110 from partial filters 100,102 pass through respective tail filters 112,114 as shown to provide outputs 116,118. Outputs 104 and 116 and 106 and 118 are summed in respective adders 120,122 to provide respective second outputs 124,126 as shown. The power of the signal is determined from outputs 104,118 (box 128) and is passed to one input of a comparator 130. The second input of the comparator 130 has a threshold value 132 applied to it. When the measured power (computed by the 1i12 operation (box 128) which denotes I2 + Q2) is lower than threshold value 132, an output signal 134 is generated and passed to latch 136. Latch 136 controls respective switch elements 138, 140 connected between outputs 104,124 and 118,126 respectively to provide respective output signals 142,144 for the I and Q signal elements as shown. Latch 136 is also connected to tail filter 114 and adder 122 of the Q signal element so that the tail filter 114 is enabled and the outputs incorporating this tail filter are used.

Instead of a simple truncation of the filter response, it may be better to use a different set of coefficients for the truncated filter from those used in the centre portion of the non-truncated filter. In this case, it would also be possible to switch the filter coefficients. Here, after switching over to the non-truncated filter, the measurements would be performed on this output. The automatic filter switching would still be effective.

The present invention is equally applicable to multiple truncations corresponding to more than two levels of filter complexity. In this case, the invention may relate to adaptation of the filter length according to variation in adjacent channel interference. However, it will be appreciated that other types of adaptation may also be implemented.

Analogue filtering prior to digitisation may introduce variations in amplitude and/or phase over the passband. By the term'passband'is meant any frequencies of nominally non-zero attenuation of the ideal matched filter response. If this is the case, it may be desirable to build compensation for these variations into the digital filtering. If the variations are only in amplitude and if these variations are symmetrical about the centre frequency of the filter (which is also aligned on the centre of the received signal) then this variation may be compensated by a trivial change in the FIR filter tap weights or coefficients.

However, if one, other or both of these conditions is not satisfied then significant additional complexity can arise in the digital filtering if full compensation is required.

Consider first the phase variations in the filter. In order to compensate for these, it becomes necessary for the FIR filters to have an asymmetrical impulse response. In this case, the reduced complexity architecture of Figure 2 cannot be used and it becomes necessary to revert to the structure of Figure 1.

It would be possible, however, to construct the response by a combination of the structure of Figure 2 and an'asymmetry filter'as shown in Figure 5.

Components which have been previously described with reference to Figure 2 are numbered alike and no further explanation to their operation will be given.

In Figure 5, input 14 is applied to an asymmetrical filter 150 and a symmetrical filter 152. Respective outputs 154,156 from filters 160,162 form inputs for an adder 160 which provides an output signal 162. Asymmetric filter 150 comprises the shift register 30 of Figure 2 where outputs from elements 30a, 30b, 30c, 30d, 30f, 30g, 30h, 30i are grouped in pairs to form inputs to subtraction units 170,172,174,176. As shown, outputs from element 30a and element 30i form the inputs to subtraction unit 170, outputs from element 30b and element 30h form the inputs to subtraction unit 172, outputs from element 30c and element 30g form the inputs to subtraction unit 174, and outputs from element 30d and element 30f form the inputs to subtraction unit 176. Outputs from subtraction units 170, 172, 174, 176 are respectively passed to multipliers 180, 182, 184, 186 where respective coefficients b4, b3, b2, b, are applied.

Outputs 190,192,194,196 from multipliers 180,182,184,186 are passed to an adder 198 which provides an output 154 for the asymmetrical filter 150.

Here, the coefficients b ; are given by the difference between the equivalent positive and negative indexed coefficients, that is, bi = aj-a j. This structure is marginally more complex than that of Figure 1, having the same number of multiplications but about twice as many additions. Note that the shift registers can be shared between the symmetrical and asymmetrical filter components. The reason for considering such a structure is that the asymmetric filter can be disabled whenever it is not necessary to compensate the phase response of the analogue filter.

Considering the orthogonal CDMA case, the asymmetry filter can be enabled whenever the despread wanted signal is weaker than the total cochannel composite signal by greater than a certain factor, determined according to the acceptable performance degradation. One possible structure would be similar to that of Figure 4, except that the thresholding of the power would be performed after despreading the wanted signal. It would, of course, be necessary to take account of any gain adjustments associated with adjacent channel interference.

Now consider the effect of analogue filter frequency asymmetry. In this case, in order to compensate this, a fully complex digital filter would be required. Such a structure is shown in Figure 6.

In Figure 6, a complex filter 200 is shown which comprises four filter elements 202,204,206,208. Each filter element 202,204,206,208 is a real FIR structure. As shown, filter elements 202,204 are connected to receive the I signal component and filter elements 206,208 to receive the Q signal component. Filter elements 202 and 208 comprise main filters for their respective signal components and filter elements 204 and 206 comprise cross filters for their respective signal components. Each filter element 202,204, 206, 208 provides respectively an output 212,214,216,218. As shown, outputs 212,216 form inputs to a first adder 220, and outputs 214,218 form inputs to a second adder 222. Outputs 224,226 from respective adders 220, 222 comprise the output I and Q signal components respectively.

The present invention can be applied here in exactly the same way as for the phase compensation. The two cross filters 204,206 can be enabled whenever the despread wanted signal is weaker than the total co-channel composite signal by greater than the a certain factor, which may be the same as that specified for the phase response although this is not necessarily the case.

Although the present invention has been described with reference to specific embodiments, it will readily be appreciated that this invention may also extend to any combination of any implementations of the filter adaptations for adjacent channel selectivity, compensation of the phase linearity of the analogue filter and compensation of frequency response asymmetry in the analogue filter.

It may be that in a combined usage, some of the operations are mutually exclusive. For example, it may be desired that the asymmetric filter compensating for the non linear phase response in the analogue filter to be implemented with limited precision arithmetic. This would be adequate to improve orthogonality of signals but would at the same time compromise the stopband attenuation of the filter. Thus, it may not be desirable to switch in the asymmetric filter component at the same time as strong adjacent channel signal have been detected. It is not likely that strong adjacent channel and strong orthogonal co-channel signals will be encountered at the same time as most deployment scenarios preclude this eventuality. Thus, the adaptive filter structure proposed in this invention confers additional advantages by allowing the inclusion of low complexity phase compensation structures only when this will not degrade adjacent channel performance in the presence of strong adjacent channel signals.

Claims (11)

CLAIMS:

1. A method of reducing the power requirements of a receiver in accordance with interference from adjacent channels or orthogonal co-channels, the method comprising the steps of : a) determining the presence of adjacent channel or co-channel interference in an input signal, and b) filtering the input signal in accordance with the interference to provide an output signal.

2. A method according to claim 1, wherein step b) comprises applying a threshold to the input signal to determine a level of interference, the output signal being produced in accordance therewith.

3. A method according to claim 2, further comprising the step of producing at least one signal component, the output signal comprising said at least one signal component or a sum of said signal components.

4. A method according to claim 3, further comprising selecting the signal components for the output signal in accordance with the level of interference.

5. A method according to claim 3, wherein the number of signal components is produced in accordance with the level of interference.

6. A filter arrangement comprising at least two elements arranged to contribute to the filtration of a signal, each element performing a number of gate switches per second, and selection means arranged to selectively alter the contribution to the filtration of the signal from at least one of the elements to alter the number of gate switches per second.

7. A filter arrangement according to claim 6, wherein the alteration of the number of gate switches per second comprises a reduction in the number of gate switches per second.

8. A filter arrangement according to claim 6 or 7, wherein the selection means is arranged to selectively remove at least one of the elements.

9. A receiver having a filter arrangement according to any of claims 5 to 8, the receiver further comprising interference determining means for determining the presence of adjacent channel or orthogonal co-channel interference, the selection means operating in accordance with the determination of the interference determining means.

10. A mobile terminal having a receiver according to claim 9.

11. A filter arrangement substantially as hereinbefore described with reference to Figures 3 to 6 of the accompanying drawings.