GB2277218A - Wiener-like filter for cellular radio - Google Patents

Abstract

A Wiener filter can be applied to give optimum estimates of the complex fading signal characteristic from noisy measurements. The performance of a Wiener filter is only marginally degraded if groups of adjacent coefficients are set to the same value, provided that the Wiener filter produces frequent outputs. Apparatus is provided for implementation of a filter in which sets of adjacent taps have the same value. This results in reduced hardware complexity. <IMAGE>

Description

APPARATUS FOR USE IN EQUIPMENT PROVIDING A DIGITAL RADIO LINK BETWEEN A FIXED AND MOBILE RADIO UNIT The present invention relates to apparatus for use in equipment providing a digital radio link between a fixed and a mobile radio unit.

Equipment for providing such a radio link is described in UK Application no 9304901.3 and is incorporated herein by reference thereto. This application describes the use of 'Wienerlike' filters for providing good estimates of the amplitudes of the Inphase, I and Quadrature phase, Qcomponents of, for example, a pilot signal. In the case of a down link (base station to mobile station) of a CDMA cellular mobile radio system, a conventional approach is for the base station to transmit the pilot signal which provides a carrier reference to all of the mobiles affiliated to that base station. This pilot signal is transmitted in a form of a long spread spectrum sequence. Because the sequence is not data modulated, the sequence is known, and the mobile receiver is at liberty to use an integration time constant prior to the 'Wienerlike' filtering which extends beyond the current time.This permits a symmetrical filter structure to be used.

A 'Wiener-like' filter is implemented as a finite impulse response (FIR) filter and because it covers generally a wide integration interval it would typically consist of many taps, perhaps as many as forty or a hundred. In implementation terms this is undesirable because it leads to the need for a large number of multiplication operations. However, the correlation of the signal over the period of the filter is relatively large and so it is possible to simplify the filter by making adjacent groups of filter tap coefficients take identical values.

The object of the present invention is to provide a hardware architecture which optimally exploits the reduction in complexity through having groups of equal tap coefficients.

According to the present invention there is provided apparatus for use in equipment providing a digital radio link between a fixed and a mobile radio unit, said apparatus comprising a first shift register having an input line for receiving an input signal, summator means having a first input connected to the input line and a second input connected to an output stage of said first shift register means, said summator means having an output connected to an input of a second shift register and to a first input of at least one multiplying means arranged to receive at a second input thereof a weighted coefficient signal, such that the coefficient gives the apparatus the properties of a 'Wienerlike' filter, said second shift register having at least one output stage arranged to apply to said first input of the same or a different multiplying means the output signal from that stage, said multiplying means being arranged to generate an output signal.

An embodiment of the present invention will now be described with reference to the accompanying drawings, in which; FIGURE 1 shows a multi-sampled integrate and dump filter feeding Wiener filter, FIGURE 2 shows a simplified multi-sampled integrate and dump filter feeding Wiener filter, FIGURE 3 shows a simplified filter structure, FIGURE 4 shows a multiple Wiener filter, FIGURE 5 shows various sampling off sets, and FIGURE 6 shows indexing for an equal coefficient filter.

Referring to Figure 1, a block diagram of a multi-sample Wiener filter is shown. An input signal received on input line 2 is connected to a first shift register 4 and to a first input of a summator circuit 6 which keeps a value equal to the sum of the contents of the shift register 4 at all times. The final stage of the shift register 4 has its output connected to a second input of the summator circuit 6. The output of the summator circuit 6 is connected to an input of the second shift register 8, and also to a first input of a multiplier 10. Each successive eighth stage of the shift register 8 has that stage connected to a first input of a multiplier circuit 12, 14, 16, 18 respectively. Each multiplier circuit has a second input and each second input receives a respective weighting coefficient.The multiplier circuit 14 receives a coefficient ao, multiplier circuit 12 receives a coefficient a-1, multiplier circuit 10 receives a coefficient a-2, multiplier circuit 16 receives a coefficient al and multiplier circuit 18 receives a coefficient a2. The output of each multiplier is connected to a respective input of a adder 20 which generates filter output signal.

Assuming that the shift register 4 is initialised with zero in all locations, then following the first eight clock cycles, the summator circuit 6 will contain the integration over a period equal to eight times the estimate update period. From then on, subsequent clock cycles will update the contents of this register.

The above described architecture reduces the number of four quadrant linear multiplications required. In the example shown in Figure 1, the overall filter 4 and 8 has a span of 40 samples but only five multiplications are required for each output sample. The number of additions per output sample, counting a subtraction as equivalent to an addition is seven. More generally the number of additions is two greater than the order of the simplified filter.

For the symmetrical filter a further saving can be obtained by exploiting the fact that the coefficients are symmetrical (an = a-n). This illustrated in Figure 2. It will be appreciated that Figure 2 is similar to Figure 1 and therefore like elements have been given the same designation. It will be seen from Figure 2 that the requirement of the two multipliers 10 and 12 of Figure 1 are not necessary because the output signals from the respective positions along the shift register are fed to a respective adder circuit 22 and 24. The adder circuits 22 and 24 also receive on a second input thereof the signals read from the relevant positions of the shift register which would have gone directly to the multipliers 16 and 18 as shown in Figure 1. The output of the adder 22 and 24 are fed directly to a input of the multipliers 16 and 18 respectively.As in Figure 1, the outputs of the multipliers 14, 16, 18 are fed to a adder 20 which generates an output signal.

With reference to Figure 3, it can be seen that the final simplified filter structure can be reduced by a further multiplication. Again, the elements that are identical to Figure 2 have been given the same numerical designations. It will be seen that the adder 24 now receives an input as before from the output of the summator circuit 6 and also an input from the final stage of the shift register 8. The output of the adder 24 is fed to an input of the multiplier 18 which also receives a weighted input ai/a0.

The output of the multiplier 18 is connected to the adder 20. The adder 20 receives a further input signal from the sixteenth stage of the shift register 8. The adder 20 generates an output signal as described before. To use the filter as described above with reference to Figure 3 to suit different vehicle speeds it is only necessary to alter the coefficient ai/a0.

Moreover, all calculations up to the final weighting and summation for the purpose of a diversity combiner are common for all speeds. The simpler solution to applying the optimum filter might be to apply all three filters in parallel and select the output which yields the best performance, as shown in Figure 4. Again, like elements have been given the same designation, it can be seen from Figure 4 that the output of the adder 24 is not only applied to the input of a multiplier 18 it is also applied to an input of two further multipliers 26 and 28. The output of the multipliers 18, 26 and 28 are connected to an input of a respective adder 20, 30, 32 and the multipliers each receive at a second input an appropriate weighting al/aO indicative of the range of speed to which the filter is to be responsive.The sixteenth stage of the shift register 8 is applied to a second input of the adder 20, 30 and 32.

For example, the output of the adder 20 may be indicative of the speed range 200 to 300 miles an hour and the coefficient ai/a0 is minus 0.09348/1.0877 for a 20 kbps and a signal to noise ratio of OdB. The output of the adder 30 may be indicative of a medium speed output in the range of 100 to 200 miles an hour and the ai/a0 coefficient is 0.99434/0.9737. The output of the adder 32 may be indicative of a low speed output in the speed range 0 to 100 miles an hour and the ai/a0 coefficient is 0.2042/0.6007.

The overall structure of Figure 1 is equivalent tda single finite impulse response filter (FIR) in which groups of adjacent coefficients are equal. The mean square error will depend upon the time difference between the instant for which the sample is used and the nominal timing of the estimate. Figure 5 illustrates the sampling offsets for three different cases. Sample A shows the times when the signal is sampled (ie. the bit rate - every 50 llsecs in this example). Sample B shows the case where the sample rate for the channel estimate is the same, indicating zero timing error. Sample C shows the channel estimate provided once for every two signal samples. Here the nominal timing of the channel estimate has been offset so that the timing error is always equal to either plus or minus 0.5 signal samples.Sample D shows the estimate provided only once every four signal samples. Here there are two offset errors, +0.5 samples and +1.5 samples. Since demodulation errors tend to be associated with the worst case effects rather than average effects, the figure of +1.5 samples will be taken to apply.

Thus, by evaluating the performance of the combined filtering with time offsets of 0, 0.5, 1.5, one can determine the minimum acceptable rate at which channel updates are required.

Independently, the duration of the integrate and dump part of the filtering can also be evaluated to determine the absolute minimum complexity filtering which can be used.

Determination of filter coefficients with arbitrary groups of adjacent coefficients equal will now be described.

Consider a filter in which contiguous groups of coefficients take the same value. Figure 6 shows such a filter with coefficients an applying for all samples from sn to Sn+1-1, where s is a vector of indices.

In the filter shown in Figure 6, sl is 3, s2 is 8, s3 is 14 and s4 is 20. This illustrates a very general case where the lengths of equal coefficient groups may differ. More usually Sn+l - sn = sm+l - sm for all m and n from 1 to k, where k is the number of equal coefficient groups. However, the theory developed hereinafter allows for the general case. Moreover, Figure 6 illustrates the fact that prediction steps other than one may be considered (3 in the example). Considering a one step predictor Si =1.

The equation for this type of filter is:

The mean square error,

can be shown to be:

Differentiating with respect to the aj s and setting to zero yields the normal equations:

then the above equation simplifies to:

It will be appreciated by those skilled in the art that variations from, and modifications to, the above described apparatus are possible which fall within the spirit and scope of the present invention. For example the theory described with reference to Figure 6 may be extendible to cope with filters where some input samples within the overall support interval are unavailable.

Claims (8)

1. Apparatus for use in equipment providing a digital radio link between a fixed and a mobile radio unit, said apparatus comprising a first shift register having an input line for receiving an input signal, summator means having a first input connected to the input line and a second input connected to an output stage of said first shift register means, said summator means having an output connected to an input of a second shift register and to a first input of at least one multiplying means arranged to receive at a second input thereof a weighted coefficient signal, such that the coefficient gives the apparatus the properties of a 'Wienerlike' filter, said second shift register having at least one output stage arranged to apply to said first input of the same or a different multiplying means the output signal from that stage, said multiplying means being arranged to generate an output signal.

2. Apparatus as claimed in claim 1, wherein a plurality of multiplying means are provided each having the first input connected to a respective output stage of the second shift register, the output stages being equally spaced along the second shift register.

3. Apparatus as claimed in claim 1, wherein a plurality of multiplying means are provided each having the first input connected to a respective output stage of the second shift register, the output stages being unequally spaced along the second shift register.

4. Apparatus as claimed in claims 1, 2 or 3, wherein the output of each multiplying means is connected to an adder circuit arranged to provide a signal at an output thereof.

5. Apparatus as claimed in any preceding claim, wherein each shift register output stage may be connected to a further adder, the output of which is connected to the first input of said multiplying means.

6. Apparatus as claimed in claim 5, wherein a single output stage is connected to the further adder, the output of which is connected to said multiplying means which, at a second input thereof, receives a weighted input signal ai/a0.

7. Apparatus as claimed in any preceding claim, wherein a channel estimate is determined for each signal sample, or once every two signal samples, or once every four signal samples, or once every arbitrary number.

8. Apparatus substantially as hereinbefore described with reference to the accompanying drawings.