GB2319363A - Monitoring signals and generating interrupts - Google Patents

Abstract

The electronic circuit 10 for monitoring logic lines 12 and generating an interrupt signal comprises a latch 14 having a first array of input ports 18 which receive input signals, from the logic lines 12, and a first array of output ports 20. A comparator 24 has a first set of comparator input ports 26 coupled to the array of output ports 20 of the latch 14 and a second set of comparator input ports 28 coupled to the logic lines 12. The comparator 24 compares first and second comparator input ports and provides an interrupt signal when a difference exists between the inputs. The comparator can be constructed from a cascadable address decoder.

Description

ELECTRONIC CIRCUIT AND METHOD OF OPERATION FOR MONITORING SIGNALS AND GENERATING INTERRUPTS Field of the Invention This invention relates to the generation of interrupt request signals.

The invention is applicable to, but not limited to, the generation of interrupt request signals in microprocessor controlled circuits.

Background of the Invention A large number of electronic circuits are now controlled by microprocessor units. Such microprocessors are used for a variety of purposes, for example, controlling the inter-operation between elements or sub-circuits, or for ensuring that particular input or output signals are delivered to the desired element ports or sub-circuits. A further use for a microprocessor is in monitoring the status of particular logic lines in electronic circuits and providing specific outputs in response to changes monitored in those logic lines.

A microprocessor system in general is used when control of input output signals is required. Specific input status's will produce software related output reactions. Typical systems are used for process controls, engine controls, motor management in cars, building alarm systems and so on. The inputs can be sensor signals such as temperature switches, movement sensors, door/ window alarm switches or pressure sensor signals. In response to these sensor signals the microprocessor may deliver specific output signals, for example siren control, break control in cars, engine controls.

With the ever increasing complexity associated with microprocessor control systems, standard operational tasks performed within electronic circuits, as mentioned above, are controlled by the microprocessor monitoring an ever increasing number of circuit or element inputs output logic lines. As such, there is a need to increase the parallel nature of such a monitoring processes.

A typical parallel-function requirement would be to process external binary parallel signals. To obtain this external input information, the processor would have to periodically poll each of the parallel input lines to look for a status change. Such a polling operation is very time consuming and hence inefficient. To avoid this polling, the operation may be designed to be event driven, by use of an interrupt signal, where the processor will only react and read the inputs when a status change has occurred. This is particularly advantageous where the parallel logic lines are used for alarm purposes, and as such will only, if ever, be activated infrequently.

Currently, a circuit designer would have an option of interconnecting a series of basic logic gates to provide a circuit that could perform monitoring of a number of control logic lines and provide a triggered output. Such an approach can be complex, and is not particularly flexible, when during the design development, modification is required to monitor additional logic lines to those originally planned.

One device available to provide a parallel monitoring operation, with a trigger output, is a Valvo PCF8754A remote input output expander chip.

This chip allows concurrent monitoring of eight logic lines and provides a triggered output when any of these logic lines changes its status value.

The Valvo chip is relatively expensive, limited to the monitoring of only eight logic lines and is controlled by a serial I2C bus, which means that time consuming driver routines have to be used. Hence, processor performance is degraded. A further disadvantage associated with such a prior art arrangement is that the device is non-cascadable for applications that require monitoring of more than eight lines. Alternative Application Specific Integrated Circuits (ASICs) could be used, but require special design tools and would be a particularly expensive solution. Therefore, it is desirable to find a less expensive, simplified and improved alternative.

This invention seeks to provide an improved monitoring and interrupt request generator, and method of operation therefor.

Summarv of the Invention In a first aspect of the present invention, an electronic circuit for monitoring logic lines and generating an interrupt signal is provided. The electronic circuit for monitoring logic lines includes a first latch having a first array of input ports such that at least one first input port of the first array of input ports receives the first input signal and a first array of output ports such that at least one first output port is operably coupled to the at least one first input port of a comparator. A comparator is provided having a first set of comparator input ports respectively operably coupled to the first array of output ports, such that a first comparator input port is operably coupled to the at least one first input port of the first latch, and a second set of comparator input ports such that at least one second comparator input port of the second set of comparator input ports receives the first input signal. The comparator compares the first and second comparator input ports and provides an interrupt signal when there exists a difference between the at least one first comparator input port and the at least one second comparator input port. - In this manner, the activation of an intermittent alarm signal is monitored by recording a status change on the latch. When the corresponding output port of the latch is compared with the current status of the alarm logic line, a difference will be recognised and an interrupt signal subsequently generated. Advantageously, there is no need for regular polling of the alarm logic lines to determine when an alarm signal is generated, thereby significantly reducing processing time associated with such techniques.

In the preferred embodiment of the invention, the comparator is a cascadable address decoder. Preferably the electronic circuit is a cascaded arrangement further including a second latch having a second array of input ports and a second array of output ports. A second comparator has a third set of comparator input ports respectively operably coupled to the second array of output ports and a fourth set of comparator input ports operably coupled to the second array of input ports.

In this manner, the comparator compares respective third and fourth comparator input ports to provide an interrupt signal when there exists a difference between the third and fourth comparator input ports, as per the first comparator arrangement described herein before. Such an arrangement provides for an indefinite number of logic lines to be monitored concurrently, thereby providing desirable flexibility to the designer when incorporating such self-check procedures and circuitry.

In a further preferred feature of the invention, the electronic circuit further includes a retriggerable monostable operably coupled to at least the first latch and first comparator for latching, for example, the status values on the first array of input ports of the first latch to the first array of output ports, when receiving an interrupt signal from the first comparator.

Advantageously, any interrupt signals that are generated are used to automatically latch input status values to output status values of the monitoring latch circuitry, such that the latches are then able to monitor subsequent alarm activations.

In a second aspect of the present invention, a method of generating an interrupt signal in an electronic circuit is provided. The electronic circuit includes a first latch having an array of input ports and an array of output ports operably coupled to a first set of input ports of a comparator, the comparator having a second set of input ports operably coupled to the array of input ports. The method includes the steps of receiving a first input signal at an input port of the first array of input ports; waiting for a latch signal to latch the status change value on a first input port of the - comparator to a corresponding first output port; meanwhile, receiving the first input signal at a second input port of the second set of input ports of the comparator; comparing the status of the first and second input ports of the comparator; and providing an interrupt (latch) signal when there exists a difference between the first input port and the second input port.

In the preferred embodiment of the invention when the electronic circuit further includes a retriggerable monostable operably coupled to the first latch and first comparator, the method further includes the steps of receiving an interrupt signal at the retriggerable monostable from the first comparator; and providing a latch signal to the array of input ports of the first latch.

A preferred embodiment of the invention will now be described, by way of example only, with reference to the drawings.

Brief Description of the Drawings FIG. 1 is a block diagram of an interrupt generating circuit according to a preferred embodiment of the invention.

FIG. 2 is a flow chart of an interrupt generating circuit, according to the preferred embodiment of the invention.

Detailed Description of the Drawings Referring first to FIG. 1, block diagram of an electronic circuit 10 for generating an interrupt signal, according to a first aspect of the preferred embodiment of the invention, is shown. The electronic circuit 10 includes a number of binary input lines 12. A first latch 14 has a first array of input ports 18 corresponding to the binary input lines 12, and a first array of output ports 20. A cascadable address decoder, operating as a comparator 24 function, is provided. The comparator has a first set of input ports 26, respectively operably coupled to the first array of output ports 20 of the first latch 14, and a second set of input ports 28, operably coupled to the binary input lines 12. It is within the contemplation of the invention that additional input monitoring and interrupt generation elements are cascadably arranged to first latch 14 and first comparator 24, for example second latch 36 and second cascadable address decoder 38, to provide the cascadable feature of the preferred embodiment of the invention. Outputs from each comparator (24, 38) are input to a retriggerable monostable circuit 40.

In operation, an alarm input signal is input to one of the binary input lines 12. A first input port 16 of the first latch 14 receives the alarm input signal, and waits for an interrupt/ latch signal to cause the array of input port values to be transferred (latched) to the array of output ports. A second input port 32 of the second set of input ports 28 of the comparator simultaneously receives the alarm input signal. Whilst waiting for an interrupt, or latch signal to initiate the status change, the first output port 22, and thus a corresponding second input port 32 of the comparator 24, will still contain the previous status value. Hence, before the interrupt signal triggers the status change, the comparator 24 compares the first input port 30 and second input port 32 holding the alarm input signal. The comparator then provides an interrupt signal when there is a difference between the status value of the first input port 30 and the respective second input port 32, that holds the alarm input signal on the second input port 32. The old status is maintained on the first output port 22 of the first latch 14 until the interrupt signal is generated and applied to the first latch 14.

The first latch 14 transfers each input port status to each respective output port on application of the interrupt pulse. Consequently, these status values become the old status values for subsequent comparisons by the comparator.

The interrupt signal output from the comparator 24 is input to the retriggerable monostable circuit 40. The retriggerable monostable circuit 40 provides the interrupt/ debounced latch signal to the first latch 14 in order to transfer input status values on the latch input ports to the output ports. A retriggerable monostable circuit is used to eliminate the effect of any bouncing flickering of the input signal, thereby avoiding production of additional and unnecessary interrupt signals. In the preferred embodiment of the invention, there is only one interrupt pulse during the debouncing time, for example 25 ms after the alarm signal has been received. There is always an interrupt generated even if the status value is changed back to the previous status value in order to ensure that no alarm signal will be missed.

Furthermore, it is within the contemplation of the invention that additional input monitoring of alarm signals and subsequent interrupt signal generation is available by cascading latch and comparison elements of the electronic circuit 10.

In the preferred embodiment of the invention, the latches are address decoders. Address decoders are typically used to detect a specific input pattern which then generates a chip select (CS) signal. However, in this application the address decoder is used in a novel way to monitor all inputs for status changes and not just for a specific logic pattern. The address decoder is used to monitor intermittent alarm signals in the electronic circuit 10, and to subsequently create an interrupt signal to indicate that an alarm signal has been triggered. The circuit allows a large number of parallel logic lines to be monitored in this manner, with intermittent and/or irregular alarm signals being caught. This arrangement negates the need for alarm logic lines to be constantly monitored to determine whether an alarm signal has been activated.

Referring now to FIG. 2, a flow chart of an interrupt generating circuit, according to a second aspect of the preferred embodiment of the invention, is shown. The electronic circuit has a first latch that includes an array of input ports and an array of output ports operably coupled to a first set of input ports of a comparator. The comparator has a second set of input ports operably coupled to the array of input ports of the first latch.

The method includes the steps of receiving a first signal, for example an alarm input signal, at an input port of the first array of input ports, as shown in step 102. The first signal is also received at a second input port of the second set of input ports of the comparator, as shown in step 106. The comparator compares the status of the first and second input ports of the comparator, as in step 108 and provides an interrupt signal, as shown in step 110, when there exists a difference between the first input port andt the second input port. A latch signal is automatically provided to the array of input ports of the first latch, when an interrupt signal has been generated, as in step 112, to latch the input ports of the first latch to the output ports.

A status change value is then latched from the input port to a respective output port of the latch, as in step 114, in response to the input signal, thereby providing a status change value on the first input port of the comparator.

It is also within the contemplation of the invention that microprocessor control is not a specific requirement and that subsequent latches and comparator elements may be used to achieve the same effect, by monitoring additional logic lines.

Advantageously, the electronic circuit described herein provides an arrangement where it is possible to cascade monitoring elements due to the I(A=BSInput of the comparator chip. Therefore, the number of inputs is not limited, creating an advantage over serial bus type solutions. The circuit offers the feature of being self resetting after power up and delivers a start-up interrupt. Implementation of the circuit, using the address decoder and comparator arrangement is inexpensive due to the wide commercial availability of such Integrated Circuits (ICs). Furthermore, the circuit has a debounce feature as described.

Thus, an improved interrupt request generator, and method of operation is provided which alleviate at least some of the disadvantages associated with prior art arrangements.

Claims (8)

Claims

1. An electronic circuit for monitoring logic lines and generating an interrupt signal comprising: a first latch having a first array of input ports such that at least one first input port of the first array of input ports receives a first input signal; a first array of output ports such that at least one first output port is operably coupled to the at least one first input port; a comparator having a first set of comparator input ports respectively operably coupled to the first array of output ports such that a first comparator input port is operably coupled to the at least one first input port of the first latch; and a second set of comparator input ports such that at least one second comparator input port of the second set of comparator input ports receives the first input signal, wherein the comparator compares the first and second comparator input ports and provides an interrupt signal when there exists a difference between the at least one first comparator input port and the at least one second comparator input port.

2. The electronic circuit according to claim 1, the electronic circuit further comprising: a second latch having a second array of input ports and a second array of output ports; and a second comparator having a third set of comparator input ports respectively operably coupled to the second array of output ports and a fourth set of comparator input ports operably coupled to the second array of input ports.

3. The electronic circuit according to claim 1 or 2, wherein the comparator is a cascadable address decoder.

4. The electronic circuit according to claims 1, 2 or 3, further comprising a retriggerable monostable operably coupled to at least the first latch and first comparator for latching the first array of input ports of the first latch to the first array of output ports on receipt of an interrupt signal to provide a status change value on a first output port responsive to the first input signal.

5. A method of monitoring logic lines and generating an interrupt signal in an electronic circuit having a first latch including an array of input ports and an array of output ports operably coupled to a first set of comparator input ports of a comparator, the comparator having a second set of comparator input ports operably coupled to the array of input ports, the method comprising the steps of: receiving a first input signal at an input port of the first array of- input ports; receiving the first input signal at a second comparator input port of the second set of comparator input ports; comparing an original status value of the first comparator input port with a status value of the second comparator input port; and providing an interrupt signal when there exists a difference between the first comparator input port and the second comparator input port.

6. The method of generating an interrupt signal in an electronic circuit according to claim 5, wherein the electronic circuit further comprises a retriggerable monostable operably coupled to at least the first latch and first comparator, the method further comprising the steps of: receiving an interrupt signal at the retriggerable monostable from the first comparator; and providing a latch signal to the first latch; latching the first array of input ports to the first array of output ports thereby providing a status change value on a respective output port of the latch in response to the first input signal.

7. An electronic circuit substantially as hereinbefore described with reference to, or as illustrated by, figure 1 of the drawings.

8. A method of generating an interrupt signal substantially as hereinbefore described with reference to, or as illustrated by, figure 2 of the drawings.